BU2 SYSTEM DIAGRAM. AMD Griffin S1G2 Processor. Lion Sabie. 638P (upga)/35w PAGE 4,5,6,7 HT LINK NORTH BRIDGE RS780M. 21mm X 21mm, 528pin BGA

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1 P STK UP LYER : TOP LYER : S LYER : IN LYER : SV LYER : IN LYER : IN LYER : S LYER : OT X LN Marvell PIE-LN 00T/0 (0/00/GagaLN) PGE RJ/RJ oard PGE SYSTEM HRGER(ISL) PGE 0 SYSTEM POWER ISLIRZ-T PGE PU ORE ISL PGE VP +.V N +.V(MX) PGE R II SMR_VTERM.V/.VSUS(TPSREGR) PGE ISHRGE./././.V PGE X Express ard (NEW R) PGE ST - H PGE 0 ST - -ROM PGE 0 E-ST G-Sensor Keyboard IR RII-SOIMM RII-SOIMM LISL0Q Touch Pad Kill SW X PGE PGE Mini PI-E ard H-V (ROSON/TV) PGE NN FLSH R PGE PGE 0 VR (UIO ONN) PGE ST 0M LP WINON K U SYSTEM IGRM PGE PGE PGE PGE PGE RII /00 MHz RII /00 MHz X ST 0M PI-E Mini PI-E ard (Wireless LN) IE/ PGE ST0 0M SMUS WPLG P (upg)/w PGE,,, NORTH RIGE mm X mm, pin G PIE X PGE,0, SOUTH RIGE PGE M Griffin SG Processor HT LINK RS0M S00 Lion Sabie mm X mm, pin G.W(Ext).W(Int) PGE,,,, US.0 US.0 Ports X M/FM TUNER ONNETOR PGE M/FM TUNER Module PGE zalia PU THERML SENSOR PGE Felice PI US / MHz ONEXNT X0 HMI/E PGE LVS PGE 0,0, udio mplifier G Webcam PGE 0, PGE X PGE PGE HP mplifier G PGE PGE PU_LK RT PGE LE river PGE NGFX_LK NGPP_LK SLINK_LK PGE LE Panel PGE PMI ontroller 0 PGE PMI PGE SSR_LK Fingerprint IEEE ONN O OZT PGE LOK GEN ISLPRS0KLFT PGE.MHz SLGSPVTR RTM0N- PI ROUTING TLE ISEL REQ0# / GNT0# Mini PI-E ard x H V EOER x luetooth PGE PGE Memory ardreader PGE INTERUPT INTE# PGE, 0 EVIE OZT REQ# / GNT# INTF# 0 NEW R PGE FN PGE FLSH SPI PGE igital MI PGE, UIO ONN (HP/ MI) PGE SPEKER onn PGE PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom LOK IGRM ate: Wednesday, January 0, 00 Sheet of

2 INEX PGE# ESRIPTION SHEMTI LOK IGRM SYSTEM INFORMTION NOTE IN V/VPU Power Sequence 0 0 LOK GENERTOR_SLGSP SG HT I/F / SG RII MEMORY I/F / SG TRL & EUG / SG PWR & / R SOIMMS: / HNNEL RS0/RS0-HT LINK/PIE I/F / RS0/RS0-SYSTEM I/F / NSWON# NSWON# S_ON/S RSMRST# PIE_WKE# SUS S00 SM US S00 SMUS SMUS Function efine SMLK0 R / R THER / LOK GEN (+V) SMT0 SMLK Mini ard/new ard (+VS) SMT SMLK HMI E (+VS) SMT RS0/RS0-POWER/ S00-PIE/PI/PU/LP / S00-PI/GPIO/US / S00-PI/GPIO/US / SUS SUSON MINON K(E) SM US 0 S00-PWR/EOUPLING / S00-STRPS & PWRG L/LE PNEL/LI/MER HMI/HMI-E(RF) RT & G-SENSOR(LISL0) ST H/O & EST/US PMI(0) -OPTION VR_ON PU_ORE VRM_PWRG._ON N_ORE K SMUS MLK MT N_MLK N_MT N_MLK N_MT SMUS Function efine TTERY (+VPU) PU THER / SENSOR/E (+V/PU) HMI E / TOUH SEN(+VS) OZT(IN/) HWPG MINI R & NN FLSH R NEW R & RJ OR/EEP TP/FP/T/P/FELI/MM ONN EPWROK N_PWRG_IN ONEXNT(X00)/SPK/MP S_PWRG_IN JK/VR/FM/MI/M/MPLIFIER E(K)-WPP/WP KEYOR/LE/KILL SW/HOLE PU LK IN PU RESET 0 HRGER (ISL) PU POWER OK SYSTEM V/V (ISL) M GRIFFIN (ISL) PU_LTSTOP# +N_ORE (RT0) R.V(TPS) ISHRGE (.V/.V) PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom SYSTEM INFORMTION ate: Thursday, November 0, 00 Sheet of

3 LK_GEN_SLGSP 0 +V +V_LK_V +.V +.V_LK_VIO L L K0HS00 K0HS00 u/0v_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ u/0v_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ ISLPRS0 P/N : SLGSP P/N : LSP000 RTM0N- P/N : L U lock chip has internal serial terminations for differencial pairs, external resistors are reserved for debug purpose. Place within 0." of LKGEN R +V +V_LK_ L K0HS00.u/.V_ +V_LK_V 0 VOT VSR VTIG VS_SR VST VPU VHTT VREF V 0 PUK_0T PUK_0 0 TIG0T TIG0 TIGT TIG PULKP_R PULKN_R NGFX_LKP_R NGFX_LKN_R RP RP 0_PR_ 0_PR_ */F_ PU_LKP (,) PU_LKN (,) NGFX_LKP (0) NGFX_LKN (0) To PU To N +.V_LK_VIO 0 G_XIN p/0v_ Y.MHZ G_XOUT p/0v_ G_XIN G_XOUT Rev: /0 ahnge 0/ Load apacitance For Matching rystal VSR_IO0 VSR_IO VTIG_IO VS_SR_IO VPU_IO OT SR0 SR TIG S_SR ST PU HTT REF X X QFN S_SR0T S_SR0 S_SRT S_SR SR0T SR0 0 SRT SR SRT SR SRT SR SRT SR SRT/STT SR/ST SRT/M_SS SR/M_NS SLINK_LKP_R SLINK_LKN_R SSR_LKP_R SSR_LKN_R NGPP_LKP_R NGPP_LKN_R LK_PIE_NEW_R LK_PIE_NEW#_R LK_PIE_MINI_R LK_PIE_MINI#_R LK_PIE_MINI_R LK_PIE_MINI#_R LK_PIE_LN_R LK_PIE_LN#_R T0 T T T RP RP RP RP RP RP RP 0_PR_ 0_PR_ 0_PR_ NGPP_LKP NGPP_LKN NEW@0_PR_ 0_PR_ LK_PIE_MINI LK_PIE_MINI# 0_PR_ 0_PR_ LK_PIE_LN LK_PIE_LN# S_REFLKP (0) S_REFLKN (0) SSR_LKP () SSR_LKN () T0 T0 LK_PIE_NEW (,) LK_PIE_NEW# (,) LK_PIE_MINI (,) LK_PIE_MINI# (,) To N To S To New ard To Mini PIE Slot To Mini PIE Slot To LN ontroller N LOK INPUT TLE N LOKS RX0 HT_REFLKP 00M IFF HT_REFLKN 00M IFF RS0 00M IFF 00M IFF (,) PLK_SM (,) PT_SM SMLK SMT HTT0T/M HTT0/M NHT_REFLKP_R NHT_REFLKN_R RP 0_PR_ HT_REFLKP (0) HT_REFLKN (0) To N REFLK_P REFLK_N M SE (.V) N M SE (.V) vref LK_P# P# MHz_0 LK_M_US_R R _ LK_M_US () To S GFX_REFLK 00M IFF 00M IFF(IN/OUT)* New ard LKREQ# +V_LK_V R R (,) NEW_LKREQ#.K_ NEW_LKREQ#.K_ LK_P# NEW_LKREQ# 0.u/0V_ T T T T LKREQ0# LKREQ# LKREQ# LKREQ# LKREQ# SLGSP T0 T T T T 0 T T T T T REF0/SEL_HTT REF/SEL_ST REF/SEL_ SEL_HTT SEL_ST SEL_ R00/R00 (value may change) RX0 RS0 R R N_OS /F_ 0./F_.V.R/0R.V R/0.R EXT_N_OS (0) RES HIP. /W +-%(00) --> S0F RES HIP 0 /W +-%(00)L-F --> S0F RES HIP /W +-%(00) --> SF00 RES HIP 0. /W +-%(00) --> S00F To N GPP_REFLK GPPS_REFLK 00M IFF 00M IFF N or 00M IFF OUTPUT 00M IFF +V_LK_V FOR EXTERML/INTERNL LOK R.K_ R *.K_ R0.K_ SEL_ST SEL_HTT SEL_ R.K_ SEL_HTT SEL_ST SEL_ 0 0* MHz.V single ended HTT clock 0* 00 MHz differential HTT clock * 00 MHz non-spreading differential SR clock 00 MHz spreading differential SR clock MHz and M SS outputs 00 MHz SR clock LK_PIE_MINI RP0 LK_PIE_MINI# 0_PR_ LK_PIE_LN RP LK_PIE_LN# 0_PR_ Place lose to rivers Side PIE_LK_MINI (,) PIE_LK_MINI# (,) PIE_LK_LN (,) PIE_LK_LN# (,) * default PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom LOK GENERTOR_SLGSP Thursday, July, 00 ate: Sheet of

4 E F G H E E 0 0 E E E E0 E E E E E E E E F E F E0 F0 E F E F E F E F E F E E E E F F F F F F0 F F F F F F F F F F F G G G G G G G G G G G G G H G0 H0 G H G G G G G G H H H H H H0 H H H H H H H H H H H H H H H H J K J K J K J K J K J J0 J J J J J J J J J J0 J J J J K0 K K K K K K K K K0 K K K J K J K J K J J K K K K K L M L M L L L L L0 L L L L L L L L L L0 L L L L L L L L L M M M M M0 M M M M M M0 M M M N0 N N N N M N M N M N M N M N M N N N N N N N N N0 N N N P P P P P P P0 P P P P P P0 P P P P P P P P P R R R R R R T U R0 T0 U0 R T U R T U R T U R T T T T R T R0 T0 R R R R R R R R R T T T T T T T T T T T T T T T U V U V U U U U U U U U U U0 U U U U U U U U U V V V V V0 V V V V V V V V V V0 V V V V V V V V V W Y W W W W W W W W W W W W W W0 W W W W Y W Y W W W W Y Y Y Y Y Y0 Y Y Y Y Y Y Y Y Y Y0 Y Y Y 0 0 Y Y E E F E E E E0 E E E E E E E E E E0 E E E E E E E E F F F F0 F F F F F F F F F F0 F F F F F F 0 +.V_VLT U VLT_0 VLT_ VLT_ VLT_ HT LINK VLT_0 VLT_ VLT_ VLT_ E E E E +.V_VLT () HT_N_PU H0 () HT_N_PU L0 () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H0 () HT_N_PU L0 () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L E E E F G G G H J K L L L M N N E F F F G H H H K K L M M M N P L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L W W V U U U T R Y W V V V U T T HT_PU_N H0 () HT_PU_N L0 () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H0 () HT_PU_N L0 () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () +.V R 0_ R 0_ +.V_VLT.u/.V_ Place close to socket 0.u/.V_ 0.u/.V_ 0.u/.V_ * If VLT is connected only on one side, one.uf cap should be added to the island side 0P_ 0 0P_.u/.V_ () HT_N_PU_LK_H0 () HT_N_PU_LK_L0 () HT_N_PU_LK_H () HT_N_PU_LK_L J J J K L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L Y W Y Y HT_PU_N_LK_H0 () HT_PU_N_LK_L0 () HT_PU_N_LK_H () HT_PU_N_LK_L () () HT_N_PU_TL_H0 () HT_N_PU_TL_L0 () HT_N_PU_TL_H () HT_N_PU_TL_L N P P P L0_TLIN_H0 L0_TLIN_L0 L0_TLIN_H L0_TLIN_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L R R T R HT_PU_N_TL_H0 () HT_PU_N_TL_L0 () HT_PU_N_TL_H () HT_PU_N_TL_L () SOKET PIN PU G_0_SQ_SG_OEM N PROJET : U Quanta omputer Inc. Size ocument Number Rev SG HT I/F / ate: Thursday, July, 00 Sheet of

5 PU +.VSUS R K/F_ Processor Memory Interface E 0 +SMR_VTERM U +SMR_VTERM R U PLE THEM LOSE MEM:T () MEM_M_T[0..] MEM_M_T[0..] () MEM_M_T0 MEM_M_T0 TO PU WITHIN " 0 W0 K/F_ G VTT 0.u/0V_ MEM_M_T M_T0 M_T0 0 MEM:M/TRL/LK VTT 0 000P_ F MEM_M_T VTT VTT MEM_M_T M_T M_T 0 0 H MEM_M_T VTT VTT MEM_M_T M_T M_T 0 0 G MEM_M_T VTT VTT MEM_M_T M_T M_T 0 G H MEM_M_T R.F_ M_ZP VTT MEM_M_T M_T M_T F0 E H MEM_M_T +.VSUS R.F_ M_ZN MEMZP PU_VTT_SENSE MEM_M_T M_T M_T E0 MEM_M_T PU_VTT_SENSE () MEMZN VTT_SENSE Y0 MEM_M_T M_T M_T E MEM_M_T MEM_M_RESET# MEMVREF_PU MEM_M_T M_T M_T T H W H MEM_M_T RSV_M MEMVREF MEM_M_T M_T M_T E MEM_M_T MEM_M_RESET# MEM_M_T0 M_T M_T MEM_M_T0 () MEM_M0_OT0 T E M0_OT0 RSV_M T MEM_M_T M_T0 M_T0 MEM_M_T () MEM_M0_OT V 0 H MEM_M_OT0 M0_OT MEM_M_T M_T M_T T U W MEM_M_T MEM_M0_OT0 () E MEM_M_OT M_OT0 M0_OT0 MEM_M_T M_T M_T T V W MEM_M_T MEM_M0_OT () F M_OT M0_OT MEM_M_OT0 MEM_M_T M_T M_T Y MEM_M_T M_OT0 T MEM_M_T M_T M_T MEM_M_T () MEM_M0_S#0 T0 G M0_S_L0 MEM_M_T M_T M_T MEM_M_T () MEM_M0_S# U V MEM_M0_S#0 () 0 G PU_M_S_L0 M0_S_L M0_S_L0 MEM_M_T M_T M_T T U0 W MEM_M_T MEM_M0_S# () PU_M_S_L M_S_L0 M0_S_L PU_M_S_L0 MEM_M_T M_T M_T T0 V0 U MEM_M_T M_S_L M_S_L0 T MEM_M_T M_T M_T E0 MEM_M_T MEM_M_T0 M_T M_T MEM_M_T0 () MEM_M_KE0 J J MEM_M_KE0 () 0 E M_KE0 M_KE0 MEM_M_T M_T0 M_T0 MEM_M_T () MEM_M_KE J0 H MEM_M_KE () 0 F M_KE M_KE MEM_M_T M_T M_T MEM_M_T PU_M_LK_H PU_M_LK_H MEM_M_T M_T M_T T N P MEM_M_T PU_M_LK_L M_LK_H M_LK_H T T PU_M_LK_L MEM_M_T M_T M_T N0 R MEM_M_T T E F0 MEM_M_LK_P M_LK_L M_LK_L MEM_M_LK_P MEM_M_T M_T M_T MEM_M_T () MEM_M_LK_P E MEM_M_LK_P () E F MEM_M_LK_N M_LK_H M_LK_H MEM_M_LK_N MEM_M_T M_T M_T MEM_M_T () MEM_M_LK_N F MEM_M_LK_N () G H MEM_M_LK_P M_LK_L M_LK_L MEM_M_LK_P MEM_M_T M_T M_T MEM_M_T () MEM_M_LK_P Y F MEM_M_LK_P () G J MEM_M_LK_N M_LK_H M_LK_H MEM_M_LK_N MEM_M_T M_T M_T MEM_M_T () MEM_M_LK_N F MEM_M_LK_N () E T PU_M_LK_H M_LK_L M_LK_L PU_M_LK_H MEM_M_T M_T M_T P R E MEM_M_T PU_M_LK_L M_LK_H M_LK_H T PU_M_LK_L MEM_M_T0 M_T M_T T P0 R MEM_M_T0 T G H0 M_LK_L M_LK_L MEM_M_T M_T0 M_T0 MEM_M_T () MEM_M_[0..] MEM_M_[0..] () G H MEM_M_0 MEM_M_0 MEM_M_T M_T M_T N P Y MEM_M_T MEM_M_ M_0 M_0 MEM_M_ MEM_M_T M_T M_T M0 N MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T N P MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T M N E MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T M N W MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T L0 L W MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T M N Y MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T L L E MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T0 M_T M_T L M Y0 MEM_M_T0 MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T0 M_T0 K K 0 MEM_M_T MEM_M_0 M_ M_ MEM_M_0 MEM_M_T M_T M_T R T E0 MEM_M_T MEM_M_ M_0 M_0 MEM_M_ MEM_M_T M_T M_T L L F0 MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T K0 L F MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T V W F MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T K J 0 MEM_M_T MEM_M_ M_ M_ MEM_M_ MEM_M_T M_T M_T K J 0 Y MEM_M_T M_ M_ MEM_M_T M_T M_T MEM_M_T MEM_M_T M_T M_T MEM_M_T () MEM_M_NK0 R0 R MEM_M_NK0 () E W M_NK0 M_NK0 MEM_M_T0 M_T M_T MEM_M_T0 () MEM_M_NK R U MEM_M_NK () W M_NK M_NK MEM_M_T M_T0 M_T0 MEM_M_T () MEM_M_NK J J MEM_M_NK () Y M_NK M_NK MEM_M_T M_T M_T F Y MEM_M_T MEM_M_T M_T M_T MEM_M_T () MEM_M_RS# R U MEM_M_RS# () M_RS_L M_RS_L MEM_M_T M_T M_T MEM_M_T () MEM_M_S# T U MEM_M_S# () F M_S_L M_S_L MEM_M_T M_T M_T MEM_M_T () MEM_M_WE# T U MEM_M_WE# () F M_WE_L M_WE_L MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T SOKET PIN MEM_M_T M_T M_T Y MEM_M_T MEM_M_T M_T M_T Y W MEM_M_T MEM_M_T0 M_T M_T E MEM_M_T0 MEM_M_T M_T0 M_T0 F MEM_M_T MEM_M_T M_T M_T F MEM_M_T MEM_M_T M_T M_T MEM_M_T MEM_M_LK_P MEM_M_LK_P M_T M_T () MEM_M_M[0..] MEM_M_M[0..] () MEM_M_M0 E MEM_M_M0 MEM_M_M M_M0 M_M0 MEM_M_M.P_ MEM_M_M M_M M_M E MEM_M_M.P_ MEM_M_M M_M M_M E F MEM_M_M MEM_M_LK_N MEM_M_LK_N MEM_M_M M_M M_M MEM_M_M MEM_M_M M_M M_M E Y MEM_M_M MEM_M_M M_M M_M MEM_M_M MEM_M_LK_P MEM_M_LK_P MEM_M_M M_M M_M Y MEM_M_M M_M M_M 0 MEM_M_LK_N.u/.V_.u/.V_.P_ Place close to PU within 00 mils.u/.v_ +SMR_VTERM.u/.V_ 0.u/.V_ 0.u/.V_.P_ MEM_M_LK_N 0.u/.V_ 0.u/.V_ To SOIMM socket (Far) () () () () () () () () () () () () () () () () MEM_M_QS0_P MEM_M_QS0_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N MEM_M_QS_P MEM_M_QS_N F E F F E F E M_QS_H0 M_QS_L0 M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L SOKET PIN M_QS_H0 M_QS_L0 M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L M_QS_H M_QS_L G H G G G G 0 Y W W W MEM_M_QS0_P () MEM_M_QS0_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () To SOIMM socket (near) +SMR_VTERM P_ 000P_ 000P_ 000P_ 0P_ 0P_ Place close to socket 0P_ 0P_ N PROJET : U Quanta omputer Inc. Size ocument Number Rev ustom SG RII MEMORY I/F / Thursday, July, 00 ate: Sheet of E

6 PU +.V PU POWER-UP 0.U/0V_ *00u/.V_ W/S= mil/0mil PU_LT_RST# PU_LT_STOP# PU_PWRG PU_LT_REQ#_PU 0u/.V_ L 00S_0EGTS_ NH % 00M +.V (,) (,) Rev: 0/ hange to S0 domain save power during S since S. R 00_ R 00_ R 00_ R 00_.u/.V_ 0.u/.V_ 00P_ PU_LKP PU LK PU_LKN 0m +.V_VLT () () () () 0 (0,) 00P_ 00P_ () PU_PWRG PU_LT_STOP# Sideand Temp sense I place them to PU within." R0 R0 PU_V0_RUN_F_H PU_V0_RUN_F_L PU_V_RUN_F_H PU_V_RUN_F_L R /F_./F_./F_ +.V_PU_V_RUN PU_LKIN_P PU_LKIN_N PU_LT_RST# PU_PWRG PU_LT_STOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT PU_HTREF0 PU_HTREF PU_RY PU_TMS PU_TK PU_TRST# PU_TI F F F0 F F E R P F E Y G0 F U V V LKIN_H LKIN_L RESET_L PWROK LTSTOP_L LTREQ_L SI SI LERT_L HT_REF0 HT_REF V0_F_H V0_F_L V_F_H V_F_L RY TMS TK TRST_L TI KEY KEY SV SV THERMTRIP_L PROHOT_L MEMHOT_L THERM THERM VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO M W F W W W Y H G E0 E PU_SV_R PU_SV_R PU_THERMTRIP_L# PU_PROHOT_L# PU_MEMHOT_L# PU_THERM PU_THERM PU_REQ# PU_TO R 0_ R00 0_ H_THRM H_THRM VIO_F_H () VIO_F_L () PU_VN_RUN_F_H () PU_VN_RUN_F_L () route as differential as short as possible testpoint under package (,,) VRM_PWRG PU_THERMTRIP_L# PU THERM +.VSUS R 00_ +.VSUS Q R K_ Q MMT0 FV0N 0 SYS_SHN# () PU_THERMTRIP# () Rev: 0/0 System will Leakage when system into G mode. R R *0_ R 00K_ *0_ Rev: /0 dd 0.u For M PU issue. +V R PU_LT_REQ#_PU 0K/F_0 R Q *FV0N NTR_VREF 0.U/0V_.K/F_ G NTR_VREF R 0_ Q FV0N Rev: 0/ hange to.k +V R.K_ *SHORT_ P PU_LT_RST# PU_LT_RST_HTP# For ebug Only PU_LT_RST# (0,) +.VSUS +.VSUS +.VSUS R R R R R T T T *00_ *00_ *00_ *00_ T T T T T *00_ R 0_ PU_TEST_TSTUP PU_TEST_PLLTEST0 PU_TEST_PLLTEST PU_TEST_YPSSLK_H PU_TEST_YPSSLK_L PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_SINGLEHIN PU_TEST_NLOGIN H0 G E E F E E F TEST TEST TEST TEST_H TEST_L TEST TEST0 TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV J H E F K H H PU_TEST_H_PLLHRZ PU_TEST_L_PLLHRZ PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_H_FLKOUT PU_TEST_L_FLKOUT T T T T T T T T PU_PROHOT_L# +.VSUS R 00_ +.VSUS +.VSUS R Q MMT0 0K_ +.VSUS +V R 0_ R *0K_ M_PROHOT# () PU_PROHOT# () R 0_ PU_LT_REQ# (0) Rev: 0/0 Follow M esign Guide add termination resistor. SOKET PIN R0 R PU FN () VFN +V.u/V_ R 0_ G/Pin- internal pull high (+V) FNPWR =.*VSET U /FON VSET G VO () FNSIG TH_FN_POWER *.0u/V_ +V R0 0K_ N S_ST 0u/V_.0u/V_ SMLERT# FN_ON () () S_SLK NTR_VREF R0 R Q Rev: 0/ hange pull-up Resistors to.k *0_ *0_ *SS_NL/SOT R +.VSUS.K_ R.K_ R *K_ PU_SI PU_SI PU_LERT PU_MEMHOT_L# Reserve Test Port PU_REQ# 00_ PU_TEST0_SNLK PU_TEST_SNEN PU_TEST_TSTUP PU_TEST_SNLK 0K_ Q MMT0 R 00_ R 00_ R 00_ R 00_ R 00_ PU_MEMHOT# (,) +.VSUS Rev:/ 0/0 M PU noise sensitivity be added termination resistor. PU H/W MONITOR +V +V +.VSUS PU_PWRG R 0_ R R *.K_ *0_ PU_PWRG_SVI_REG () HT onnector +.VSUS (,) N_MLK (,) N_MT () PM_THERM# RHU00N0 +V Q Rev: 0/ GMT G Reverse R 0 Ohm For Thermal Sensor issue. Q LM_SM LM_SM R0 *0_ RHU00N0 OVERT# heck E Setting egree R R0 R0 R0 0K_ 0K_ 0K_ 00_ +V_THERM U SLK V S XP SMLERT# LERT# XN THERM_SH# OVERT# MSOP M0 MX,GP,WLG RESS: H 0.u/0V_ H_THRM +V 00P_ H_THRM R R 0_ R *0_ 0K_ Q MMT0 SYS_SHN# *u/v_ +.VSUS +.VSUS PU_SV_R PU_SV_R Serial VI R 0_ R R K_ *0_ R 0_ R R0 K_ *0_ VFIX MOE PU_SV () Serial VI lock PU_SV () Serial VI ata VI Override ircuit SV SV Voltage Output(PU Power) V.V.0V 0.V *0.u/0_ PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO N N 0 0 PU_LT_RST_HTP# KEY *HT ONN PROJET : U Quanta omputer Inc. Size ocument Number Rev ustom SG TRL & EUG / Thursday, July, 00 ate: Sheet of

7 PU 0 UF PU_ORE0 PU VN_ORE +.VSUS UE G V0_ H V0_ J V0_ J V0_ J V0_ J V0_ K V0_ K0 V0_ K V0_ K V0_0 L V0_ L V0_ L V0_ L V0_ L V0_ L V0_ M V0_ M V0_ M V0_ M0 V0_0 N V0_ N V0_ N V0_ K VN_ M VN_ P VN_ T VN_ V VN_ H VIO J VIO K VIO K VIO K VIO K VIO L VIO M VIO M VIO M VIO0 M VIO N VIO SOKET PIN V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ VIO VIO VIO VIO VIO VIO VIO VIO0 VIO VIO VIO VIO VIO VIO VIO P P0 R R R R T T T T0 T T U U U U U V V V0 V V W Y Y V V V V U T T T T R P P P P PU_ORE +.VSUS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS E VSS VSS E VSS VSS E VSS VSS E VSS VSS E VSS VSS0 E VSS VSS E VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS00 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS0 VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS E VSS VSS F VSS VSS F VSS VSS F VSS VSS F VSS VSS0 F VSS VSS F VSS VSS F VSS VSS F VSS VSS F VSS0 VSS H VSS VSS H VSS VSS H VSS VSS H VSS VSS J VSS SOKET PIN J J J0 J J J J K K K K K K K L L L0 L L L L M M M N N N0 N N P P P P P R R0 R R T T T T T T U U U U0 U U U U V V V V V V V W Y Y N PU_ORE0 PU_ORE PU VN_ORE +.VSUS +.VSUS u/.v_ u/.v_ u/.v_ OTTOM SIE EOUPLING +.VSUS EOUPLING ETWEEN PROESSOR N IMMs PLE LOSE TO PROESSOR S POSSILE.u/.V_ 0.u/.V_ u/.v_ u/.v_ 0 u/.v_.u/.v_ 00 0.u/.V_ u/.v_ u/.v_ u/.v_.u/.v_ 0.0u/V_ u/.v_ u/.v_ u/.v_.u/.v_ 0.0u/V_ 0.u/.V_ 0.u/.V_ u/.v_ 0.u/.V_ 0P_ 0 0.0u/V_ 0 0.0u/V_ 0 0.u/.V_ 0.u/.V_ 0P_ 0.0u/V_ 0.u/.V_ 0P_ 0P_ 0 0P_ PROESSOR POWER N GROUN PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom SG PWR & / ate: Wednesday, ecember, 00 Sheet of

8 MEM_M_KE MEM_M0_OT MEM_M_ MEM_M_ MEM_M_NK0 MEM_M_ MEM_M_WE# MEM_M0_S# MEM_M_RS# MEM_M_KE0 MEM_M_S# MEM_M0_S#0 MEM_M_T MEM_M_T0 MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_NK MEM_M_T MEM_M_T MEM_M_NK PT_SM PLK_SM MEM_M_T MEM_M_M MEM_M_M MEM_M0_OT0 MEM_M_M0 MEM_M_M MEM_M_M MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEMHOT_IMM#_ MEM_M_ MEM_M_RESET# MEM_M0_OT MEM_M_ MEM_M_ MEM_M_KE0 MEM_M0_S# MEM_M_RS# MEM_M_WE# MEM_M_KE MEM_M_S# MEM_M0_S#0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_RESET# PT_SM MEM_M_T PLK_SM MEMHOT_IMM#_ MEM_M_M MEM_M0_OT0 MEM_M_M MEM_M_M MEM_M_M MEM_M_M0 SMVREF_IM MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ IM_S0 IM_S IM_S0 IM_S SMVREF_IM MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_0 MEM_M_KE0 MEM_M_0 MEM_M_ MEM_M0_OT0 MEM_M_ MEM_M_ MEM_M_NK MEM_M_KE MEM_M_ MEM_M_NK0 MEM_M_NK MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_KE MEM_M_NK MEM_M_ MEM_M_0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M0_OT0 MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M_WE# MEM_M_S# MEM_M_RS# MEM_M0_S#0 MEM_M0_S#0 MEM_M_RS# MEM_M_NK0 MEM_M_NK MEM_M_NK MEM_M_ SMVREF_IM PT_SM PLK_SM SMVREF_IM MEMHOT_IMM# MEMHOT_IMM# MEMHOT_IMM# MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M0_S# MEM_M0_OT MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_M MEM_M_T MEM_M_T0 MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_T MEM_M_KE0 MEM_M_NK MEM_M_ MEM_M_ MEM_M_WE# MEM_M_S# MEM_M_ MEM_M_ MEM_M_ MEM_M_ MEM_M0_S# MEM_M0_OT MEM_M_0 MEM_M_NK0 MEM_M_T[0..] () MEM_M_QS0_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS0_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_KE0 () MEM_M_KE () MEM_M_RS# () MEM_M_S# () MEM_M_WE# () MEM_M0_S#0 () MEM_M0_OT0 () MEM_M0_OT () MEM_M0_S# () MEM_M_KE0 () MEM_M_KE () MEM_M_QS_N () MEM_M_RS# () MEM_M_S# () MEM_M_WE# () MEM_M0_S#0 () MEM_M0_OT0 () MEM_M0_OT () MEM_M_QS_P () MEM_M_QS_P () MEM_M0_S# () MEM_M_QS_P () MEM_M_LK_P () MEM_M_QS0_N () MEM_M_LK_N () MEM_M_QS0_P () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_LK_P () MEM_M_LK_N () MEM_M_T[0..] () MEM_M_[0..] () MEM_M_NK0 () MEM_M_NK () MEM_M_NK () MEM_M_M[0..] () MEM_M_[0..] () MEM_M_NK0 () MEM_M_NK () MEM_M_NK () MEM_M_M[0..] () PLK_SM (,) PT_SM (,) PU_MEMHOT# (,) MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_P () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_N () MEM_M_QS_P () MEM_M_QS_N () +V +V +SMR_VTERM +SMR_VTERM +SMR_VTERM +.VSUS +SMR_VTERM +SMR_VTERM +.VSUS +.VSUS +.VSUS +V +SMR_VREF +.VSUS +.VSUS +.VSUS +.VSUS +V +V Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : U N R SOIMMS: / HNNEL ustom Thursday, July, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : U N R SOIMMS: / HNNEL ustom Thursday, July, 00 Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : U N R SOIMMS: / HNNEL ustom Thursday, July, 00 o SMbus ddress SMbus ddress 0 0 TERMINTOR EOUPLING PITOR R TERMINTOR lose R socket RESS: H PLE LOSE TO SOKET( PER EMI/EM) RII Rev: / No-Sutff RII H/W Montor ircuit. RP _PR_ RP _PR_ R 0K_ R 0K_ *0.u/0V_ *0.u/0V_ 0.u/0V_ 0.u/0V_ 0U/0V_ 0U/0V_ R *0K_ R *0K_ RP _PR_ RP _PR_ 0.U/0V_ 0.U/0V_ RP _PR_ RP _PR_ R 0_ R 0_ RP _PR_ RP _PR_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM (REVERSE) (H=.) N R SO-IMM SOKET.V SO-IMM (REVERSE) (H=.) N R SO-IMM SOKET.V 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ 0 000P_ 0 000P_ RP _PR_ RP _PR_ 0U/0V_ 0U/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ S SL O.S 0 +VS U0 *SU+T&R U0 *SU+T&R RP _PR_ RP _PR_ R K/F_ R K/F_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ RP0 _PR_ RP0 _PR_ R *0_ R *0_ RP _PR_ RP _PR_ T0 T0 RP _PR_ RP _PR_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_ RP0 _PR_ RP0 _PR_ 00 0.u/0V_ 00 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R K/F_ R K/F_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ R 0K_ R 0K_ RP _PR_ RP _PR_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ T T 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ RP _PR_ RP _PR_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R *0_ R *0_ R 0K_ R 0K_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM (REVERSE) (H=0.) N R SO-IMM SOKET.V SO-IMM (REVERSE) (H=0.) N R SO-IMM SOKET.V RP0 _PR_ RP0 _PR_ 0.u/0V_ 0.u/0V_ RP0 _PR_ RP0 _PR_ 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0 0.u/0V_ 000P_ 000P_ RP _PR_ RP _PR_ 0 0.U/0V/0 0 0.U/0V/0 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ RP _PR_ RP _PR_ RP _PR_ RP _PR_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ R0 0K_ R0 0K_

9 RS0 RS0 isplay Port Support (muxed on GFX) 0 P0 GFX_TX0,TX,TX and TX UX0 and HP0 P GFX_TX,TX,TX and TX UX and HP () HT_PU_N H0 () HT_PU_N L0 () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H0 () HT_PU_N L0 () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N H () HT_PU_N L () HT_PU_N_LK_H0 () HT_PU_N_LK_L0 () HT_PU_N_LK_H () HT_PU_N_LK_L () HT_PU_N_TL_H0 () HT_PU_N_TL_L0 () HT_PU_N_TL_H () HT_PU_N_TL_L U Y HT_RX0P HT_TX0P Y HT_RX0N PRT OF HT_TX0N V HT_RXP HT_TXP E V HT_RXN HT_TXN E V HT_RXP HT_TXP F V HT_RXN HT_TXN F U HT_RXP HT_TXP F U HT_RXN HT_TXN F T HT_RXP HT_TXP H T HT_RXN HT_TXN H P HT_RXP HT_TXP J P HT_RXN HT_TXN J P HT_RXP HT_TXP K P HT_RXN HT_TXN K N HT_RXP HT_TXP K N HT_RXN HT_TXN K HT_RXP HT_RXN HT_RXP HT_RXN HT_RX0P HT_RX0N Y HT_RXP Y HT_RXN W HT_RXP W0 HT_RXN V HT_RXP V0 HT_RXN U0 HT_RXP U HT_RXN U HT_RXP U HT_RXN T HT_RXLK0P T HT_RXLK0N HT_RXLKP HT_RXLKN M HT_RXTL0P M HT_RXTL0N R HT_RXTLP R0 HT_RXTLN HYPER TRNSPORT PU I/F HT_TXP F HT_TXN G HT_TXP G0 HT_TXN H HT_TX0P J0 HT_TX0N J HT_TXP J HT_TXN K HT_TXP L HT_TXN J HT_TXP M HT_TXN L HT_TXP M HT_TXN P HT_TXP P HT_TXN M HT_TXLK0P H HT_TXLK0N H HT_TXLKP L HT_TXLKN L0 HT_TXTL0P M HT_TXTL0N M HT_TXTLP P HT_TXTLN R HT_N_PU H0 () HT_N_PU L0 () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H0 () HT_N_PU L0 () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU H () HT_N_PU L () HT_N_PU_LK_H0 () HT_N_PU_LK_L0 () HT_N_PU_LK_H () HT_N_PU_LK_L () HT_N_PU_TL_H0 () HT_N_PU_TL_L0 () HT_N_PU_TL_H () HT_N_PU_TL_L () R 00/F_ HT_RXLP HT_TXLP R 00/F_ HT_RXLN HT_RXLP HT_TXLP HT_TXLN HT_RXLN HT_TXLN lose to N within " RS0M lose to N within " U PR OF MEM_0(N) MEM_Q0/VO_VSYN(N) E MEM_(N) MEM_Q/VO_HSYN(N) 0 V MEM_(N) MEM_Q/VO_E(N) E MEM_(N) MEM_Q/VO_0(N) Y MEM_(N) MEM_Q(N) V MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q/VO_(N) Y MEM_(N) MEM_Q/VO_(N) 0 MEM_(N) MEM_Q/VO_(N) MEM_0(N) MEM_Q0/VO_(N) E E MEM_(N) MEM_Q/VO_(N) MEM_(N) MEM_Q(N) 0 Y MEM_(N) MEM_Q/VO_(N) MEM_Q/VO_0(N) MEM_0(N) MEM_Q/VO_(N) E MEM_(N) MEM_(N) MEM_QS0P/VO_IKP(N) Y MEM_QS0N/VO_IKN(N) W W MEM_RSb(N) MEM_QSP(N) 0 Y MEM_Sb(N) MEM_QSN(N) E MEM_WEb(N) MEM_Sb(N) MEM_M0(N) W MEM_KE(N) MEM_M/VO_(N) E V MEM_OT(N) IOPLLV(N) E V MEM_KP(N) IOPLLV(N) E W MEM_KN(N) IOPLLVSS(N) E MEM_OMPP(N) MEM_OMPN(N) MEM_VREF(N) E RS0M S_MEM/VO_I/F R +._IOPLLV_N +.V_IOPLLV SPM_VREF *K/F_ 0mils wdith or more R R 0_ R 0_ *K/F_ T0 T () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN () PIE_RXP () PIE_RXN T T0 () PIE_RXP () PIE_RXN () PIE_S_N_RX0P () PIE_S_N_RX0N () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN +.V +.V +.V U GFX_RX0P GFX_RX0N GFX_RXP GFX_RXN GFX_RXP GFX_RXN E GFX_RXP F GFX_RXN G GFX_RXP G GFX_RXN H GFX_RXP H GFX_RXN J GFX_RXP J GFX_RXN J GFX_RXP J GFX_RXN L GFX_RXP L GFX_RXN M GFX_RXP L GFX_RXN P GFX_RX0P M GFX_RX0N P GFX_RXP M GFX_RXN R GFX_RXP P GFX_RXN R GFX_RXP R GFX_RXN P GFX_RXP P GFX_RXN T GFX_RXP T GFX_RXN E GPP_RX0P GPP_RX0N E GPP_RXP GPP_RXN GPP_RXP GPP_RXN V GPP_RXP W GPP_RXN U GPP_RXP U GPP_RXN U GPP_RXP U GPP_RXN S_RX0P Y S_RX0N S_RXP Y S_RXN S_RXP S_RXN W S_RXP Y S_RXN RS0M GFX_TX0P PRT OF GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TX0P GFX_TX0N GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GFX_TXP GFX_TXN GPP_TX0P GPP_TX0N GPP_TXP GPP_TXN GPP_TXP PIE I/F GPP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN GPP_TXP GPP_TXN S_TX0P S_TX0N S_TXP S_TXN PIE I/F S S_TXP S_TXN S_TXP S_TXN PE_LRP(PE_LRP) PE_LRN(PE_LRN) PIE I/F GFX E E F F F F H H H H J J K K K K M M M M N N P P Y Y Y Y V V E E E GFX_TX0P_ GFX_TX0N_ GFX_TXP_ GFX_TXN_ GFX_TXP_ GFX_TXN_ GFX_TXP_ GFX_TXN_ T T S_TX0P_ S_TX0N_ S_TXP_ S_TXN_ S_TXP_ S_TXN_ S_TXP_ S_TXN_ HMI_LKP HMI_T0P HMI_TP HMI_TP PIE_TXP0_ PIE_TXN0_ PIE_TXP_ 0 PIE_TXN_ 0 PIE_TXP_ 0 PIE_TXN_ 0 PIE_TXP_ 0 PIE_TXN_ 0 PIE_TXP_ PIE_TXN_ PIE_TXP_ 0 PIE_TXN_ 0 N_PIELRP R N_PIELRN R lose to North ridge GPP0 GPP GPP GPP GPP GPP 0 R R R R 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ X PIE LN(Marvell) Wireless Lan HMI_TP HMI_TN HMI_TP HMI_TN HMI_T0P HMI_T0N HMI_LKP HMI_LKN HMI_LKN HMI_T0N HMI_TN HMI_TN T T PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () PIE_TXP () PIE_TXN () T T PIE_TXP () PIE_TXN () HMI_TP () HMI_TN () HMI_TP () HMI_TN () HMI_T0P () HMI_T0N () HMI_LKP () HMI_LKN () PIE_N_S_TX0P () PIE_N_S_TX0N () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () +.V_V_PIE EXPRESS R (NEW R) X 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_.K/F_ K/F_ 0./F_ 0./F_ 0./F_ 0./F_ Robson/H ecoder To HMI ONN on't support in RS0M Red PROJET : U Quanta omputer Inc. Green lue Rev: 0/0 dded the EMI Solution. N Size ocument Number Rev ustom RS0/RS0-HT LINK/PIE I/F / ate: Thursday, July, 00 Sheet of

10 RS0 +V +.V L LMPGSN_ R 0_ 0. +V_V_N.u/.V_ 0.u/0V_ +.V_VI_N Rev: /0 dd 0.u For RT Screen Flicker. 0 0.U/.V_ Rev: 0/ Follow silicon hange R0 From 0 To 0ohm For Unbalanced power bus IR drop.. () () () +.V RT_R RT_G RT_ 0R Termination < 000 mils trace LOSE TO N +.V_VQ_N TV_/R_SYS R0 R R HSYN () HSYN +.V VSYN _HSYN(PWM_GPIO) TXLK_LP(G_GPIO) INT_TXLLKOUT+ () () VSYN INT_TXLLKOUT- () 0/F_ 0/F_ 0/F_ L R 0_ LK_INT _VSYN(PWM_GPIO) TXLK_LN(G_GPIO) () LK F +.V R0 0_ T_INT _SL(PE_RLRN) TXLK_UP(PIE_RESET_GPIO) () T E L LMPGSN S(PE_TLRN) TXLK_UN(PIE_RESET_GPIO) R /F RSET_N G LMPGSN RSET(PWM_GPIO) +.V_VLTP_N.u/.V_ +.V_PLLV VLTP(N) +.V_PLLV PLLV(N) VSSLTP(N).u/.V_ PLLV(N) +.V_VLT N +.V +.V PLLVSS(N) VLT_(N) L L +.V_VHTPLL VLT_(N) H +V_VLT_N VHTPLL VLT_(N) LMPGSN_ LMPGSN_ +.V_VPIEPLL VLT_(N) 0 VPIEPLL E VPIEPLL VSSLT(VSS) 0mils width 0.u/0V_.u/.V_ L.u/.V_ N_RST#_IN VSSLT(VSS) +V +.V_VHTPLL N_PWRG_IN SYSRESETb VSSLT(VSS) L () N_PWRG_IN 0 LMPGSN_ N_LT_STOP# POWERGOO VSSLT(VSS) 0 0 N_LLOW_LTSTOP LTSTOPb VSSLT(VSS) E0 *LMPGSN_ LLOW_LTSTOP VSSLT(VSS).u/.V_ HT_REFLKP VSSLT(VSS) RS0M Only HT_REFLKN HT_REFLKP I *.u/.v/0 HT_REFLKN 0mils width L R EXT@0_ N_REFLK_P () EXT_N_OS E +.V_VPIEPLL R EXT@0_ N_REFLK_N REFLK_P/OSIN(OSIN) F I LMPGSN_ REFLK_N(PWM_GPIO) E INT_LVS_ON R 0_ INT_LVS_IGON () LVS_IGON(PE_TLRP) LVS_EN_L () NGFX_LKP T F +.V R EXT@.K_ R0 EXT@.K_ GFX_REFLKP LVS_LON(PE_RLRP) LVS_KL_EN () NGFX_LKN T I/O G 0u/.V_.u/.V_ GFX_REFLKN LVS_EN_L(PWM_GPIO) External LK GPP_REFLKP T U GPP_REFLKN GPP_REFLKP T U GPP_REFLKN I/O () () L0 LMPGSN_ INT_LVS_EILK INT_LVS_EIT () HMI T () HMI LK () T T +N_ORE_ON T.U/.V_ Without TV-Out feature S_REFLKP S_REFLKN HMI T HMI LK RS0_FT_GPIO +N_ORE_ON RS0_UX_L F E F G H H E F F G G E F E F V V 0 G U V(N) V(N) VI(N) VSSI(N) VQ(N) VSSQ(N) _Pr(FT_GPIO) Y(FT_GPIO) OMP_Pb(FT_GPIO) RE(FT_GPIO0) REb(N) GREEN(FT_GPIO) GREENb(N) LUE(FT_GPIO) LUEb(N) GPPS_REFLKP(S_REFLKP) GPPS_REFLKN(S_REFLKN) I_LK I_T _T0/UX0N _LK0/UX0P UXP(N) UXN(N) STRP_T RSV UX_L(N) RS0M PRT OF RT/TVOUT LOKs PM PLL PWR LVTM MIS. TXOUT_L0P(N) TXOUT_L0N(N) TXOUT_LP(N) TXOUT_LN(N) TXOUT_LP(N) TXOUT_LN(G_GPIO0) TXOUT_LP(N) TXOUT_LN(G_GPIO) TXOUT_U0P(N) TXOUT_U0N(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(PIE_RESET_GPIO) TXOUT_UP(N) TXOUT_UN(N) TXOUT_UP(PIE_RESET_GPIO) TXOUT_UN(N) TMS_HP(N) HP(N) TVLKIN(PWM_GPIO) THERMLIOE_P THERMLIOE_N TESTMOE E TXLOUT+ TXLOUT- TMS_HP0 TMS_HP SUS_STT#_N R_N_THRM R_N_THRM TEST_EN R INT_TXLOUT0+ () INT_TXLOUT0- () INT_TXLOUT+ () INT_TXLOUT- () INT_TXLOUT+ () INT_TXLOUT- () T T0 R 0_ R 0_.K_ TMS_HP () T T T SUS_STT# () FOR S INTERNL LOK North ridge RESET +VG_N LVS LON +V +V STRP EUG US GPIO () S_ISP_LKP () S_ISP_LKN RP *INT@0_PR_ N_REFLK_P N_REFLK_N (,) _RST# R 0_ R *.K_ N_RST#_IN R 0K_ R 0K_ N_L_ONTROL FT_GPIO0: STRP_EUG_US_PIE_ENLE +V R R K_ *K_ HSYN (,) PU_LT_RST# R *0_ Q For Side Port Enables/isable 0 : Enable(efault) : isable () HT_REFLKP () HT_REFLKN () S_NHT_REFLKP () S_NHT_REFLKN RP *INT@0_PR_ HT_REFLKP HT_REFLKN HT N (,) PU_LT_STOP# +.V Q +VG_N R *.K_ N_LT_STOP# N_PWRG_IN Q SS_NL/SOT N00E-G +V R R K_ *K_ VSYN Enables the Test ebug us using GPIO.(RS0 -->VSYN#) : Enable(efult) 0 : isable () S_REFLKP () S_REFLKN () S_PIE_N_LKP () S_PIE_N_LKN RP *INT@0_PR_ S_REFLKP S_REFLKN North ridge -Link *SS/SOT R 0_ +.V +VG_N R INT_LVS_ON R0 N_L_ONTROL.K_ VGS-TH<.V +V UX L Value need update R R *0K_.K_ +N_ORE_ON Rev: 0/ Support a Two-Step Voltage ontrol of North ridge ore voltage. Reserve Pin +V () () PU_LT_REQ# LLOW_LTSTOP R 0_ R 0_ N_LLOW_LTSTOP Rev: 0/ Modified the Level Shift ircuit For System leakage issue. Q *SS/SOT *.K_ LVS_KL_EN FV0N Q R0 N_L_ONTROL.K_ INT_LVS_LON () Rev: /0 hange Q P/N For VGS 0.V<Vt<.V R0 R R *K_ *K_ 0/F_ TV_/R_SYS RS0_FT_GPIO RS0_UX_L R R *.K_ *.K_ HMI T HMI LK RS0;RS0 +V R *0_ +VG_N LVS_EN_L Q *FV0N R *.K_ INT_LVS_PWM () PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom RS0/RS0-SYSTEM I/F / Thursday, July, 00 ate: Sheet of 0

11 RS0/RX0/RS0 POWER IFFERENE TLE E G G G H J R L L L L M N P R R R V U V V W W W W W Y E E VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE VSSPIE0 E G E E J J K M L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 UF PIN NME VHT VHTRX VHTTX VPIE RS0 N N +.V N RX0 +.V +.V +.V +.V RS0 +.V +.V +.V +.V PIN NME IOPLLV V VI VQ RS0 RX0 RS0 +.V N +.V +.V N +.V +.V N +.V +.V N +.V PRT / GROUN VG V_MEM VPIE +.V +.V +.V N N +.V +.V +.V +.V PLLV PLLV VPIEPLL +.V +.V +.V N N +.V +.V +.V +.V VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT0 VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSSHT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS RS0M V V_MEM VG +.V +.V/.V +.V +.V N N +.V +.V/.V +.V VHTPLL VLTP VLT +.V +.V +.V +.V N N +.V +.V +.V E G G G H J L L L L M0 N P0 R R R R H0 U V W W W Y L M N P P R R T U U U V W W Y E0 K IOPLLV +.V N +.V VLT +.V N N +.V +.V L +.V LMPGSN_ hip ug Errata use hip an Remove.().u/.V_ +.V +.V.u/.V_ +.V_VHT 0.u/0V_ +.V_VHTRX +.V_VHTTX Rev: /0 hange VHTTX Voltage From.V to. Rails For hip. L LMPGSN_ L0 LMPGSN_ L LMPGSN_.u/.V_ 0.u/.V_.u/.V_ 0.u/0V_ 0.u/0V_ R 0_ R 0_ 0.u/0V_ 0.u/0V_ +.V_VPIE 0.u/0V_.V(0.00) u/0v_.v(0.00) 0.u/0V_ 0.u/0V_ 0 0.u/0V_ 0.u/0V_ 0. 0.u/0V_.V(0.).V(0.) +.V_VG_N +.V_V_MEM 0. 0.u/0V_ 0.u/0V_ 0.u/0V_ J K L M P R T H G F0 E E Y0 W V U T R P M J0 P0 K0 M0 L0 W H T0 R0 Y E U0 F G E UE VHT_ VHT_ VHT_ VHT_ VHT_ VHT_ VHT_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTRX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_ VHTTX_0 VHTTX_ VHTTX_ VHTTX_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ PRT / POWER VG_(V_) VG_(V_) V_MEM(N) V_MEM(N) RS0M VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_0 VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ VPIE_ V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_ V_ V_ V_ V_ V_ V_ V_0 V_ V_ V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) V_MEM(N) VG_(N) VG_(N) E F G H J K M L P R T V U K J U J K M L L M M N N P P P R R T T U T J E0 Y H H u/0V_.V() 0.u/0V_ 0 0.u/0V_.V(0.) R0 0_.V(0.0) 0 0.u/0V_ +.V_V_PIE +.V_V_MEM +V_VGV +N_ORE +.V +V +.V Rev: /0 hange and Fix the N ore Voltage to.v For hip. 0.u/0V_ 0.u/0V_ 0 0 u/0v_ 0 0.u/0V_ 0 0.u/0V_ R u/0v_ 0 0.u/0V_ 0u/.V_ *0_ R 0_.u/.V_ 0u/.V_ 0 *0u/.V_ R 0_ +N_ORE Rev: hange Footprint to 00 size 0.u/0_ 0.u/0_ RS0 N PROJET : U Quanta omputer Inc. Size ocument Number Rev ustom RS0/RS0-POWER/ ate: Thursday, pril 0, 00 Sheet of

12 S00 FOR INTERNL LOK (,) PU_LKP (,) PU_LKN (,) LK_PIE_NEW (,) LK_PIE_NEW# (,) LK_PIE_MINI (,) LK_PIE_MINI# +VPU TERM TERM TERM TERM From lk Gen To N -Link LK For North ridge For North ridge For PU Host lk To Marvell Lan To New ard To Mini ard, VRT S_PU_LKIN_P S_PU_LKIN_N S_GPP_LKP S_GPP_LKN S_GPP_LKP S_GPP_LKN Place close to LK GEN () SSR_LKP () SSR_LKN (0) S_PIE_N_LKP (0) S_PIE_N_LKN (0) S_ISP_LKP (0) S_ISP_LKN (0) S_NHT_REFLKP (0) S_NHT_REFLKN (,) PIE_LK_LN (,) PIE_LK_LN# (,) PIE_LK_MINI (,) PIE_LK_MINI# +.V_PIE_VR +.V S_PU_LKIN_P S_PU_LKIN_N S_GPP_LKP S_GPP_LKN S_GPP_LKP S_GPP_LKN (,,,) PLTRST# (0,) _RST# () PIE_S_N_RX0P () PIE_S_N_RX0N () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_S_N_RXP () PIE_S_N_RXN () PIE_N_S_TX0P () PIE_N_S_TX0N () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN () PIE_N_S_TXP () PIE_N_S_TXN +.V_PIE_PV +.VSUS +.V TERM +VRT R 0/F_ RT_X R00 R R G *0K_ *0K_ U/0V_ R *SHORT_ P (0) LLOW_LTSTOP K_ () PU_PROHOT# () PU_PWRG Rev: 0/ RT ircuit R/R0/R/R Follow Standar ircuit Value. (,0) PU_LT_STOP# (,0) PU_LT_RST# +VPU Rev: 0/0 No-Stuff R For Leakage when system into G mode. 0MIL Input Rev: 0/0 s the same location Name(G) For Toshiba Service Team Request. N R00 Q MMT0 R K/F_ RP *INT@0_PR_ RP *INT@0_PR_ RP *INT@0_PR_ R0 K/F_ R.K/F_.PIE Reference lk(ext lk Gen). -Link lk to North ridge(int lk Gen) lose to S R */F_ L RP RP RP RP RP0 RP RP RP RP Install for Int lk Gen OUPLING PS LOSE TO S00 Ext: lk Gen Int: -Link lock to N R R _ 0 R R LMPGSN_ 0 EXT@0_PR_ EXT *INT@0_PR_ INT R0 _ *INT@0_PR_ *INT@0_PR_ *INT@0_PR_ *P_ T T *INT@0_PR_ *INT@0_PR_ *P_ Y T 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ 0.u/0V_ /F_.0K/F_ 0u/.V_ *INT@0_PR_ *INT@0_PR_ Y *MHZ _RST#_S _RX0P RX0N RXP RXN RXP RXN RXP RXN_ S_PIE_LRP S_PIE_LRN u/0v_ PIE_RLKP PIE_RLKN N_ISP_LKP N_ISP_LKN N_HT_LKP N_HT_LKN PU_HT_LKP PU_HT_LKN SLT_GFX_LKP SLT_GFX_LKN GPP_LK0P GPP_LK0N GPP_LKP GPP_LKN GPP_LKP GPP_LKN GPP_LKP GPP_LKN RT_X RT_X S00_M_X R0 *0M_ S00_M_X RT_X 0m U S00 N _RST# PILK0 Part of PILK V PIE_TX0P PILK V PIE_TX0N PILK V PIE_TXP PILK V PIE_TXN PILK/GPIO U PIE_TXP U PIE_TXN T PIE_TXP T PIE_TXN PIRST# U PIE_RX0P U PIE_RX0N 0 U PIE_RXP V PIE_RXN R0 PIE_RXP R PIE_RXN R PIE_RXP R PIE_RXN T PIE_LRP T PIE_LRN 0 P PIE_PV P PIE_PVSS 0 N PIE_RLKP/N_LNK_LKP N PIE_RLKN/N_LNK_LKN K N_ISP_LKP K N_ISP_LKN 0 M N_HT_LKP E0# M N_HT_LKN 00MHZ E# E# P PU_HT_LKP E# M PU_HT_LKN FRME# EVSEL# M SLT_GFX_LKP IRY# M SLT_GFX_LKN TRY# PR J GPP_LK0P STOP# J GPP_LK0N PERR# SERR# L0 GPP_LKP REQ0# L GPP_LKN REQ# REQ# M GPP_LKP REQ#/GPIO0 M0 GPP_LKN REQ#/GPIO GNT0# N GPP_LKP GNT# P GPP_LKN GNT# GNT#/GPIO L M_M_M_OS GNT#/GPIO LKRUN# LOK# J M_X INTE#/GPIO INTF#/GPIO INTG#/GPIO J0 M_X INTH#/GPIO LPLK0 LPLK X L0 L L L X LFRME# LRQ0# LRQ#/GNT#/GPIO MREQ#/REQ#/GPIO SERIRQ RT XTL F LLOW_LTSTP F PROHOT# F LT_PG G LT_STP# G LT_RST# S00 PU PI EXPRESS INTERFE LP RT LOK GENERTOR PI LKS PI INTERFE RTLK INTRUER_LERT# VT P P P P T T N U P V T V U V V T W T R R R U U Y W V Y Y Y Y W U Y W Y U W W V E E E V E E G E H H J J H H V PI_LK0_R PI_LK_R PI_LK_R PI_LK_R PI_LK_R PI_LK_R PIRST#_S REQ0# REQ# REQ# REQ# GNT# GNT# GNT# LKRUN#_R INTE# INTF# INTG# INTH# LPLK0_R LPLK_R LRQ#_S S_GPIO SERIRQ INTRUER_LERT# 0MIL R0 _ R _ R _ R _ R _ R R R _ [0..] [0..] (,,) REQ0# REQ# GNT# GNT# INTE# () INTF# () FM@0_ *GS@0_ S_GPIO R PLK_OZ () PLK_PM () PI_LK () PI_LK () PI_LK () PI_LK () PIRST# (,) R _ PLK_ (,) R _ PLK_EUG (,) L0 (,) L (,) L (,) L (,) LFRME# (,) LRQ#0 () T T SERIRQ (,,) RT_LK () T VRT R R FM_INT () HPINT () *.K_ *.K_ E0# (,) E# (,) E# (,) E# (,) FRME# (,) EVSEL# (,) IRY# (,) TRY# (,) PR (,) STOP# (,) PERR# () SERR# () REQ0# () REQ# () T PORT_# () T GNT0# () GNT# () T Rev: /0 EL G-Sensor SI Event(GPIO). T R0 0_ LKRUN# (,) Rev: 0/0 Remove Test Ports For Space Limiting. u/0v_ 0.u/0V_ R R *.K_.K_ 00K_ +V S_0-000L Rev: /0 hange Part Number. RT R K/F_ *0M_ R P_.KHZ 0M_ P_ N PROJET : U Quanta omputer Inc. Size ocument Number Rev ustom S00-PIE/PI/PU/LP / ate: Thursday, July, 00 Sheet of

13 S00 () Z_LK Z_SOUT Part of MHz (,) PI_PME# E RI# PI_PME#/GEVENT# LK_M_US T E SLP_S RI#/EXTEVNT0# USLK/M_M_M_OS LK_M_US () +.VSUS T H SLP_S/GPM# US_ROMP_S (,) SUS# F US_ROMP G R.K/F_ SLP_S# Input () SUS# G SLP_S# () NSWON# H PWR_TN# () S_PWRG_IN H R.K_ S_SLK SUS_STT# PWR_GOO (0) SUS_STT# K Rev: 0/0 Reserve the 0hm to US ontroller. R *.K_ S_TEST SUS_STT# H R.K_ S_ST +V_S R *.K_ S_TEST TEST US_FSP E H Rev: 0/0 Swap US ONN From US to US For ontroller EST ertification. R *.K_ S_TEST0 TEST US_FSN E H TEST0 () GTE0 Y Rev: / Swap the New ard From US to US For OHI ontrollers. G0IN/GEVENT0# US_FSP F () RIN# W KRST#/GEVENT# US_FSN E () SI# K LP_PME#/GEVENT# US_FSP R 0_ USP+ +V_S T0 K LP_SMI#/EXTEVNT# US_HSP Rev: /0 Support the New ard Hot Plug Function. H US_FSN R 0_ USP- T F SYS_RST# S_STTE/GEVENT# US_HSN J0 J SYS_RESET#/GPM# (,) PIE_WKE# H USP0+ (0) GPM# WKE#/GEVENT# US_HS0P E T F USP0- (0) E-ST and US onnector R.K_ S_SLK LINK/GPM# US_HS0N F () PU_THERMTRIP# J SMLERT#/THRMTRIP#/GEVENT# US_FSP () W_PWRG W R.K_ S_ST N_PWRG US_HSP T0 US_FSN R 0_ S_RSMRST# US_HSN T0 () RSMRST# R.K_ S_SMLK RSMRST# US_HSP 0 USP+ () USP- () TV/H EOER Min-ard R.K_ S_SMT US_HSN 0 OR_I E US_FSP R *0_ USP+ USP+ (0) R 0K_ USO_GPM OR_I ST_IS0#/GPIO0 US_HSP G US_FSN R *0_ USP- USP- (0) US onnector OR_I0 LK_REQ#/ST_IS#/GPIO US_HSN H R0 FM@0_ FM_LK_REQ0# SMRTVOLT/ST_IS#/GPIO () FM_LK W USP+ () Rev: 0/0 US Overcurrent Pull-up 0K For Open rain. R *0_ S_LK_REQ# LK_REQ0#/ST_IS#/GPIO0 US_HSP E (,) NEW_LKREQ# V USP- () LUETOOTH R00 FM@0_ FM_T_REQ# LK_REQ#/ST_IS#/FNOUT/GPIO US_HSN E +V () FM_T W0 LK_REQ#/ST_IS#/FNIN/GPIO0 () SPKR W USP+ () PLK_SM SPKR/GPIO US_HSP (,) PLK_SM USP- () FINGERPRINT R.K_ SUS_STT# PT_SM SL0/GPO0# US_HSN (,) PT_SM W S_SMLK S0/GPO# (,) S_SMLK K USP+ () R *0K_ S_LK_REQ# S_SMT SL/GPO# US_HSP (,) S_SMT K USP- () Min-ard FM_ETET S/GPO# US_HSN () FM_ETET 0 R.K_ PLK_SM _SL/GPIO () PM Y USP+ () LL#/GPIO _S/GPIO US_HSP G T USP- () NEW R R.K_ PT_SM LOW_ET LL#/GPIO US_HSN G () LOW_ET Y R0 *GS@0_ GEVENT# SHUTOWN#/GPIO () HPT G R_RST#/GEVENT# US_HSP USP+ () Rev: /0 EL G-Sensor SI Event(GPIO). H US_HSN H USP- () MER US IT_LK_UIO Rev: 0/0 Move oard I Pin Name From GPIO to GPIO. G *SHORT_ P SYS_RST# Z_LK (,) PU_MEMHOT# (0,) () NEW_ET# (,) Rev: 0/0 dded the US Overcurrent to Support US.0 Ports. Rev: 0/0 Move Hot Plug Pin Name From GEVENT# to GPM. H udio Interface R _ *0P_ To zalia H0H-0PT R 0_ USO# T R 0_ () () () R USO#0 Z_SIN0 T T T Z_RST# H_UX_RST# T NEW@0_ PU_MEMHOT#_IN USO_GPM USO_GPM USO_GPM S_JTG_TK USO_GPM Z_SYN Z_RST# +.V R 0K_ E F E M M J J L M L M L H H0 H F E E U US_O#/IR_TX/GEVENT# US_O#/IR_TX0/GPM# US_O#/IR_RX0/GPM# US_O#/IR_RX/GPM# US_O#/GPM# US_O#/GPM# US_O0#/GPM0# Z_ITLK Z_SOUT Z_SIN0/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SIN/GPIO Z_SYN Z_RST# Z_OK_RST#/GPM# IM_GPIO0 IM_GPIO SPI_S#/IM_GPIO IE_RST#/F_RST#/IM_GPO IM_GPIO IM_GPIO IM_GPIO IM_GPIO H UIO US O INTEGRTE u S00 PI / WKE UP EVENTS INTEGRTE u US MIS GPIO US. US.0 US_HSP US_HSN US_HS0P US_HS0N IM_GPIO IM_GPIO IM_PWM0/IM_GPIO0 SL/IM_GPIO S/IM_GPIO SL_LV/IM_GPIO S_LV/IM_GPIO IM_PWM/IM_GPIO IM_PWM/IM_GPO IM_PWM/IM_GPO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO IM_GPIO0 IM_GPIO F F E0 E E E G0 G S_SLK S_ST S_SLK S_ST LK_M_US R USP+ () USP- () USP0+ () USP0- () EMI *0_ S_SLK () S_ST () S_SLK () S_ST () S_GPIO () S_GPIO () Felica *0P_ SPI/LP define US onnector(rj/us OR) To zalia S00 Rev: 0/ There is internal.k of I/O alls So hange Pull-own Resistors From 0K to K. () Z_SOUT_UIO () Z_SYN_UIO () Z_RST#_UIO R _ R _ *0P_ *0P_ Z_SOUT To zalia Z_SYN OR_I W/ New rad W/ rad us W/ FL Panel W/ LE Panel W/ G-Sensor W/O G-Sensor W/O FM H W/FM L To zalia R *W/O@K_ OR_I R0 HM@0K_ W/ HMI W/O HMI H L R0 _ Z_RST# R0 *LOW@K_ LOW_ET R0 MIN@0K_ Main Strem Low ost H L OR_I OR_I () M I Selection Table OR_I0 OR_I OR_I FM_ETET OR_I LOW_ET H L H L H L R0 R R R0 *@K_ *LE@K_ *W/O@K_ *FM@K_ M I OR_I0 OR_I OR_I FM_ETET R0 R R R0 NEW@0K_ L@0K_ *GS@0K_ W/O@0K_ +V N PROJET : U Quanta omputer Inc. Size ocument Number Rev ustom S00-PI/GPIO/US / Thursday, July, 00 ate: Sheet of

14 S00 PLE ST OUPLING PS LOSE TO S00 U ST H E-ST ST O (0) ST_TXP0 (0) ST_TXN0 (0) ST_TXP (0) ST_TXN (0) ST_TXP (0) ST_TXN +.V (0) ST_RXN0 (0) ST_RXP0 (0) ST_RXN (0) ST_RXP (0) ST_RXN (0) ST_RXP NOTE: R IS K % FOR MHz XTL,.K % FOR 00MHz INTERNL LOK 0m) m ST_X ST_X +.V_PLLV_ST ST_TXP0_R ST_TXN0_R ST_TXP_R ST_TXN_R Rev: 0/ hange H ontrol From hannel/ to hannel/0 For Spin own Issue. ST_TXP_R ST_TXN_R Rev: 0/ hange Setting the ST O to be IE Legacy class Mode.. 0 P_ P_ Y MHZ L0 LMPGSN_ 0.0u/V_ 0.0u/V_ 0.0u/V_ 0.0u/V_ 0.0u/V_ 0.0u/V_ R 0M_ () ST_LE# +.V_PLLV_ST +V_XTLV_ST 0.0u/V_ 0.0u/V_ 0.0u/V_ 0.0u/V_ ST_TXP0_ ST_TXN0_ ST_RXN0_ ST_RXP0_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_TXP_ ST_TXN_ ST_RXN_ ST_RXP_ ST_RIS_PN ST_X ST_X Rev: /0 ahnge /0 Load apacitance For Matching rystal. 0 u/0v_ u/0v_ R R0 R R T T0 T T R R R./F_./F_./F_./F_./F_./F_ 0.0u/V_ 0.0u/V_ K/F_ ST_TX0P E ST_TX0N 0 ST_RX0N 0 ST_RX0P E0 ST_TXP 0 ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP ST_TXP E ST_TXN ST_RXN ST_RXP E ST_TXP ST_TXN ST_RXN E ST_RXP ST_TXP ST_TXN E ST_RXN ST_RXP V Y W W ST_L ST_X ST_X ST_T#/GPIO PLLV_ST XTLV_ST S00 ST PWR SERIL T S00 IE_IORY Part of IE_IRQ IE_0 IE_ IE_ IE_K# IE_RQ IE_IOR# IE_IOW# IE_S# IE_S# IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_0/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO IE_/GPIO0 SPI_I/GPIO SPI_O/GPIO SPI_LK/GPIO SPI_HOL#/GPIO SPI_S#/GPIO LN_RST#/GPIO ROM_RST#/GPIO FNOUT0/GPIO FNOUT/GPIO FNOUT/GPIO FNIN0/GPIO0 FNIN/GPIO FNIN/GPIO TEMP_OMM TEMPIN0/GPIO TEMPIN/GPIO TEMPIN/GPIO TEMPIN/TLERT#/GPIO HW MONITOR SPI ROM T /00/ 0/GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO /GPIO0 V VSS Y Y Y Y E E0 0 E 0 0 E E G F F U J M M M P P R F G P0 P P P P P P P P P P0 P P P P P LN_RST# ROM_RST# S_FNOUT S_FNOUT m V_HWM PIORY () IRQ () P0 () P () P () PK# () PREQ () PIOR# () PIOW# () PS# () PS# () P[0..] () Rev: 0/0 Reserve the oard I For US ontroller. Rev: 0/0 dded the oard I to GPIO.. R0 R R *0.u/0V_ T0 OR_I () *US@K_ US@K RST# (0,) Rev: 0/0 Remove Test Ports For Space Limiting. T0 T T0 PM_THERM# () Rev: 0/0 Remove Test Ports For Space Limiting. 0 *0_ *.u/.v_ R 0_ +V V--H/W Monitor nalog power Rev: /0 hange +V omain For System Leakage When System into S Mode. +V L LMPGSN_ m +V_XTLV_ST u/0v_ Place near ball PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom S00-PI/GPIO/US / ate: Thursday, July, 00 Sheet of

15 S00 PLE LL THE EOUPLING PS ON THIS SHEET LOSE TO S S POSSILE. Rev: /0 The V Power Pin to be connected to S0_.V Power For hip. hip ug use hip an Remove +V R00 0_ V_--.V IE I/O power.v flash memory I/O power +.V +.V +.V +V_S 00u/.V_ R 0_ L L LMPGSN_ L 0 LMPGSN_ LMPGSN_ 0u/.V_ For support US wakeup-->v_s u/0v_ u/.v_ u/.v_ u/.v_ 0 u/.v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ u/0v_ 0 u/.v_ 0 u/0v_ +.V_S_R +V_ +.V_PIE_VR m +.V_V_ST u/0V_ +V_V_US 0.u/0V_ 0. u/0v_ u/0v_ u/0v_ 0 u/0v_ 0.u/0V_ 0.u/0V_ u/0v_ 0. 0.u/0V_ 0.u/0V_ 0.u/0V_ 0. U L VQ_ M VQ_ T VQ_ U VQ_ U VQ_ U VQ_ V VQ_ W VQ_ Y VQ_ VQ_0 VQ_ VQ_ Y0 V V V E V P PIE_VR_ P PIE_VR_ P0 PIE_VR_ P PIE_VR_ R PIE_VR_ R PIE_VR_ R PIE_VR_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ V_ST_ E V_ST_ VTX_0 VTX_ VTX_ VTX_ VTX_ E VTX_ F VRX_0 F VRX_ F VRX_ G VRX_ G VRX_ G VRX_ S00 Part of PI/GPIO I/O IE/FLSH I/O -LINK I/O ST I/O PLL LKGEN I/O ORE S.V_S I/O ORE S0 POWER US I/O V_ V_ V_ V_ V_ V_ V_ V_ V_ KV_.V_ KV_.V_ KV_.V_ KV_.V_ S_.V_ S_.V_ S_.V_ S_.V_ S_.V_ S_.V_ S_.V_ S_.V_ S_.V_ US_PHY_.V_ US_PHY_.V_ V_VREF VK_.V VK_.V V L M M N P P R R T L L L L J J L L G G 0 0 E J K E m +.V_V_S_R 0 +.V_KV +V_VK +.V_VK +V_V 0.u/0V_ +.VLW_R +.V_US_PHY_R m u/0v_ 0 u/0v_ 0 u/0v_ m m 0m 00 m VLW_R +V_VREF u/0v_ u/0v_ u/0v_ 0 u/.v_ u/0v_ R 0 u/0v_ u/0v_ u/0v_.u/.v_.u/.v_.u/.v_ 0 u/0v_.u/.v_ 0 0u/.V_ L R LMPGSN_ R 0_ R 0_ R0 0_ K/F_ H0H-0PT R 0_ u/.v_ +.V +V_S +.V_S +.V_S +V +V *0_ +.V_S +.V T0 U0 U U V V W Y Y Y Y E E F F G H H J J J J J K0 K K K H J J K M M M P F UE VSS_ VSS_ VSS_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_0 VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_0 VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_0 VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_ VSS_ VSS_ST_0 VSS_ VSS_ VSS_ VSS_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_0 VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_0 VSS_ VSS_US_ VSS_ VSS_US_ VSS_0 VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_ VSS_ VSS_US_0 VSS_ VSS_US_ VSS_ VSS_US_ VSS_0 VSS_US_ VSS_US_ PIE_K_VSS_ PIE_K_VSS_0 PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_ PIE_K_VSS_0 PIE_K_VSS_ PIE_K_VSS_ VSS S00 GROUN Part of VSSK F0 G H K K K L L L0 L L L L M M0 M M M N N N P P P0 P P P R R R R R0 R R T T T U U V Y E E P R R T U U0 V V0 V W W W W L S00 S00 u/0v_ u/0v_ u/0v_ 0.u/0V_ 0.u/0V_ +V +V_VK L +.V L +.V_VK +V_S L +V_V LMPGSN_ LMPGSN_ LMPGSN_.u/.V_.u/.V_ 0u/.V_ 0.u/0V_ PROJET : U Quanta omputer Inc. N Size ocument Number Rev ustom S00-PWR/EOUPLING / ate: Friday, May 0, 00 Sheet of