4-Bit ALU Circuit Glitch Reduction for Power Optimization

Transcription

1 4-Bit ALU Circuit Glitch Reduction for Power Optimization For ELEC 6270 Dr. Vishwani D. Agrawal By Hunter Thorington Fall 2015 Abstract ELEC 6270 is an elective offered by Auburn University s Dr. Vishwani D. Agrawal. This paper concludes a semester s worth of studies in low power circuit design. The project I was tasked with was: Redesign a 4-bit ALU circuit for glitch reduction and examine its power saving. In this final semester project, I developed my own VHDL model of a simple ALU and synthesized this design using Leonardo Spectrum. Following synthesis, I used the PTM High Performance 45nm Metal Gate model provided. After applying the model to the netlist, the design was simulated for a base line. Following initial characterization of the circuit, the circuit was enhanced for glitch reduction and low power operation by adding buffers on noncritical paths. The results show a marked 27% decrease in power consumption for the applied test vector. Keywords low power, CMOS, 45nm, gate delay, glitch reduction, power optimization, ALU, Auburn I. INTRODUCTION This report was written for ELEC 6270 Low Power Design of Electronic Circuits for Dr. Vishwani D. Agrawal. This class focused on the design of digital circuit systems for reduced power consumption, power analysis algorithsm, low power MOS technologies, low power design architectures for FPGA, memory and microprocessors and reduction of power in testing of circuits. The project I was assigned was Redesign a 4-bit ALU circuit for glitch reduction and examine its power saving. II. PROJECT BACKGROUND A. Glitch Reduction Circuit power is all about Dynamic Power. Dynamic power or CV2 2, is the amount of power consumed by each gate each time a transistion occurs. A glitch is defined as any intermediate change of state of a signal, whether from high to low or low to high during signal propagation before the final value is reached. These glitches cause unwanted power consumption. B. Boolean Gate Single Transition Theorem This theorem states that for correct operation with minimum energy consumption, a Boolean gate much produce no more than one event per transition. This means that for optimal power reduction signal arriving at the input of a Boolean gate much either arrive at the same time (assuming internal Boolean gate delays are equal) or arrive at nearly the same time in order to produce a single synchronized transition at the output of the gate. If each and every gate in the circuit is held to this theorem the circuit will have minimized power consumption due to glitches. C. Differential Path Delays A multi-input gate will inevitably have differential path delay. This delay occurs when the path from one input to the output respective to another input to the same output is different. Gate with differential path delay inherently introduce glitch power consumption into the circuit. Figure 1. Shows the glitch caused by a multi-input gate with differential path delay. Figure 1. Differential Path Delay In this figure The input A precedes the response of the gate to input B which lags by one time period, this produces a momentary high glitch on the output. This high output draws Figure 2. Glitch Reduced Using a Buffer Delay

2 power from the power supply, but is wasted because it soon returns to the expected value 0. Figure 2 demonstrates that by placing a delay buffer on input A this issue can be reduced. Notice in Figure 2 how the glitch is minimized. Therefore, to ensure glitch reduction, delay A, the input delay must be less than the delay B delay A. This is represented by the equation d < DPD. D. Delay Balance Method The buffer enhanced differential delay method can be extended to circuit wide glitch reduction. The balanced delay method treats the entire circuit as an effectively large Boolean gate, but rather than have delay buffers external to the gate the buffers are internal. Delay buffers are inserted on non-critical paths in the circuit to delay their response to be in time with the critical path. If this method is followed for all non-critical paths through the circuit, all paths will have the same delay. This results creates a circuit with minimal glitch power loss. E. Gate Delay Mathmatical Glitch Suppression Once can define gate delay, the time taken for a signal to propagate from input to output as di. The time differential for each input can be defined as ti the earlies arriving signal, and T i the latest arriving signal. To ensure a glitch is suppressed T i t i < d i F. Linear Programing Buffer Delay Minimization To achieve near optimal power reduction, the minimum number of buffers must be used. While this criterion is nonlinear, one can minimize the sum of the total buffer delays. By minimizing total buffer delay one ensures that a near optimal number of buffers are inserted into the circuit and draw no more power than necessary to reduce glitch power consumption. To many buffers (each drawing power themselves) can increase power consumption rather than reduce. G. ALU Example The slides provided example results from a previous student of this project. The project took a ALU, an industry standard DIP package ALU. The circuit was modified in an undisclosed manner and achieved an average of 21% power reduction. I began my design work for this project by studying the circuit and preparing to optimize the s design for glitch reduction. This proved to be a difficult task to large size of the nearing 75 gates. Also, the circuit schematic would have to be drawn by hand in Design Architect to get a base line. Due to time constraints, I decided to design my own ALU with fewer functions and write it in VHDL allowing it to be synthesized into a gate-level model with which I could then modify. III. PROJECT DESIGN A. VHDL Model of 4-Bit ALU The 4-Bit ALU model for this project was written in VHDL. The ALU has 4 functions add, subtract, add one, and subtract one. This design could clearly be extended to a larger design but was out of scope for this project. The ALU has two inputs A and B which are the two 4 bit unsigned arguments. The output is a 4 bit vector F. The function of the ALU is selected by setting the bus S. entity alu is port( Clk : in std_logic; --clock signal A,B : in unsigned(3 downto 0); --input operands S : in unsigned(1 downto 0); --Operation to be performed F : out unsigned(3 downto 0) --output of ALU ); end alu; architecture Behavioral of alu is signal t1,t2,t3: unsigned(3 downto 0) := (others => '0'); begin t1<= A; t2<= B; F<= t3; process(clk) begin if(rising_edge(clk)) then --Do the calculation at the positive edge of clock cycle. case S is when "00" => t3<= t1 + t2; --addition when "01" => t3<= t1 - t2; --subtraction when "10" => t3<= t1-1; --sub 1 when "11" => t3<= t1 + 1; --add 1 when others => NULL; end case; end if; end process; end Behavioral; B. Synthesis using Leonardo Spectrum The circuit was synthesized using Leonardo Spectrum into TSMC 035 design package for 35nm operation. The resulting circuit contained 26 block level gates and 54 total gates. Leonardo defined the critical path as follows and featured a 1.11ns delay time. Critical path #1, (unconstrained path) NAME GATE ARRIVAL LOAD S(0)/ up 0.04 ix1/y xnor dn 0.07 ix7/y xnor up 0.02 ix9/y xnor dn 0.03 ix134/y aoi up 0.02

3 ix146/y mux up 0.02 ix155/y mux up 0.02 ix89/y xnor dn 0.01 reg_t3(3)/d dff dn 0.00 data arrival time 1.11 C. Vector Selection HSPICE was used to simulate the circuit by applying a test vector set. The test vector set I used contained 1024 test vectors. This represented every possible input combination one time for each operation. These vectors were run 5ns apart for a total of 5120ns to profile the circuit for power consumption. D. Power Analysis Initial Circuit The power analayis for the un modified circuit was run using HSPICE. The result showed 336uW used before glitch reduction. ****** transient analysis tnom= temp= ***** avg_current= E-01 from= E+00 to= E-06 rms_current= E-01 from= E+00 to= E-06 avg_pow= E-01 from= E+00 to= E-06 rms_pow= E-01 from= E+00 to= E-06 powavg= E-01 powrms= E-01 E. Glitch Reduction Design Using Buffer Delays As given earlier, the critical path had a delay of 1.11ns. Using the gate level model of the circuit I determined 8 paths that could be optimized using buffer delays to bring their total path delay near 1.11 ns. These buffer delays are as follows: Path 1: S[1] ix129, ix1, ix7, ix136, ix134, new buffer, ix146, ix155, regt33 Buffer delay added 0.32ns Path 2: S[0], ix129, ix127, ix7, new buffer, ix134, ix146, ix155,ix89,reg33 Buffer delay added 0.33ns Path 3: S[1], new buffer, ix134, ix146, ix155, ix99, reg33 Buffer delay added 0.33ns Path 4: A[0], new buffer, ix11, regt30, Buffer delay added 0.93ns Path 5: S[1], ix127,ix7,ix9, new buffer,ix11 Buffer delay added 0.90ns Path 6: A[1], ix9,new buffer, ix87,ix63,reg32 Buffer delay added 0.27ns Path 7: S[1], ix35, new buffer, ix37,reg31 Buffer delay added 0.35ns Path 8: S[1], ix134, new buffer, ix37,reg31 Buffer delay added 0.38ns F. Power Analysis Final Circuit The power analayis for the modified circuit was run using HSPICE. The result showed 336uW used before glitch reduction. G. Power Analysis Initial Circuit The power analayis for the un modified circuit was run using HSPICE. The result showed 336uW used before glitch reduction. ****** transient analysis tnom= temp= ***** avg_current= E-01 from= E+00 to= E-06 rms_current= E-01 from= E+00 to= E-06 avg_pow= E-01 from= E+00 to= E-06 rms_pow= E-01 from= E+00 to= E-06 powavg= E-01 powrms= E-01 H. Results Comparison Average power consumption A. Results 4-Bit ALU Standard 4-Bit ALU w/ buffer delay glitch reduction % Difference 336uW 243uW 27.6% IV. CONCLUSION This simple ALU designed allowed me to tune in really good results. Using a minimal number of delay buffers, 8, on select non critical paths allow me to make 9 selected paths through the circuit has similar delays. This resulted in fewer glitches and decreased power consumption. While not all paths were optimized and the number of buffers and total buffer delay was not optimized using linear programming I feel this a good results considering the time constraints and project scope. Please see the following pages and appendixes for addition evidence of completed work. B. Overall This project and class was quite enjoyable. I really learned a lot about power reduction and how complex and simple it can be at the same time. Low power devices are the next generation devices that will be made. Battery power and mobile devices rely heavily on reduced power consumption. The design and analysis techniques learned in this class are very applicable to the job market today. I feel I have come away with actionable knowledge ready to be applied and expanded on in my career. REFERENCES [1] Vishwani D. Agrawal, James J. Danaher Professor of ECE 5/course.html [2] Victor P. Nelson, Professor of ECE

4 Circuit Design Before Buffers, Red Line Shows Critical Path Circuit Design After Buffers, Red Line Shows Critical Path, Green Arrows new Buffers

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6 Waveforms demonstrating Glitch Power Reduction After: Glitch and the Power drawn from VDD. Wow! Big Reduction! Before: Glitch and the Power drawn from VDD

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8 Appendix I. Spice Netlist and HSPICE analysis configuration parameters. * LVS netlist generated with ICnet by 'hlt0001' on Wed Apr at 22:39:34 * * Globals. *.inc '45nm_MGK.pm'.global GND VDD.param lam=0.045u.param t=300ns.param tr=0.01ns.param supply=1v.option post brief probe vclk Clk 0 pulse( n.1n 1n 2n) VDD VDD GND supply.vec 'aluvectors.vec' X_alu A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] S[0] S[1] F[0] + F[1] F[2] F[3] Clk alu * * Component pathname : $ADK/parts/mux21 *.subckt mux21 S0 A0 A1 Y M_I$5 Y S0 N$10 VDD pmos L=0.4u W=.045u M_I$13 N$6 A1 GND GND nmos L=0.4u W=2u M_I$12 Y S0 N$6 GND nmos L=0.4u W=2u M_I$17 Y N$7 N$5 VDD pmos L=0.4u W=.045u M_I$16 N$5 A1 VDD VDD pmos L=0.4u W=.045u M_I$7 N$4 A0 GND GND nmos L=0.4u W=2u M_I$6 Y N$7 N$4 GND nmos L=0.4u W=2u M_I$4 N$10 A0 VDD VDD pmos L=0.4u W=.045u M_I$3 N$7 S0 GND GND nmos L=0.4u W=1u M_I$2 N$7 S0 VDD VDD pmos L=0.4u W=1.8u.ends mux21 * * Component pathname : $ADK/parts/inv01 *.subckt inv01 A Y M_I$411 Y A VDD VDD pmos L=0.4u W=1.8u M_I$412 Y A GND GND nmos L=0.4u W=1u.ends inv01 * * Component pathname : $ADK/parts/nand02 *.subckt nand02 Y A0 A1 M_I$472 Y A1 VDD VDD pmos L=0.4u W=2.4u M_I$471 Y A0 VDD VDD pmos L=0.4u W=2.4u

9 M_I$4 Y A0 N$7 GND nmos L=0.4u W=2u M_I$5 N$7 A1 GND GND nmos L=0.4u W=2u.ends nand02 * * Component pathname : $ADK/parts/xnor2 *.subckt xnor2 Y A0 A1 M_I$218 N$213 A1 GND GND nmos L=0.4u W=2u M_I$217 N$212 A0 N$213 GND nmos L=0.4u W=2u M_I$9 N$212 A1 VDD VDD pmos L=0.4u W=2.6u M_I$8 N$212 A0 VDD VDD pmos L=0.4u W=2.6u M_I$7 N$3 N$212 GND GND nmos L=0.4u W=2u M_I$6 Y A1 N$3 GND nmos L=0.4u W=2u M_I$5 Y A0 N$3 GND nmos L=0.4u W=2u M_I$4 Y A1 N$1 VDD pmos L=0.4u W=5.2u M_I$3 Y N$212 VDD VDD pmos L=0.4u W=2.6u M_I$2 N$1 A0 VDD VDD pmos L=0.4u W=5.2u.ends xnor2 * * Component pathname : $ADK/parts/buf16 *.subckt buf16 A Y M_I$1238 N$1022 A GND GND nmos L=0.4u W=100u M_I$1235 N$1022 A VDD VDD pmos L=0.4u W=180u M_I$1233 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$1232 Y N$1022 GND GND nmos L=0.4u W=50u M_I$1231 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$1230 Y N$1022 GND GND nmos L=0.4u W=50u M_I$1229 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$1228 Y N$1022 GND GND nmos L=0.4u W=50u M_I$1227 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$1226 Y N$1022 GND GND nmos L=0.4u W=50u M_I$1023 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$1022 Y N$1022 GND GND nmos L=0.4u W=50u M_I$1021 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$1020 Y N$1022 GND GND nmos L=0.4u W=50u M_I$817 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$818 Y N$1022 GND GND nmos L=0.4u W=50u M_I$614 Y N$1022 VDD VDD pmos L=0.4u W=180u M_I$615 Y N$1022 GND GND nmos L=0.4u W=50u M_I$411 N$1022 A VDD VDD pmos L=0.4u W=180u M_I$412 N$1022 A GND GND nmos L=0.4u W=50u.ends buf16 * * Component pathname : $ADK/parts/aoi22 *.subckt aoi22 B1 A0 A1 B0 Y M_I$425 Y B0 N$9 GND nmos L=0.4u W=2u M_I$426 Y B1 N$4 VDD pmos L=0.4u W=2.6u M_I$12 N$8 A1 GND GND nmos L=0.4u W=2u M_I$11 Y A0 N$8 GND nmos L=0.4u W=2u

10 M_I$7 Y B0 N$4 VDD pmos L=0.4u W=2.6u M_I$6 N$4 A1 VDD VDD pmos L=0.4u W=2.6u M_I$5 N$4 A0 VDD VDD pmos L=0.4u W=2.6u M_I$13 N$9 B1 GND GND nmos L=0.4u W=2u.ends aoi22 * * Component pathname : $ADK/parts/xor2 *.subckt xor2 Y A0 A1 M_I$421 Y N$4 GND GND nmos L=0.4u W=1u M_I$420 Y N$4 VDD VDD pmos L=0.4u W=1.8u M_I$218 N$213 A1 GND GND nmos L=0.4u W=2u M_I$217 N$212 A0 N$213 GND nmos L=0.4u W=2u M_I$9 N$212 A1 VDD VDD pmos L=0.4u W=2.6u M_I$8 N$212 A0 VDD VDD pmos L=0.4u W=2.6u M_I$7 N$3 N$212 GND GND nmos L=0.4u W=2u M_I$6 N$4 A1 N$3 GND nmos L=0.4u W=2u M_I$5 N$4 A0 N$3 GND nmos L=0.4u W=2u M_I$4 N$4 A1 N$1 VDD pmos L=0.4u W=5.2u M_I$3 N$4 N$212 VDD VDD pmos L=0.4u W=2.6u M_I$2 N$1 A0 VDD VDD pmos L=0.4u W=5.2u.ends xor2 * * Component pathname : $ADK/parts/dff *.subckt dff QB Q CLK D M_I$441 N$847 bclk- N$851 GND nmos L=0.4u W=3u M_I$440 N$849 N$847 VDD VDD pmos L=0.4u W=1u M_I$439 N$847 bclk- N$848 VDD pmos L=0.4u W=1u M_I$438 N$848 N$849 VDD VDD pmos L=0.4u W=1u M_I$437 N$847 bclk N$845 VDD pmos L=0.4u W=5.4u M_I$436 N$845 D VDD VDD pmos L=0.4u W=5.4u M_I$452 bclk bclk- GND GND nmos L=0.4u W=2u M_I$673 Q QB GND GND nmos L=0.4u W=2u M_I$672 Q QB VDD VDD pmos L=0.4u W=.045u M_I$669 QB N$1074 GND GND nmos L=0.4u W=2u M_I$675 QB N$1074 VDD VDD pmos L=0.4u W=.045u M_I$668 N$1071 N$1074 GND GND nmos L=0.4u W=1u M_I$667 N$1073 N$1071 GND GND nmos L=0.4u W=1u M_I$666 N$1074 bclk- N$1073 GND nmos L=0.4u W=1u M_I$665 N$1072 N$847 GND GND nmos L=0.4u W=3u M_I$664 N$1074 bclk N$1072 GND nmos L=0.4u W=3u M_I$663 N$1071 N$1074 VDD VDD pmos L=0.4u W=1u M_I$662 N$1074 bclk N$1070 VDD pmos L=0.4u W=1u M_I$661 N$1070 N$1071 VDD VDD pmos L=0.4u W=1u M_I$660 N$1074 bclk- N$1069 VDD pmos L=0.4u W=5.4u M_I$659 N$1069 N$847 VDD VDD pmos L=0.4u W=5.4u M_I$449 bclk- CLK GND GND nmos L=0.4u W=2u M_I$448 bclk- CLK VDD VDD pmos L=0.4u W=.045u M_I$453 bclk bclk- VDD VDD pmos L=0.4u W=.045u M_I$445 N$849 N$847 GND GND nmos L=0.4u W=1u M_I$444 N$852 N$849 GND GND nmos L=0.4u W=1u M_I$443 N$847 bclk N$852 GND nmos L=0.4u W=1u

11 M_I$442 N$851 D GND GND nmos L=0.4u W=3u.ends dff * * Component pathname : /home/u1/hlt0001/4bitalu3/alu *.subckt alu A[0] A[1] A[2] A[3] B[0] B[1] B[2] B[3] S[0] S[1] F[0] F[1] + F[2] F[3] Clk X_ix155 nx60 nx58 nx145 nx154 mux21 X_ix146 nx34 nx32 nx133 nx145 mux21 X_ix136 nx6 nx135 inv01 X_ix129 S[1] nx128 inv01 X_ix159 nx158 B[3] nx128 nand02 X_ix150 nx149 B[2] nx128 nand02 X_ix141 nx140 B[1] nx128 nand02 X_ix127 nx126 B[0] nx128 nand02 X_ix85 nx84 nx0 nx158 xnor2 X_ix87 nx86 N$465 nx84 xnor2 X_ix89 nx88 nx154 nx86 xnor2 X_ix59 nx58 nx0 nx149 xnor2 X_ix61 nx60 A[2] nx58 xnor2 X_ix63 nx62 nx145 nx60 xnor2 X_BUF1614 A[3] N$465 buf16 X_BUF1613 nx34 N$462 buf16 X_BUF1612 nx133 N$14 buf16 X_ix134 N$674 N$27 N$459 N$460 nx133 aoi22 X_BUF1611 A[0] N$253 buf16 X_BUF1610 nx140 N$255 buf16 X_BUF169 nx135 N$27 buf16 X_BUF168 A[0] N$459 buf16 X_BUF167 S[0] N$460 buf16 X_BUF166 S[0] N$676 buf16 X_BUF165 N$676 N$675 buf16 X_BUF164 N$675 N$458 buf16 X_BUF163 N$674 N$673 buf16 X_BUF162 N$673 N$672 buf16 X_BUF161 N$672 N$457 buf16 X_ix33 nx32 nx0 N$255 xnor2 X_ix35 nx34 A[1] nx32 xnor2 X_ix37 nx36 N$14 N$462 xnor2 X_ix1 nx0 S[0] S[1] xnor2 X_ix7 nx6 nx0 nx126 xnor2 X_ix9 N$674 N$253 nx6 xnor2 X_ix11 nx10 N$458 N$457 xor2 X_reg_t3_3 N$dummy_esc1[3] F[3] Clk nx88 dff X_reg_t3_2 N$dummy_esc1[2] F[2] Clk nx62 dff X_reg_t3_1 N$dummy_esc1[1] F[1] Clk nx36 dff X_reg_t3_0 N$dummy_esc1[0] F[0] Clk nx10 dff.ends alu.tran 1ns '4*t'.measure tran avg_current avg i(vdd) from=0ns to='4*t'.measure tran rms_current rms i(vdd) from=0ns to='4*t'.measure tran avg_pow avg p(vdd) from=0ns to='4*t'.measure tran rms_pow rms p(vdd) from=0ns to='4*t'.measure tran powavg param='avg_current*supply'.measure tran powrms param='rms_current*supply'

12 .print i(vdd).print power.probe v(a[0]) v(a[1]) v(a[2]) v(a[3]) v(b[0]) v(b[1]) v(b[2]) v(b[3]) v(s[0]) v(s[1]) v(f[0]) v(f[1]) v(f[2]) v(f[3]) v(clk).end

13 Appendix II. ALU Test Vectors ; start of Pattern Definition section RADIX vname A[[3:0]] B[[3:0]] S[[1:0]] IO I I I period 1 tunit ns slope 0.01 vih 1 vil 0 voh 0.7 vol 0.3 ;Vector Table A 0 0 B 0 0 C 0 0 D 0 0 E 0 0 F A 0 1 B 0 1 C 0 1 D 0 1 E 0 1 F A 0 2 B 0 2 C 0 2 D 0 2 E 0 2 F A 0 3 B 0 3 C 0 3 D 0 3 E 0 3 F A 0 0 B 0 0 C 0 0 D 0 0 E 0 0 F A 1 1 B 1 1 C 1 1 D 1 1 E 1 1 F A 1 2 B 1 2 C 1 2 D 1 2 E 1 2 F A 1 3 B 1 3 C 1 3 D 1 3 E 1 3 F A 2 0 B 2 0 C 2 0 D 2 0 E 2 0 F A 2 1 B 2 1 C 2 1 D 2 1 E 2 1 F A 2 2 B 2 2 C 2 2 D 2 2 E 2 2 F A 2 3 B 2 3 C 2 3 D 2 3 E 2 3 F A 2 0 B 2 0 C 2 0 D 2 0 E 2 0 F A 3 0 B 3 0 C 3 0 D 3 0 E 3 0 F A 3 1 B 3 1 C 3 1 D 3 1 E 3 1 F A 3 2 B 3 2 C 3 2 D 3 2 E 3 2 F A 3 3 B 3 3 C 3 3 D 3 3 E 3 3 F A 3 0 B 3 0 C 3 0 D 3 0 E 3 0 F A 4 0 B 4 0 C 4 0

14 D 4 0 E 4 0 F A 4 1 B 4 1 C 4 1 D 4 1 E 4 1 F A 4 2 B 4 2 C 4 2 D 4 2 E 4 2 F A 4 3 B 4 3 C 4 3 D 4 3 E 4 3 F A 4 0 B 4 0 C 4 0 D 4 0 E 4 0 F A 5 1 B 5 1 C 5 1 D 5 1 E 5 1 F A 5 2 B 5 2 C 5 2 D 5 2 E 5 2 F A 5 3 B 5 3 C 5 3 D 5 3 E 5 3 F A 6 0 B 6 0 C 6 0 D 6 0 E 6 0 F A 6 1 B 6 1 C 6 1 D 6 1 E 6 1 F A 6 2 B 6 2 C 6 2 D 6 2 E 6 2 F A 6 3 B 6 3 C 6 3 D 6 3 E 6 3 F A 6 0 B 6 0 C 6 0 D 6 0 E 6 0 F A 7 0 B 7 0 C 7 0 D 7 0 E 7 0 F A 7 1 B 7 1 C 7 1 D 7 1 E 7 1 F A 7 2 B 7 2 C 7 2 D 7 2 E 7 2 F A 7 3 B 7 3 C 7 3 D 7 3 E 7 3 F A 7 0 B 7 0 C 7 0 D 7 0 E 7 0 F A 8 0 B 8 0 C 8 0 D 8 0 E 8 0 F A 8 1 B 8 1 C 8 1 D 8 1 E 8 1 F A 8 2 B 8 2 C 8 2 D 8 2 E 8 2 F A 8 3 B 8 3 C 8 3 D 8 3 E 8 3 F A 8 0 B 8 0 C 8 0 D 8 0 E 8 0 F A 9 1 B 9 1 C 9 1 D 9 1 E 9 1 F A 9 2 B 9 2 C 9 2 D 9 2 E 9 2 F A 9 3 B 9 3 C 9 3 D 9 3 E 9 3 F A 0 1 A 0 2 A 0 3 A 0 4 A 0 5 A 0 6 A 0 7 A 0 8 A 0 9 A 0 A A 0 B A 0 C A 0 D A 0 E A 0 F A 0 0 A 1 1 A 1 2 A 1 3 A 1 4 A 1 5 A 1 6 A 1 7 A 1 8 A 1 9 A 1 A A 1 B A 1 C A 1 D A 1 E A 1 F A 1 0 A 2 1 A 2 2 A 2 3 A 2 4 A 2 5 A 2 6 A 2 7 A 2 8 A 2 9 A 2 A A 2 B A 2 C A 2 D A 2 E A 2 F A 2 0 A 3 1 A 3 2 A 3 3 A 3 4 A 3

15 5 A 3 6 A 3 7 A 3 8 A 3 9 A 3 A A 3 B A 3 C A 3 D A 3 E A 3 F A 3 0 A 0 1 A 0 2 A 0 3 A 0 4 A 0 5 A 0 6 A 0 7 A 0 8 A 0 9 A 0 A A 0 B A 0 C A 0 D A 0 E A 0 F A 0 0 B 0 1 B 0 2 B 0 3 B 0 4 B 0 5 B 0 6 B 0 7 B 0 8 B 0 9 B 0 A B 0 B B 0 C B 0 D B 0 E B 0 F B 0 0 B 1 1 B 1 2 B 1 3 B 1 4 B 1 5 B 1 6 B 1 7 B 1 8 B 1 9 B 1 A B 1 B B 1 C B 1 D B 1 E B 1 F B 1 0 B 2 1 B 2 2 B 2 3 B 2 4 B 2 5 B 2 6 B 2 7 B 2 8 B 2 9 B 2 A B 2 B B 2 C B 2 D B 2 E B 2 F B 2 0 B 3 1 B 3 2 B 3 3 B 3 4 B 3 5 B 3 6 B 3 7 B 3 8 B 3 9 B 3 A B 3 B B 3 C B 3 D B 3 E B 3 F B 3 0 B 0 1 B 0 2 B 0 3 B 0 4 B 0 5 B 0 6 B 0 7 B 0 8 B 0 9 B 0 A B 0 B B 0 C B 0 D B 0 E B 0 F B 0 0 C 0 1 C 0 2 C 0 3 C 0 4 C 0 5 C 0 6 C 0 7 C 0 8 C 0 9 C 0 A C 0 B C 0 C C 0 D C 0 E C 0 F C 0 0 C 1 1 C 1 2 C 1 3 C 1 4 C 1 5 C 1 6 C 1 7 C 1 8 C 1 9 C 1 A C 1 B C 1 C C 1 D C 1 E C 1 F C 1 0 C 2 1 C 2 2 C 2 3 C 2 4 C 2 5 C 2 6 C 2 7 C 2 8 C 2 9 C 2 A C 2 B C 2 C C 2 D C 2 E C 2 F C 2 0 C 3 1 C 3 2 C 3 3 C 3 4 C 3 5 C 3 6 C 3 7 C 3 8 C 3 9 C 3 A C 3 B C 3 C C 3 D C 3 E C 3 F C 3 0 C 0 1 C 0 2 C 0 3 C 0 4 C 0 5 C 0 6 C 0 7 C 0 8 C 0 9 C 0 A C 0 B C 0 C C 0 D C 0 E C 0 F C 0 0 D 1 1 D 1 2 D 1 3 D 1 4 D 1 5 D 1 6 D 1 7 D 1 8 D 1 9 D 1 A D 1 B D 1 C D 1 D D 1 E D 1 F D 1 0 D 2 1 D 2 2 D 2 3 D 2 4 D 2 5 D 2 6 D 2 7 D 2 8 D 2 9 D 2 A D 2 B D 2 C D 2 D D 2 E D 2 F D 2 0 D 3 1 D 3 2 D 3 3 D 3 4 D 3 5 D 3 6 D 3 7 D 3 8 D 3 9 D 3 A D 3 B D 3 C D 3 D D 3 E D 3 F D 3 0 E 0 1 E 0 2 E 0 3 E 0 4 E 0 5 E 0 6 E 0 7 E 0 8 E 0 9 E 0 A E 0 B E 0 C E 0 D E 0 E E 0 F E 0 0 E 1 1 E 1 2 E 1 3 E 1 4 E 1 5 E 1 6 E 1 7 E 1 8 E 1 9 E 1 A E 1 B E 1 C E 1 D E 1 E E 1 F E 1 0 E 2 1 E 2 2 E 2 3 E 2 4 E 2 5 E 2 6 E 2 7 E 2 8 E 2 9 E 2 A E 2 B E 2 C E 2 D E 2 E E 2 F E 2 0 E 3 1 E 3 2 E 3 3 E 3 4 E 3 5 E 3 6 E 3 7 E 3 8 E 3 9 E 3 A E 3 B E 3 C E 3 D E 3 E E 3 F E 3 0 E 0 1 E 0 2 E 0 3 E 0 4 E 0 5 E 0 6 E 0 7 E 0 8 E 0 9 E 0 A E 0 B E 0 C E 0 D E 0 E E 0 F E 0 0 F 0 1 F 0 2 F 0 3 F 0 4 F 0 5 F 0 6 F 0 7 F 0 8 F 0 9 F 0 A F 0 B F 0 C F 0 D F 0 E F 0 F F 0 0 F 1 1 F 1 2 F 1 3 F 1 4 F 1 5 F 1 6 F 1 7 F 1 8 F 1 9 F 1 A F 1 B F 1 C F 1 D F 1 E F 1 F F 1 0 F 2 1 F 2 2 F 2 3 F 2 4 F 2 5 F 2 6 F 2 7 F 2 8 F 2 9 F 2 A F 2 B F 2 C F 2 D F 2 E F 2 F F 2 0 F 3 1 F 3 2 F 3 3 F 3 4 F 3 5 F 3 6 F 3 7 F 3 8 F 3 9 F 3 A F 3 B F 3 C F 3 D F 3 E F 3 F F 3

16 Appendix III. HPSICE with Buffer Modifications Using: /usr/bin/time -p /linux_apps/synopsys/v2.5/hspice/hspice/linux/hspice -i alu_16buf.sp ****** HSPICE -- E SP1 32-BIT (Feb ) linux ****** Copyright (C) 2010 Synopsys, Inc. All Rights Reserved. Unpublished-rights reserved under US copyright laws. This program is protected by law and is subject to the terms and conditions of the license agreement from Synopsys. Use of this program is your acceptance to be bound by the license agreement. HSPICE is the trademark of Synopsys, Inc. Input File: alu_16buf.sp Command line options: -i alu_16buf.sp lic: No 'setenv LM_LICENSE_FILE' in current environment' lic: lic: FLEXlm: v10.8 lic: USER: hlt0001 HOSTNAME: eelnx165.eng.auburn.edu lic: HOSTID: b PID: lic: Using FLEXlm license file: lic: lic: Checkout 1 hspice lic: License/Maintenance for hspice will expire on 21-jul-2015/ lic: 1(in_use)/50(total) FLOATING license(s) on SERVER perseus.eng.auburn.edu lic: Init: read install configuration file: /linux_apps/synopsys/v2.5/hspice/hspice/meta.cfg **info** (alu_16buf.sp:15) DC voltage reset to initial transient source value in source 0:vclk new dc= D+00 **warning**(nmos:m_i$13)warning: Acde = may be too small in BSIM4 model with w=2e-06 l=4e-07. **info** set option symb=1 internally to help for convergence. ***************************************************************** ****** option summary ****** runlvl = 3 bypass = 2 Opening plot unit= 15 file=alu_16buf.pa0 **info** dc convergence failure, resetting dcon option to 1 and retrying **info** dc convergence successful you can increase the efficiency of the operating point calculation by setting dcon= 1 in the.option statement ****** HSPICE -- E SP1 32-BIT (Feb ) linux ****** ****** * lvs netlist generated with icnet by 'hlt0001' on wed apr at 22:39:34 ****** operating point information tnom= temp= *****

17 ***** operating point status is voltage simulation time is 0. node =voltage node =voltage node =voltage + 0:a[0] = 0. 0:a[1] = 0. 0:a[2] = :a[3] = 0. 0:b[0] = 0. 0:b[1] = :b[2] = 0. 0:b[3] = 0. 0:clk = :f[0] = m 0:f[1] = m 0:f[2] = m + 0:f[3] = m 0:s[0] = 0. 0:s[1] = :vdd = :n$14 = m 1:n$253 = m + 1:n$255 = m 1:n$27 = m 1:n$457 = m + 1:n$458 = m 1:n$459 = m 1:n$460 = m + 1:n$462 = m 1:n$465 = m 1:n$672 = m + 1:n$673 = m 1:n$674 = m 1:n$675 = m + 1:n$676 = m 1:n$dummy_= m 1:n$dummy_= m + 1:n$dummy_= m 1:n$dummy_= m 1:nx0 = m + 1:nx10 = m 1:nx126 = m 1:nx128 = m + 1:nx133 = m 1:nx135 = m 1:nx140 = m + 1:nx145 = m 1:nx149 = m 1:nx154 = m + 1:nx158 = m 1:nx32 = m 1:nx34 = m + 1:nx36 = m 1:nx58 = m 1:nx6 = m + 1:nx60 = m 1:nx62 = m 1:nx84 = m + 1:nx86 = m 1:nx88 = m 2:n$10 = m + 2:n$4 = m 2:n$5 = m 2:n$6 = m + 2:n$7 = m 3:n$10 = m 3:n$4 = m + 3:n$5 = m 3:n$6 = m 3:n$7 = m + 6:n$7 = m 7:n$7 = m 8:n$7 = m + 9:n$7 = m 10:n$1 = m 10:n$212 = m +10:n$213 = m 10:n$3 = m 11:n$1 = m +11:n$212 = m 11:n$213 = m 11:n$3 = m +12:n$1 = m 12:n$212 = m 12:n$213 = m +12:n$3 = m 13:n$1 = m 13:n$212 = m +13:n$213 = m 13:n$3 = m 14:n$1 = m +14:n$212 = m 14:n$213 = m 14:n$3 = m +15:n$1 = m 15:n$212 = m 15:n$213 = m +15:n$3 = m 16:n$1022 = m 17:n$1022 = m +18:n$1022 = m 19:n$4 = m 19:n$8 = m +19:n$9 = u 20:n$1022 = m 21:n$1022 = m +22:n$1022 = m 23:n$1022 = m 24:n$1022 = m +25:n$1022 = m 26:n$1022 = m 27:n$1022 = m +28:n$1022 = m 29:n$1022 = m 30:n$1022 = m +31:n$1 = m 31:n$212 = m 31:n$213 = m +31:n$3 = m 32:n$1 = m 32:n$212 = m +32:n$213 = m 32:n$3 = m 33:n$1 = m +33:n$212 = m 33:n$213 = m 33:n$3 = m +34:n$1 = m 34:n$212 = m 34:n$213 = m +34:n$3 = m 35:n$1 = m 35:n$212 = m +35:n$213 = m 35:n$3 = m 36:n$1 = m +36:n$212 = m 36:n$213 = m 36:n$3 = m +37:n$1 = m 37:n$212 = m 37:n$213 = m +37:n$3 = m 37:n$4 = m 38:bclk = m +38:bclk- = m 38:n$1069 = m 38:n$1070 = m +38:n$1071 = m 38:n$1072 = m 38:n$1073 = m +38:n$1074 = m 38:n$845 = m 38:n$847 = m +38:n$848 = m 38:n$849 = m 38:n$851 = m +38:n$852 = m 39:bclk = m 39:bclk- = m +39:n$1069 = m 39:n$1070 = m 39:n$1071 = m +39:n$1072 = m 39:n$1073 = m 39:n$1074 = m

18 +39:n$845 = m 39:n$847 = m 39:n$848 = m +39:n$849 = m 39:n$851 = m 39:n$852 = m +40:bclk = m 40:bclk- = m 40:n$1069 = m +40:n$1070 = m 40:n$1071 = m 40:n$1072 = m +40:n$1073 = m 40:n$1074 = m 40:n$845 = m +40:n$847 = m 40:n$848 = m 40:n$849 = m +40:n$851 = m 40:n$852 = m 41:bclk = m +41:bclk- = m 41:n$1069 = m 41:n$1070 = m +41:n$1071 = m 41:n$1072 = m 41:n$1073 = m +41:n$1074 = m 41:n$845 = m 41:n$847 = m +41:n$848 = m 41:n$849 = m 41:n$851 = m +41:n$852 = m ****** * lvs netlist generated with icnet by 'hlt0001' on wed apr at 22:39:34 ****** transient analysis tnom= temp= ***** avg_current= E-01 from= E+00 to= E-06 rms_current= E-01 from= E+00 to= E-06 avg_pow= E-01 from= E+00 to= E-06 rms_pow= E-01 from= E+00 to= E-06 powavg= E-01 powrms= E-01 x time current vdd m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

19 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

20 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

21 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

22 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

23 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

24 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

25 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

26 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

27 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

28 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

29 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

30 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

31 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

32 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m

33 n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m n m