Clocked Adiabatic XOR and XNOR CMOS Gates Design Based on Graphene Nanoribbon Complementary Field Effect Transistors

Transcription

1 Clocked Adiaatic XOR and XNOR CMOS Gates Design Based on Graphene Nanorion Complementary Field Effect Transistors Yaser M. Banadaki, Ashok Srivastava and Safura Sharifi Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, U.S.A College of Science, Louisiana State University, Baton Rouge, LA 70803, U.S.A Astract In this paper, graphene nanorion field effect transistors (GNR FET) have een used in design of new energyefficient XNOR/XOR gates ased on clocked adiaatic logic (CAL), which results in the reduction of power density y nearly 65% comparing with the earlier CAL design in 45 nm technology node. In addition, the GNR FET allows scaling of supply voltage, which results in nearly three times reduction in power density. The on-chip power density of new XNOR/XOR gates remains elow the limit reported y the International Technology Roadmap for Semiconductors (ITRS) up to the operation frequency of aout 1GHz at the scaled supply voltage equal to 0.7V. Keywords GNR FET, XNOR/XOR gates, clocked adiaatic logic, power density, scaled supply voltage I. INTRODUCTION Although aggressive scaling of transistor dimensions and increasing chip complexity has satisfied the demand for increasing the performance of integrated circuits, reducing the power dissipation has een always a major research effort for applications in portale devices. At the device level, the reduction in power dissipation has een achieved mainly y scaling down the supply voltage and reducing capacitances with the scaling of transistors and interconnects. However, transistor and interconnect dimensions are limited in size due to physics ehind it. Furthermore, small geometry effects in MOS FETs [1] play a major role in the performance of integrated circuits as it increases the leakage current and consequently the static power dissipation. The well-known Moore s law is nearly approaching to an end in next decade, there is increasing efforts in search of new materials such as caron nanotues (CNT) [2] and graphene [1, 3] possily sustituting silicon in integrated circuits. ITRS has predicted that the higher carrier moilities in these materials allow more aggressive supply voltage scaling at the same time with higher drive current than in silicon MOSFETs, resulting in improvement in oth speed and power dissipation [4]. Graphene is a promising alternative to silicon due to its atomically thin planar structure, high carrier concentration, high carrier moilities and thermal conductivity [5]. Patterning narrow stripes of graphene known as graphene nanorions (GNR) can open a and gap of several hundred mev due to the Corresponding author ashok@ece.lsu.edu quantum confinement of carriers [6] in order to make GNR field effect transistor suitale for logic applications. At the circuit level, the reduction in energy loss or heat dissipation can e otained in energy recovery techniques [7] using the two key rules of clocked adiaatic logic: Never turn-on a transistor when there is a potential difference across it, and never turn-off a transistor when current is flowing through it. Novel GNR FET-ased circuits can e desired for ultra-low energy operation. The exclusive-or (XOR) and exclusive-nor (XNOR) gates play an important role in ALU of core processors [8, 9]. XOR/XNOR gates have een implemented in energy recovery CMOS circuits [10] and in emerging technologies ased on caron nanotues [11]. In this work, we extend our design of XOR/XNOR gates to a new clocked adiaatic logic using an emerging 2D material (graphene) ased FETs. The proposed GNRFET-ased XOR/XNOR gates can work with the scaled supply voltage, V DD down to 0.7V at 45 nm technology node. Fig. 1. (a) Schematic of GNR FET, () dispersion relation of GNR(13,0) and (c) equivalent circuit of GNR FET.

2 It can reduce the energy dissipation and power density elow the reported value in ITRS [4]. In Section II, the model equation and equivalent circuit model of GNR FET are descried. Several CAL XOR/XNOR circuits and the proposed GNR FET-ased CAL XOR/XNOR circuits are presented for use in SPICE and results are presented in Section III followed y conclusion in Section IV. II. GNR FET MODEL The GNR FET structure is shown in Fig. 1(a), where the rion of armchair chirality GNR (13,0) is the channel material in MOSFET-like structure. The nanorion under the gate is intrinsic while the extension regions etween the gate regions and the source and drain contacts are doped with the concentration of n-type dopants per caron atom to form Ohmic contacts. The insulator layer is aluminum nitride (AlN) with the relative dielectric permittivityκ = 9 and thickness t ox = 1nm, which can e deposited on graphene with good uniformity and reproduciility [12]. The length and width of the channel are L G = 45nm and W G = 5.0 nm, respectively. The supply voltage V DD is 1.1V for 45 nm technology node, which Fig. 3. Circuit schematic of the new CAL XOR/XNOR gate. has een scaled down to 0.7V to show the low voltage operation of GNR FETs for decreasing power density in the proposed XOR/XNOR gates. The quantum confinement of carriers in one dimensional structure of armchair-gnr opens a and gap of Eg = 0.86eV for GNR(13,0) and fulfills the requirement of low-power logic application [3]. The dispersion relation of GNR(13,0) has een otained using tight-inding calculation ased on nearest neighor orthogonal p z oritals as asis functions [13, 14] shown in Fig. 1(). The corresponding energy, E and effective mass, m of the lowest suands are otained as shown in Tale 1 in order to use in calculation of the thermionic drain-source current, I th, the and-to-andtunneling current, I BTBT, and the channel charge, Q CH. Landauer-Buttiker formulism [6] descries the drain-source current of each suand. Assuming the unity transmission coefficient (T) for the energy range of integration and using Fermi-Dirac integral of order 0, an analytical expression of the thermionic current can e otained as follows [15], I th 2qkTr EFS EC EFD EC = [ln(1 + ) ln(1 + )] (1) h kt kt Fig. 2. Circuit schematics of (a) 2N-2N2P XNOR/XOR, () asic CAL XOR/XNOR and (c) PL-GL CAL XOR/XNOR. where h is Planck s constant, q is an electron charge, k is Boltzmann constant, T is asolute temperature, T r is the transmission coefficient, EFS = qvs and EFD = qvd are the Fermi levels at source and drain contacts, respectively corresponding to source V S and drain V D voltages. The conduction and is E C = E qψ ch, where Ψ ch is channel potential calculated y equating the charges implied y the potentials of terminals in the channel to total charges across the all capacitors coupled into the channel [16, 17]. The channel charge is otained y summation over the carrier density of suands as follows,

3 Tale 1. Energy E and effective mass m of the lowest suands otained from tight-inding calculation Armchair GNR(13,0) qlg E ( EFS EC) E ( EFD EC) QCH = [ ( f( ) f( )) D ( E) de] kt kt (2) 1 where f( x) = {1+ exp( x)} is the Fermi-Dirac distriution function. The integral in Eq. (2) has no closed-form solution unless approximated y Boltzmann distriution, f( x) exp( x) for non-degenerate situation ( EF E) > 3kT [15] or the weighted comination of Boltzmann distriution with step function [16]. D ( E) is the density of states (DOS) in GNR, which relates to the energy and effective mass of suand, as follows [15], 2( E + E) m D ( E) = (3) π EEE ( + 2 E) The thermionic current strongly dominants the carriers transport at very high drain voltages, however, the and-toand tunneling, I BTBT, can e important in suthreshold region at small gate voltage and sufficiently high V DS. When the conduction and at the drain side can e elow the valance and at channel side, i.e. VCH, D > 2E, it can e calculated as follows [18], 2q I k T T Minimum Conduction Band Energy Suand #1 E1 = 0.43eV Suand #2 E2 = 0.61eV Suand #3 E3 = 1.49eV Suand #4 E4 = 1.58eV Effective Mass m = 0.11m 1 0 m = 0.108m 2 0 m = 0.19m 3 0 m = 0.65m exp(( qv E E )/ k T ) CH, D F B BTBT = B [ BTBT ln( )] h 1+ exp(( E EF)/ kbt) (4) where T BTBT is the Wentzel Kramers Brillouin transmission coefficient and is calculated following the work of Kane [19] as follows, 2 (1/2) 3/2 π πm ( η2 E) TBTBT exp ( ) (5) 3/2 9 2 q F where F = ( VCH, D + ( EF Ψch )/ q)/ lrelax is the electrical field triggering the tunneling process through the junction at the drain side of the GNR channel. η = 0.5 is a fitting parameter that represents the andgap narrowing effect under high electrical field [20] and lrelax = 40nmis the relaxation length of potential drop, V CH, D, across the drain-channel junction. The equivalent circuit of GNR FET is shown in Fig. 1(c) [21], which has een implemented in SPICE circuit simulator as a su-circuit of a GNR FET. The circuit has a current source which models the current flowing through the GNR channel calculated y the summation of thermionic current, I th (Eq. (1)) and the BTBT current, I BTBT (Eq. (4)). CCH, S and CCH, D are two intrinsic capacitors which are given y CCH, S = QCH VS and C = Q V. The capacitors etween gate to channel, CH, D CH D CGCH, and sustrate to channel, CSUB, CH are geometrical capacitors [16]. The resistor, Ri models the series resistance of contact i, which can e made negligile y using local GNR interconnects in all-graphene structure [22] since it is much shorter than the mean free path of graphene [23]. III. ENERGY RECOVERY LOGIC AND SIMULATION RESULTS We have simulated different energy-efficient GNR FETased XOR/XNOR circuits as done in conventional CMOS circuits [2]. Figure 2(a) shows 2N-2N2P XNOR/XOR circuit [24] as a modified version of efficient charge recovery logic (ECRL) and stated under partial energy recovery logic family [7]. In the circuit, the cross-coupled inverters latch the output and the required logic of XNOR = (A+B) (A+B) and XOR=(A B)+(A B) are then implemented y two complementary networks. The cross-coupled inverters stailize the output logic and two complementary pull-down networks increase the speed of discharging the inverters tree during the evaluation phase. Figure 2() shows clocked adiaatic logic (CAL) [10, 25], where a clock signal controls transistors M1 and M2 allowing the inverter circuit to operate with a single clocked power supply, Φ and hold the output logic value corresponding to the previous evaluation phase when the clock signal disconnect the input logic network from the crosscoupled inverters [25]. Adding M3 and M4 in Fig. 2(c) can Fig. 4. Input and output waveforms of the new CAL XOR/XNOR circuit.

4 Fig. 5. Power density versus frequency for different XOR/XNOR circuits. insulate the input part from the logic output part in order to cancel the leakage path of eight transistors of input networks. The complementary input logic networks are called the powerless (PL) XOR and ground-less (GL) XNOR circuits [8]. PL- GL CAL XOR/XNOR circuits transfer the asic disadvantage of their inputs to outputs, such that these display ad output levels and poor delay characteristics. These circuits cannot function properly y scaling down the supply voltage [8]. In this work, we have improved GNR FET-ased CAL XOR/XNOR as shown in Fig. 3 which consumes less power than the other CAL circuits [10]. The implementation of oth input logic networks are comined in one circuit using only six transistors [26]. Likewise in input circuits of Fig. 2(c), there are a single connection to a clocked power supply, Φ and a single connection to ground with no direct path etween them which avoids the short circuit currents while allowing the scaling of supply voltage. In addition, the input network doesn t need complementary of inputs A and B in the circuits of Fig. 2 and has two transistors less than in Fig. 2(c) for reduced power consumption. Figure 4 shows input and output waveforms of the proposed CAL XOR/XNOR. Switching power clock, Φ has the trapezoid waveform with the same duration as the input waveforms A and B. In the evaluation phase, the clock signal, CLK enales the logic evaluation, which restores in latch configuration implemented y the cross-coupled inverters. In the hold phase, the CLK disales the logic evaluation and the previously stored logic state repeats at outputs regardless of current input signals. It can e seen that the circuit can operate at the scaled supply voltage, V DD equal to 0.8V. The possiility of andgap engineering allows to reduce the threshold voltage of GNR FET corresponding to the andgap implied y GNR width. Thus, there is another degree of freedom eside the channel length for GNR FET-ased circuits, such that the proposed GNR FET circuits can operate at a much reduced supply voltage. In conventional MOSFET, the andgap of silicon is fixed, threshold voltage and the corresponding supply voltage depend upon the choice of gate electrode material, dielectric constant and thickness of oxide layer and sustrate doping. Threshold voltage in GNR FET can e tuned y the andgap engineering of GNR such that wide GNR FETs can operate under scaled supply voltages. Thus, high-moility materials like GNR in channel can reduce the dynamic power consumption (CV 2 DD f ) resulting in net improvement in oth speed and power dissipation as reported in ITRS [4]. In addition, the effective mass of electrons and holes is same in GNR FET such that complementary GNR FET can operate at scaled voltages without the need for increasing the physical channel width in the pull-up network as d CMOS logic. The power density on a chip is a key consideration for down-scaling of VLSI circuits. The power density PD can e calculated as follows [7], P PD = (6) α A where P is the total power consumption, A is the active area of transistors and α is the area factor which accounts for the chip area in routing. We have assumed α = 4 [7] in our simulations. Figure 5 shows the power densities of the XOR/XNOR circuits of Fig. 2 and our new CAL XOR/XNOR circuit in Fig. 3 at different frequencies for the supply voltage 1.1V of 45 nm technology node. It can e seen that the power densities of all the circuits are increased y increasing the operation frequency while the new CAL XOR/XNOR has the least power density and decreases the power density y nearly 65% comparing with the PL-GL CAL XOR/XNOR circuit. However, the power density at 1.1V for 45 nm technology node is still aout Fig. 6. Power density versus frequency y scaling the supply voltage from 1.1V for 45 nm technology node down to 0.7V for GNR FET-ased circuits. (a) 2N-2N2P XOR/XNOR gates, () asic CAL XOR/XNOR gates, (c) PL- GL XOR/XNOR gates and new CAL XOR/XNOR gates.

5 Tale 2. power-delay product (PDP) of PL-GL and the new-cal XOR/XNOR gates for the implantations ased on GNR FET and conventional CMOS at V DD = 0.7V, f = 3MHz and V DD = 0.9V, f = 60MHz. 20 times higher than the limit in ITRS [4]. The advantage of GNR FET which has the high-moility channel can provide some relief y allowing more aggressive V DD scaling [4]. Figure 6 shows the reduction in power densities of the ERL circuits y scaling down the supply voltage from 1.1V to 0.7V. It can e seen that new CAL XOR/XNOR circuit can consume much less power and can satisfy the tolerale power density up to aout 1GHz for V DD = 0.7V. However, the circuit cannot operate in frequencies higher than 1GHz in V DD = 0.7V, such that the circuit designers have to use higher supply voltage for higher frequencies while still keeping the power density within the acceptale level. The power-delay product (PDP) is a figure of merit correlated with the energy efficiency of a logic gate. Tale 2 shows the PDP of PL-GL and the new CAL XOR/XNOR gates ased on GNR FETs and CMOS at two different supply voltages and operation frequencies. The CMOS implementation used 45nm high-performance liraries from Predictive Technology Model (PTM [27]) for the same device geometries as GNR FETs. In Tale 2, comparing two rows shows the effectiveness of the proposed CAL XOR/XNOR gates in reducing the PDP while comparing two columns shows the importance of GNR FET for low-power integrated circuit design. For V DD = 0.7V and f = 3MHz, it can e seen that the CMOS implementation of PL-GL XOR/XNOR gates 18 shows the PDP equal to watt. s while its implementation with GNR FET reduces the PDP to watt. s, leading to ~ 33% reduction. However, the major PDP reduction can e otained y changing the design to the proposed new CAL XOR/XNOR gates, which results in 18 approximately 7 times reduction of PDP to watt. s. At the higher frequency, f = 60 MHz, we have to increase V DD to 0.9V as the CMOS cannot operate at the scaled supply voltage of 0.7V. For V DD = 0.9V and f = 60MHz, the same power reduction can e oserved due to oth the modification in the CAL circuit design and the implantation of the circuit using GNR FET. It can e seen that at V DD = 0.9V and f = 60 MHz, the GNR FET implementation of new-cal has ~ 60% more PDP than the operation at V DD = 0.7V and f = 3MHz while its CMOS implantation shows approximately 4 times increase in PDP, indicating the importance of GNR FET for low-voltage and high frequencies operation. In our recent work [1], we have shown using quantumased atomistic simulation that higher moility of GNR channel results in higher current density and therey the GNR FET-ased logic shows lower PDP than the CMOS-ased logic. We have shown that the narrow GNR channel has larger andgap and exhiits superior static performance than wider GNRs, reduced static power consumption. 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