Hot-Carrier Reliability Comparison for pmosfets With Ultrathin Silicon-Nitride and Silicon-Oxide Gate Dielectrics

Transcription

1 158 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 3, SEPTEMBER 2001 Hot-Carrier Reliability Comparison for pmosfets With Ultrathin Silicon-Nitride and Silicon-Oxide Gate Dielectrics Igor Polishchuk, Student Member, IEEE, Yee-Chia Yeo, Student Member, IEEE, Qiang Lu, Student Member, IEEE, Tsu-Jae King, Member, IEEE, and Chenming Hu, Fellow, IEEE Abstract The degradation of 100-nm effective channel length pmos transistors with 14 Å equivalent oxide thickness Jet Vapor Deposition (JVD) Si 3 N 4 gate dielectric under hot-carrier stress is studied. Interface-state generation is identified as the dominant degradation mechanism. Hot-carrier-induced gate leakage may become a new reliability concern. Hot-carrier reliability of 14 Å Si 3 N 4 transistors is compared to reliability of 16 Å SiO 2 transistors. Index Terms Degradation mechanism, interface states, stressinduced leakage current, substrate current. I. INTRODUCTION AS GATE-OXIDE thickness in MOS devices is reduced, the increasing gate leakage current poses a major challenge to continued transistor scaling. Reliability of the ultrathin SiO presents another major concern. Therefore, a transition to a gate material with a higher dielectric constant is critical for further CMOS scaling. A number of high-k dielectrics, such as Ta O [1], Al O [2], La O [2], ZrO [3], HfO [4], and several silicates have been proposed to replace SiO in the gate stack. Stability of these materials in contact with silicon during high-temperature processing steps remains a major problem. Therefore, it might be a few years before a successful integration of a high-k dielectric into CMOS fabrication process becomes reality. At the same time, Si N, which has a relatively high dielectric constant of 7.5 (almost twice that of SiO ), has been used by the semiconductor industry for decades and is relatively easy to integrate into the fabrication process. Good performance of Si N transistors has already been demonstrated [5], [6]. However, it is necessary to demonstrate good reliability of thin Si N before it can replace SiO as gate dielectric. Studies of time-dependent dielectric breakdown [5], [7] and time-dependent dielectric wearout [8] indicate that Si N under Fowler Nordheim stress meets reliability requirements. It still remains to be shown that hot-carrier reliability of Si N gate dielectrics is acceptable. Earlier work [7] indicates good hot-carrier reliability of nmosfet Jet Vapor Deposition (JVD) nitride transistors with Manuscript received July 19, 2001; revised October 5, This work was supported by Semiconductor Research Corporation under Contract SRC The work of I. Polishchuk was supported in part by NIST and SRC through the Graduate Fellowship Program. The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA USA ( igorp@eecs.berkeley.edu). Publisher Item Identifier S (01) Å equivalent oxide thickness. In this paper, we will show that the hot-carrier lifetime of Si N pmosfets is similar to that of SiO pmosfets. We also examine the mechanism responsible for pmosfet degradation. It has been long known that the mechanism responsible for the device degradation in nmosfet is interface-state generation. The situation for pmosfets is less clear. It had long been believed that hot-carrier reliability of pmosfets is not as serious an issue as hot-carrier reliability of nmosfets for the following reason. The mean free path of holes in silicon is about one half that of the electrons [9]; therefore, holes scatter more frequently and fewer of them reach high enough energies (about 4 ev) to create interface states [10]. However, as the transistor channel length has been scaled down into the deep-submicron regime (and supply voltages have been reduced) hot-carrier induced degradation of pmosfets has been approaching that of nmosfets [11]. Consequently, the hot-carrier reliability of pmosfets has been studied in more detail. Three hot-carrier degradation mechanisms in pmosfets have been identified [12], [13]. The first is negative oxide charge trapping. Electron trapping near the drain region leads to a reduction in the threshold voltage and to the effective channel shortening. As a result, pmosfet drive current increases. This mechanism is most important in longer channel pmosfets, and gate current has been used as a predictor of the device lifetime. The second mechanism is the generation of interface states by hot holes, which leads to channel mobility degradation. In this case, the substrate current should be used to predict the device lifetime, and the third mechanism is positive oxide charge trapping. Interface-state generation has been shown to be the dominant degradation mechanism for m surface channel pmosfets [12]. We will show that this conclusion remains true for our 100-nm devices, for both oxide and nitride gate dielectrics. II. DEVICE FABRICATION AND CHARACTERIZATION A. Fabrication Stage The Si N transistors with 100-nm channel length were made using a LOCOS-isolation CMOS process without halo implant. The silicon nitride gate dielectric was deposited by Jet Vapor Deposition (JVD) [14] at Yale University. Following a 5-min 800 C anneal in N, undoped poly-si was deposited by LPCVD. -line lithography and photoresist ashing in O /01$ IEEE

2 POLISHCHUK et al.: HOT-CARRIER RELIABILITY COMPARISON FOR pmosfets 159 Fig. 1. Equivalent oxide thickness is extracted from C V characteristics using a quantum mechanical simulator. Fig. 2. Silicon-nitride pmosfets have lower mobility, but higher current drive (at V ) than silicon-oxide pmosfets. L=W =0:1=1m. plasma were used to define gate electrodes down to 100 nm. Following the gate patterning, source and drain regions were formed by ion implantation. A dose 1 10 cm was used to form the source and drain extensions in pmosfets. Dopants were activated by rapid thermal annealing in N. The SiO transistors used in this study for comparison purposes were fabricated using a similar process. B. Characterization The gate-dielectric equivalent oxide thickness is extracted using a quantum mechanical simulator [15]. The quantum mechanical simulator solves Poisson s and Schrödinger s equations self-consistently in order to determine the precise inversion/accumulation charge distribution in the substrate at various gate bias conditions. This charge distribution is then used to produce a simulated capacitance versus voltage characteristic. The values of the oxide-equivalent dielectric thickness and the substrate doping concentration are varied until a good match to the experimental data is achieved. The simulator also considers the voltage drop in the polysilicon gate electrode in order to account for the polysilicon depletion effect (the decrease in the gate capacitance in the strong inversion regime.) For the nitride transistors, is 14 Å and n-well doping concentration is 4 10 cm (Fig. 1). For the oxide transistors, is 16 Å and n-well doping concentration is 7 10 cm. Fig. 2 shows the output current characteristics for both types of transistors. At low drain bias, the oxide transistor has a higher drain current. This is due to the well-known fact that nitride transistors have lower channel mobility. At high drain bias (close to the supply voltage), the situation is reversed, and the nitride transistor has a higher current drive. This higher current drive can be explained by higher inversion charge density in 14 Å Si N transistors. The major advantage of the Si N gate dielectric is the reduction of the gate leakage current (Fig. 3). The leakage current of the 14 Å Si N pmosfet is an order of magnitude lower than that of the 16-Å SiO pmosfet. The reduction in the gate leakage current for nmosfets is even larger [16]. III. DEVICE FABRICATION AND CHARACTERIZATION The drain voltage during the hot carrier stress ranged from 4.5 to 6.5 V; the gate voltage was chosen to Fig. 3. Even though Si N s equivalent oxide thickness is less than that of SiO by 2 Å, it provides over an order of magnitude reduction in gate leakage current. TABLE I PEAK I STRESS CONDITIONS FOR Si N TRANSISTORS (L=W = 0:1=1 m) maximize the substrate current. The exact stress conditions for each of the nitride transistors are listed in Table I. As we have outlined in the introduction, hot-electron injection becomes a relatively less important mechanism of pmosfet degradation as the channel length becomes shorter than 0.25 m [12], [13], [17]. Therefore, we do not expect the stress at low ( ), which favors hot-electron injection, to be the worst-case stress condition. Many recent papers were dedicated to the discussion of whether stress at maximum gate voltage ( ) or stress at maximum substrate current leads to the fastest device degradation [17], [18]. We chose to use

3 160 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 3, SEPTEMBER 2001 (a) Fig. 5. Degradation of Si N pmosfet parameters. (b) Fig. 4. Degradation in (a) transconductance and (b) gate leakage current as a result of hot-carrier stress. (Stress V = 06:5 V, stress time = 500 s). the stress at maximum, since the stress at maximum would not have been practical in our case. Applying such a high gate voltage to our ultrathin dielectrics would lead to rapid device degradation under Fowler Nordheim (FN) (rather than hot-carrier) stress. For example, the transconductance of a JVD transistor under 4.5 V stress would drop by 10% in about 2 s [8], while the same amount of degradation due to hot carrier stress under peak condition takes 5 10 s. (Extrapolated lifetime under 2-V FN stress is in excess of 10 s [8].) The hot-carrier stress was periodically interrupted, and transistor parameters such as saturation drain current, linear drain current, threshold voltage shift, peak transconductance, subthreshold swing, and gate leakage current were monitored. An example of device degradation is shown in Fig. 4. Degradation in transconductance [Fig. 4(a)] and associated degradation in drive current are especially important factors which affect circuit performance. We chose to define the device lifetime as the time to reach 10% degradation in (drain current measured at V and mv). degradation follows exactly the same time dependence as the degradation in peak transconductance, while changes by 4% for every 10% change in (Fig. 5). This is expected, since both and are directly proportional to hole channel mobility, while depends on the hole saturation velocity as well as mobility. We attribute the increase in the gate leakage current observed in Fig. 4(b) to trap-assisted tunneling. These traps are created in the gate dielectric by hot carriers. This increase in the gate leakage current can become a reliability concern for logic transistors with ultrathin gate dielectrics, as it can lead to increased Fig. 6. Positive 1V corresponds to electron trapping, negative 1V to hole trapping and interface trap generation. power consumption. The changes in next section. will be discussed in the IV. RESULTS AND DISCUSSION A. Hot-Carrier Degradation Mechanism We examine the mechanism responsible for the device degradation by examining the change in the threshold voltage (Fig. 6). In the early stages of stress, electrons are trapped in the gate dielectrics as indicated by the positive. Electron trapping follows a logarithmic dependence on time [12]. This is consistent with a model in which the electrons are created by impact ionization near the drain region, propelled toward the gate electrode by the vertical electric field, and captured by the traps which exist in the dielectric. Silicon nitride is known to have a higher density of traps than silicon oxide; in addition, its physical thickness is almost twice that of the oxide, hence, silicon nitride shows a larger positive. In the later stages of stress, becomes negative indicating a positive charge buildup in the gate dielectric. The positive charge can result from either hole trapping in the dielectric or the creation of positively charged interface states at the dielectric interface. In practice, it may be hard to draw a distinction between the two phenomena, as it is hard to distinguish between bulk and interface traps in the case of ultrathin dielectrics. We believe that interface state generation is predominant, as the electric field near the drain does not favor hole injection in the dielectric. Furthermore, the change in becomes a power-law function of time, consistent with the interface generation model [12].

4 POLISHCHUK et al.: HOT-CARRIER RELIABILITY COMPARISON FOR pmosfets 161 Fig. 7. Similar LDD design results in similar I versus V characteristic. Fig. 9. Transistor lifetime extrapolation. L = 0:1 m. Fig. 8. Transistor lifetime depends on I, but not on the gate dielectric or the LDD design. the lifetime of the Si N transistors against the lifetime of the control SiO devices. Also included in Fig. 7 is the substrate current measured for SiO devices with a more aggressive (higher doping) LDD design. At a given, these devices have a higher peak electric field, and therefore a higher. Lower lifetime for these devices should be expected at a given. One still should be able to compare the lifetimes of different dielectrics if the comparison is made at the same.(we have already confirmed that interface-state generation by hot holes is the major degradation mechanism; therefore, is the correct lifetime predictor.) Fig. 8 shows that the lifetime follows the same power-law dependence on with the slope of 1.5 commonly observed for pmosfets [10], [20] for the devices with different gate dielectrics and different LDD designs. To further support the interface-state generation model, we note that the result of the charge trapping alone on device performance is quite modest. A s stress at V leads to a 40-mV shift in ; this would translate approximately into a 3% change in. In reality, however, drain current changes by more than 10% during this stress. Essentially, all of the degradation in is due to the decrease in hole mobility. Therefore, interface-state generation is the dominant degradation mechanism. B. Lifetime Comparison Between Si N and SiO Devices Our next task is to determine the reliability properties of gate nitride as expressed by the hot-carrier lifetime. In general, hot-carrier lifetime depends on the properties of the gate dielectric as well as on LDD design. Thus, simply determining the lifetime of transistors with a new gate dielectric is rather meaningless. Instead, the lifetime of the Si N devices should be compared to the lifetime of SiO devices with a similar LDD design. We verified that our nitride and oxide transistors are indeed comparable in terms of source drain engineering by comparing the substrate currents in these devices. Substrate current is an exponential function of the peak electric field in the channel pinch-off region [19]. Since both device types have the same peak as a function of drain voltage (Fig. 7), the electric field in the pinch-off region is the same for these two device types at a given. Therefore, we can directly compare V. SUMMARY AND CONCLUSION We have found that the hot-carrier lifetime of pmosfets with JVD nitride gate dielectric is similar to that of devices with SiO gate dielectric. This conclusion is in agreement with the observation by other researchers [21] that interface generation in oxide and oxynitride pmosfets is insensitive to nitridation. The reason behind this insensitivity is likely to be the fact that hot carriers cause damage to the silicon surface [19]. We have also confirmed that interface-state generation remains the dominant device degradation mechanism for deep-submicron pmos- FETs. Therefore, should be used as the predictor of device lifetime. The lifetime of transistors as a function of is shown in Fig. 9. The extrapolation to low operating voltages indicates that a supply voltage of around 3.8 V would lead to a 10-year lifetime for both Si N and control SiO transistors. This high voltage is explained by the conservative LDD design in our devices. A more aggressive LDD design would lead to a 2.2-V supply voltage limit, while improving the transistors current drive. In conclusion, we have shown that hot-carrier reliability of Si N transistors is no worse than that of SiO transistors. In addition, a 14-Å Si N pmosfet has higher and lower gate leakage current than a 16-Å SiO pmosfet. This makes Si N a promising alternative to SiO as the dielectric of choice for future generations of CMOS devices.

5 162 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 3, SEPTEMBER 2001 ACKNOWLEDGMENT Device fabrication was done in the Microfabrication Laboratory of the University of California at Berkeley. JVD nitride was deposited at Yale University. REFERENCES [1] D. Park, Y.-C. King, Q. Lu, T.-J. King, C. Hu, A. Kalnitsky, S.-P. Tay, and C.-C. Cheng, Transistor characteristics with Ta O gate dielectric, IEEE Electron Device Lett., vol. 19, p. 441, [2] A. Chin, Y. Wu, S. Chen, C. Liao, and W. Chen, High quality La O and Al O gate dielectrics with equivalent oxide thickness 5 10Å, in Dig. Tech. Papers, 2000 Symp. VLSI Technology, p. 16. [3] Y. Ma, Y. Ono, L. Stecker, D. R. Evans, and S. T. Hsu, Zirconium oxide based gate dielectrics with equivalent oxide thickness of less than 1.0 nm and performance of submicron MOSFET using a nitride gate replacement process, in Int. Electron Devices Meeting 1999 Tech. Dig., p [4] L. Kang, Y. Jeon, K. Onishi, B. H. Lee, W.-J. Qi, R. Nieh, S. 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Hu, Modeling of substrate current in pmosfets, IEEE Electron Device Lett., vol. EDL-8, p. 413, [10], Hot-carrier current modeling and device degradation in surface-channel pmosfets, IEEE Trans. Electron Devices, vol. 37, pp , [11] T. Tsuchiya, Y. Okazaki, M. Miyake, and T. Kobayashi, New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET, IEEE Trans. Electron Devices, vol. 39, pp , Feb [12] R. Woltjer, G. M. Paulzen, H. G. Pomp, H. Lifka, and P. H. Woerlee, Three hot-carrier degradation mechanisms in deep-submicron PMOS- FETs, IEEE Trans. Electron Devices, vol. 42, p. 109, [13] A. Bravaix, Hot-carrier degradation evolution in deep-submicrometer CMOS technologies, in IEEE Int. Integrated Reliability Workshop, Final Report, 1999, pp [14] T. P. Ma, Making silicon nitride film a viable gate dielectric, IEEE Trans. Electron Devices, vol. 45, p. 680, [15] Quantum Mechanical CV Simulator. Univ. of California, Berkeley. [Online]. Available: [16] Y.-C. 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VLSI Technology, p. 82. [21] J. F. Zhang, H. K. Sii, G. Groeseneken, and R. Degraeve, Degradation of oxides and oxynitrides under hot hole stress, IEEE Trans. Electron Devices, vol. 47, p. 378, Igor Polishchuk (S 98) received the B.Sc. degree in physics from the California Institute of Technology, Pasadena, in 1997 and a M.S. degree in electrical engineering from the University of California, Berkeley, in He is currently working toward the Ph.D. degree at the University of California, Berkeley. His research interests include reliability of ultrathin gate oxides and high-k dielectrics, metal gate technology, and carrier transport modeling in MOS devices. Mr. Polishchuk received the California Fellowship in Microelectronics in 1997 and currently holds the SRC/NIST Graduate Fellowship. Yee-Chia Yeo (S 98) received the B.Eng. degree with first class honors and the M.Eng. degree from the National University of Singapore (NUS), both in electrical engineering. He is currently working toward the Ph.D. degree in electrical engineering at the University of California, Berkeley. He has worked on the characterization of lasers for low-cost optoelectronics at the British Telecommunications Laboratories, Ipswich, U.K., and also on the study of GaN-based quantum-well lasers at NUS. His research interests include MOS device physics, sub-100-nm device fabrication, strained SiGechannel MOSFETs, metal gates, and advanced gate dielectrics. Mr. Yeo was awarded the 1995 IEE Prize, the 1996 Lee Kuan Yew Gold Medal, and the 1996 Institution of Engineers, Singapore (IES) Gold Medal for being the best undergraduate in electrical engineering at NUS. He is also the recipient of the Overseas Graduate Scholarship from NUS. Qiang Lu (S 01) received the B.S. degree in physics from Peking University, China, in He is currently a graduate student in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. His research interests include high-k dielectrics and metal gate materials for MOS devices, and oxide reliability. Tsu-Jae King (M 91) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA. At Stanford, her research involved the seminal study of polycrystalline silicon germanium films and their applications in metal oxide-semiconductor (MOS) technologies. She joined the Xerox Palo Alto Research Center, Palo Alto, CA, as a Member of Research Staff in 1992 to research and develop polycrystalline silicon thin-film transistor technologies for high-performance display and imaging applications. She joined the faculty of the University of California, Berkeley, in August 1996 where she is currently an Associate Professor of Electrical Engineering and Computer Sciences, and the Faculty Director of the UC Berkeley Microfabrication Laboratory. Her research activities are in sub-100-nm MOS devices and technology, and thin-film materials and devices for integrated microsystems and large-area electronics. She has authored or co-authored over 150 papers and holds five U.S. patents. Chenming Hu (S 71 M 76 SM 83 F 90) received his B.S. degree from the National Taiwan University in 1968 and the M.S. and Ph.D. degrees from the University of California, Berkeley. He is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at UC Berkeley. His research areas include microelectronic devices and technology and device modeling for circuit simulation. He has authored or co-authored five books and over 700 research papers. He is a member of the National Academy of Engineering, a fellow of the Institute of Physics, and an honorary professor of the Chinese Academy of Science, Beijing, and Chiao Tung University, Taiwan. He leads the development of the MOSFET model BSIM, the industry standard model for IC simulation. He received the 1997 Jack A. Morton Award for contributions to MOSFET reliability. He has received UC Berkeley s highest honor for teaching the Distinguished Teaching Award, and the DARPA Most Significant Technological Accomplishment Award for codeveloping the FinFET transistor structure.