1658 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003

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1 1658 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003 Electrical Characterization and Process Control of Cost-Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing Szu-Wei Huang and Jenn-Gwo Hwu, Senior Member, IEEE Abstract A cost-effective technique was introduced to prepare ultrathin aluminum oxide (Al 2 O 3 ) gate dielectrics with equivalent oxide thickness (EOT) down to 14 A.Al 2 O 3 was fabricated by anodic oxidation (anodization) of ultrathin Al films at room temperature in deionized water and then furnace annealed at 650 Cin N 2 ambient. Both dc and dac (dc superimposed with ac) anodization techniques were investigated. Effective dielectric constant of 7 5 and leakage current of 2 3 orders of magnitude lower than SiO 2 are observed. The conduction mechanism in Al 2 O 3 gate stack is shown to be Fowler Nordheim (F N) tunneling. Saturated current behavior in the inversion region of MOS capacitor is observed. It is found that the saturation current is sensitive to interface state capacitance and can be used as an efficient way to evaluate the Al 2 O 3 gate stack/si-substrate interfacial property. An optimal process control for preparing Al 2 O 3 gate dielectrics with minimized interface state capacitance via monitoring the inversion saturation current is demonstrated. Index Terms Al 2 O 3, anodic oxidation, high- gate dielectrics, MOS capacitor. I. INTRODUCTION THE continuous decrease of the thickness of gate oxides used in modern ULSIs has to confront the limit of material itself. As the thickness of SiO is less than 30, direct tunneling effect becomes serious and may result in static power dissipation of devices and erroneous switching in circuits. In addition, device minimization may also reduce the capability of current driving. In order to make a breakthrough on what is aforementioned, it is necessary to increase the physical thickness as well as the dielectric constant of the gate dielectrics. The study of high dielectric constant (high- ) gate dielectrics is thus becoming more and more important, and several high- gate dielectrics and process technologies had been developed [1] [7] for the advanced complementary metal-oxide-semiconductor (CMOS) devices. High- gate dielectrics are generally wanted to be thermally and chemically stable on Si-substrate, and to have high dielectric constant, low Manuscript received November 26, 2002; revised February 21, This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC E The review of this paper was arranged by Editor C.-Y. Lu. The authors are with the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. ( hwu@cc.ee.ntu.edu.tw). Digital Object Identifier /TED leakage current, low thermal budget, large energy band gap, good interfacial quality, long-term reliability, and CMOS-compatible fabrication process. Aluminum oxide Al O is a potential high- gate dielectric material as its heat of formation is 399 Kcal/mol [1], the lifetime operated at low voltage regime is longer than 10 years [1], the dielectric constant excluding interfacial layer (interlayer) ranges from 9 to 10, the energy band gap is about 9 ev, and the interface state density is lower than cm ev at midgap [8] [10]. Al O prepared by atomic layer deposition (ALD) shows a lifetime of 10 years at the low voltage regime but suffers from channel mobility degradation [1]. Highgate dielectrics are generally deposited on the Si surface and usually cause surface damages. The channel mobility is therefore degraded by Coulomb scattering. This disadvantage is overcome by ultrahigh-vacuum reactive atomic-beam deposition which provides better interfacial quality with less than cm ev and comparable channel mobility with SiO gate oxides at high fields [8], [9]. Another process to obtain lower (below cm ev ) is dry oxidation of AlN films [10]. It must be mentioned that the SiO growth will promote the interfacial quality between the high- gate dielectrics and the Si-substrate. The trap level in Al O is reported to be 1.6 ev as examined from the slope of Frenkel Poole plot [10]. For the high- gate dielectrics/si-substrate interface, metal silicate is another concern for device performance. Al silicate formed during low pressure chemical vapor deposition (LPCVD) is investigated to understand the growth kinetics of Al O [11]. Most silicate formation is formed during deposition and the following high temperature annealing. It is found that Al silicate layer is stable with Si and is composed of Al-Si-O bonding unit compounded from Al, Si, and OH radical. The existence of a silicate layer complicates the conduction mechanism and charge trapping behavior in high- gate dielectrics. In Si N SiO stack gate dielectrics, four different tunneling modes had been proposed to identify the most possible current transport mechanism, and it is found that simulation results fit the experimental data well under the postulated one-step direct tunneling model [12]. The primary conduction mechanism in Al O deposited by atomic layer chemical vapor deposition (ALCVD) is verified to be tunneling, and the barrier height associated with Fowler Nordheim (F N) tunneling is about 1.6 ev [13]. Comparing the tunneling mechanism reported /03$ IEEE

2 HUANG AND HWU: COST-EFFECTIVE HIGH- ALUMINUM OXIDE GATE DIELECTRICS 1659 in [10] and [13], the current transport mechanism in Al O is still unclear and seems to be strongly process dependent. On the other hand, charge trapping is worse in high- gate dielectrics because of their imperfect dielectric quality as well as the presence of interlayer. Charge trapping in Al O grown by molecular beam epitaxy (MBE) is explored by examining the effect of annealing on defect passivation. The authors suggest that the absorbed moisture can release hydrogen during post-metallization anneal (PMA) to passivate defects in oxide [14]. It has been proved that Al O can be grown by anodic oxidation (anodization) of Al films in various electrolytes [15], [16]. In this work, room-temperature anodization of ultrathin Al films in D.I. water was demonstrated to be an alternative technique to prepare Al O gate dielectrics on P-Si substrates. The obtained Al O devices exhibit very attractive capacitance-voltage (C V) and current-voltage (I V) characteristics, in comparison with conventional thermal oxides. Current transport mechanism under high field injection is also identified. The saturation current density of an MOS capacitor biased in the inversion region is used to reflect the interfacial property [17] as well as the anodization level of ultrathin Al films. To further understand the interfacial property, we propose an interface state capacitance C model utilizing the low-frequency effect of interface states to evaluate the Al O gate stack/si-substrate interface. The saturation current in the inversion region is sensitive to C and is a very useful parameter to examine the interfacial property. Therefore, it is applied to find the optimization of process control. A reliable charge trapping behavior of Al O gate dielectrics is also demonstrated by using the constant voltage stress (CVS) technique. II. EXPERIMENTS The substrate of MOS capacitors was 3-in, Boron-doped (100) P-type silicon wafer with a resistivity of 1 10 cm. Modified RCA cleaning was carried out first, then % pure Al was thermally evaporated onto the silicon surface with a thickness of by using the tungsten boat at torr and the temperature of wafer was kept at room temperature. In order to suppress the Kirkendall effect, i.e., alloy spiking effect [18], and to eliminate the metallic cluster formed on silicon surface, the evaporation rate was limited to be smaller than 0.1 s. The as-deposited Al film was anodized immediately after evaporation to reduce the natural oxidation in atmosphere. Anodization was proceeded in D.I. water to reduce the possible contamination from electrolyte. Platinum plate was used as the cathode. The anode was also performed by the Platinum plate that carefully contacted with the backside of the wafer without touching the ultrathin Al film to obtain a uniform anodization field. The constant field and time used in dc anodization were V/cm and min, respectively. For dac (dc superimposed with ac) anodization, dc bias was fixed at 25 V and the ac signal with 5 V amplitude and 200 Hz switching frequency was superimposed. The anodization time for dac anodization was 13 min. Postoxidation annealing (POA) was implemented in the furnace at 650 C in 99.99% N for 60 s. Gate electrode was also thermally evaporated using Fig. 1. High-resolution cross-sectional transmission electron microscope picture of Al O gate dielectric MOS capacitor. The lines indicate the interfaces of Al gate/al O, AlO /interlayer, and interlayer/p-si substrate. A 44.4 A gate dielectric with smooth interfaces and uniform thickness is observed % pure Al to make good contact with Al O. The gate area was defined by conventional photolithography and wet etching. Finally, Al with 1% silicon was thermally evaporated on the backside of the wafer which serves as the back contact after the removal of native oxide by buffered oxide etchant (BOE). I V and C V characteristics were measured by an HP4140B pa meter and an HP4284 precision LCR meter, respectively. Equivalent oxide thickness (EOT) was extracted by fitting the C V curves after two-frequency, i.e., 1 M and 100 KHz, correction [19] under the consideration of quantum mechanical effect [20]. The quantum effect in thickness determination of ultrathin SiO is suitable for extracting the EOTs of high- gate dielectrics. It can be proved that the small signal charge centroids at silicon surface are the same for devices with SiO and equivalent thickness high- gate oxides under identical gate bias. All measurements were done at room temperature. III. RESULTS AND DISCUSSIONS High-resolution cross-sectional transmission electron microscope (HRTEM) image of the fabricated MOS structure is shown in Fig. 1. It is observed that the thickness of entire dielectric film is uniform. The thickness of the interlayer (the bottom layer) is almost half of the entire dielectric film, which is consistent with the structure obtained by LPCVD [11]. The compositions of the interlayer are probably composed of Al silicate AlSi O [11] and suboxide SiO [21] resulting from the reaction of Al with Si-substrate during Al evaporation and subsequent POA. The other possible reason for Al silicate formation is the reaction of Al with Si and OH ions [11]. It is well known that high-temperature annealing crystallizes the amorphous metal oxides and increases its dielectric constant, but gives rise to extra SiO growth to decrease the effective dielectric constant. It is reported that the interlayer may introduce charge trapping centers in the dielectric film [22] and cause leakage current due to interface states [23]. For the sample shown in Fig. 1, from its physical thickness of 44.4 and EOT of 23, one can obtain an effective dielectric constant of about 7.5 including the interlayer. The effective dielectric constant is lower than that reported in the literature [1], [9], [10] due to the existence of interlayer, and this can be improved by suitable control of the anodization parameters to reduce the interlayer growth.

3 1660 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003 Fig. 2. C V curves of an Al O sample measured at 1 M and 100 KHz. The result of two-frequency correction is also shown. The C V curve of 23-A thermal oxide is shown for comparison. Fig. 3. Hysteresis of C V behavior with EOT =15and 23 A. The flatband voltage shift of the thicker gate dielectric is 40 mv while the thinner one is negligible. The C V curves used to extract EOT of the Al O film are demonstrated in Fig. 2. The hump of the 100 KHz curve in the depletion region originates from the interface states that provides C connected with oxide capacitance C in series. Therefore, the C V curve after two-frequency extraction is distorted with respect to the thermal oxide. As the oxide thickness is decreased, the portion of charges located at the Al O /interlayer and interlayer/si-substrate interfaces is increased and consequently, leads to an extraordinary deformation (not negative shift) of the C V behavior [22]. The frequency dispersion between 1-M and 100-KHz curves can be attributed to the charge trapping centers existed in the dielectric films that implies an imperfect dielectric quality. Interestingly, the C V curve of Al O does not show positive shift as compared to the thermal oxide. This phenomenon indicates that the negative oxide trapped charge generated by the residual negative ions during anodization [24], [25] did not occur in this work. It may be ascribed to the fact that residual hydrogen-related species after anodic process dissociate into hydrogen during POA to passivate the dangling bonds in the anodic Al O. The hydrogen can also be released from the dielectric film by the following thermal processes such as PMA that passivates oxide defects and interface states further [14]. Fig. 3 represents the hysteresis of Al O gate dielectrics with EOT and 23. The V hysteresis shift of the C V curve with EOT is about 40 mv while that with 15 is almost invariant. The results are similar to that observed by Wang et al. in the ZrO sample which shows that the portion of interlayer in a thicker gate dielectric is closer to the interlayer/si-substrate interface than in the thinner one [22]. Fig. 4 illustrates the gate current density versus gate voltage (J V) curves of Al Al O /interlayer/p-si capacitors with an EOT of 23. The J V curve of SiO sample with the same EOT is also shown for comparison. In the negative bias condition, the gate current is mainly conducted by the electrons injected from the metal gate to the conduction band and consequently increases with increasing gate voltage as shown in Fig. 4. On the other hand, the current level in the negative bias condition shows the normal oxide thickness dependence which increases with decreasing oxide thickness as shown in Fig. 5. Therefore, Fig. 4. J V characteristics of nine Al O gate dielectric MOS capacitors with an EOT of 23 A. The 23-A thermal SiO sample is also shown for comparison. Fig. 5. Leakage current densities of Al O MOS capacitors fabricated by dc and dac anodization with EOTs ranging from 14 to 23 A. the gate leakage current in the negative bias condition will increase with increasing negative gate voltage until the catastrophic oxide breakdown occurs. Reduction of gate leakage current in the accumulation region, i.e., gate injection region, caused by a thicker physical thickness in Al O samples is clearly observed. Although the of Al O Si-substrate interface is higher than that of SiO Si-substrate interface, the gate leakage current can still be suppressed by phonon scattering through the longer tunneling distance. The leakage

4 HUANG AND HWU: COST-EFFECTIVE HIGH- ALUMINUM OXIDE GATE DIELECTRICS 1661 Fig. 6. F N plot of Al O gate dielectric MOS capacitor with EOT =23A. The electrical field is obtained by using physical thickness. The effective electron mass is extracted from the slope of the linear fit. Fig. 7. Current densities biased at +5 V (inversion region) of Al O MOS capacitors as a function of EOT. characteristics of MOS capacitors with gate dielectrics fabricated by dc and dac anodization are shown in Fig. 5. Leakage current of two to three orders lower than SiO is accomplished with EOT ranging from 14 to 23. It is noted that each data point contains at least 10 devices with the same performance as those shown in Fig. 4. DC and dac anodizations show similar tendency in the current level and the normal thickness dependence. Moreover, the dispersion of current densities under the same EOT points out that different anodization levels forms distinct structures of the obtained gate dielectrics. This fact confirms that the gate leakage current depends strongly on the microstructure of the gate dielectric itself. The tunneling mechanism of anodic Al O under high field injection is shown in Fig. 6. The electrical field is calculated by using the physical thickness to explore the exact tunneling mechanism. The measurement was carried out at room temperature while both the Frenkel Poole conduction and the thermal ionic emission may provide the current component [26]. However, a straight fit of the F N plot suggests that F N tunneling is the dominant conduction mechanism in Al O gate dielectric under high field condition. The barrier height between the Fermi level of Al and the conduction band edge of Al O together with the effective electron mass in Al O can be fitted from the slope of F N plot. A barrier height of 1.6 ev according to the report of Zafar et al. [13] was adopted to extrapolate the effective electron mass of, where is the free electron mass. The gate current of P-type MOS capacitor in the inversion region, i.e., substrate injection region, is conducted by minority carrier generation from back contact, interface states, and bulk traps. The current component provided by the minority carrier diffusion from the back contact can be neglected at room temperature while dominate at high temperature [17]. Thus, the gate current is mainly conducted by the minority carrier generation from the interface states and the bulk traps in the depletion layer at room temperature. The amount of interface states should be invariant under deep depletion and therefore contributes a constant component to the gate current. However, the amount of bulk traps increases very slowly with depletion width under deep depletion and results in a very slowly increasing current component. Consequently, the gate current shows a nearly-saturation tendency in log scale after entering the deep depletion region like that shown in Fig. 4. In fact, the interface states and the bulk traps determine the level and slope of J V curve in the inversion region, respectively. For the current saturation mechanism of thermal SiO, Si atom on the surface of the wafer was consumed to grow SiO while the saturation current level increases with oxide thickness under 30 regime [27]. But for the Al O gate dielectrics, the oxidation of the as-deposited Al film consumes sparse Si atoms and therefore produces thinner SiO and fewer bulk traps. This will give rise to a lower saturation current level than SiO as shown in Fig. 4. The nearly-saturation current behavior points out that the Al film can be suitably anodized without damaging the Si surface seriously. Excess anodization may introduce extra SiO growth between Al O and silicon to increase interface and bulk traps. These will enhance the level and slope of saturation current under substrate injection. Fig. 7 shows the correlation between saturation current density under substrate injection and EOTs. For dc anodization, current density varies within one order of magnitude from 14 to 23. This behavior implies that the evaporated Al films with different initial thickness are anodized properly without insufficient or excessive oxidation. For dac anodization, the applied anodization bias switches between 20 and 30 V with an average of 25 V. The ac switching effect is of interest. During the relatively positive period, stronger field further anodizes the Al film just like that in dc anodization. In the relatively negative period, weaker field is insufficient to anodize but goads OH into oxide to passivate the dangling bonds. The interface states are therefore reduced and consequently lower the saturation current level as observed in Fig. 7. Even though the saturation current level is sensitive to substrate doping and/or the thickness of interlayer, it is accurate enough for monitoring the anodization level of Al films. The relationship between saturation current level and C can be examined as follows. In MOS devices, can be used as an indicator of the interfacial property of oxide/si-substrate interface. As a matter of fact, upon reducing the oxide thickness, it is difficult to derive by using the high-low frequency method because of the substantially increased gate leakage current. As a result, the C was extracted instead of for examining the interfacial property. Fig. 8(a) and (b) illustrates the equivalent capacitance models of MOS structure without and with C,

5 1662 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 7, JULY 2003 Fig. 8. Equivalent capacitance models of MOS structure (a) without and (b) with interface state capacitance. respectively. Wherein C represents the oxide capacitance, C is the capacitance of semiconductor considering the quantum mechanical effect [20], and C comes from the interface states. Fig. 9 shows the two-frequency corrected, 1 K and 1 MHz C V curves used to evaluate C. Obviously, the C V curve after twofrequency (1 M and 100 KHz) correction stretches out due to the existence of interface states. The 1 MHz curve without distortion can be explained that much fewer interface states could follow the ac switching signal at such a high frequency. Nevertheless, the 1 KHz curve shows a hump near V without illumination because of the larger C at lower frequency. Thus, the 1-MHz and the 1-KHz C V curves in Fig. 9 can be represented by Fig.8 (a) and (b), respectively. In order to establish a quantitative description of C, we define the capacitance difference at V between 1 MHz and 1 KHz as C. The C can be derived by the following equation: Fig. 9. C V curves measured at 1 M and 1 KHZ for the calculation of C. The two frequency extracted C V curve is shown for contrast. The capacitance difference between the measured 1 M and 1 KHz C V curves is defined as C. where C denotes the theoretical oxide capacitance obtained by EOT, C and C are the gate capacitances measured at V at 1 MHz and 1 KHz, respectively. In other words, C represents C connected with C in series, and C denotes the parallel capacitance of C and C connected with C in series. Based on the low frequency effect of interface states, C calculated from (1) is helpful for reflecting the influence of interface states on C V characteristic. Fig. 10 demonstrates the relationship between C extracted from (1) for the devices with similar EOTs and gate current density under different gate biases. It is observed that the gate current density increases with gate bias at the same C. Since the interface states provide a fixed current component, the increased gate current density can be attributed to the increased bulk traps due to the broadened depletion width when gate bias is increased. But for the device with the largest C, interface states dominate the gate current density and results in a less dependency on bulk traps. For a certain gate bias, the gate current density apparently increases with C which implies that the level of gate current density is strongly dependent on C. Interestingly the gate current density becomes less sensitive to C under higher gate bias. This phenomenon can be explained by the fact that the current component generated by more bulk traps in the wider depletion region screens the current component generated by interface states. Nevertheless, the gate current (1) Fig. 10. Gate current density biased at the substrate injection region versus interface state capacitance. The gate current density shows a strong dependence on interface state capacitance. Fig. 11. biases. Gate current density versus anodization time with different gate density is linked with interface states and can be used to monitor the interfacial property of high- gate dielectrics/si-substrate interface. Fig. 11 shows the gate current density versus anodization time measured at various gate biasing voltages. The optimal process condition can be found at min which is in accordance with the lower gate current density with an EOT of 14. The curves in Fig. 11 show similar variations regardless of excess or insufficient anodization. This phenomenon indicates that saturation current level is indeed useful to examine the interfacial properties.

6 HUANG AND HWU: COST-EFFECTIVE HIGH- ALUMINUM OXIDE GATE DIELECTRICS 1663 Fig. 14. C V curves before and after electrical stress of 07.7 MV/cm. The flat-band voltage shift is 63 mv. Fig. 12. (a) EOT. (b) Gate injection current density. (c) Interface state capacitance versus anodization time of Al O gate dielectrics. Finally, charge trapping characteristic of Al O gate dielectric is investigated by constant voltage stress as shown in Fig. 13. The stressed gate voltage is 3.4 V that leads to a stress field of 7.7 MV/cm by using the physical thickness. The gate current is slightly decreased under constant field stress which indicates electron trapping as identified by the C V curves shown in Fig. 14 with a flat-band voltage shift of 63 mv. The electron trapping in Al O are probably resulted from the neutral trap centers created by the bonds breaking by mobile [28]. The charge trapping under constant voltage stress is not obvious in the anodic Al O gate dielectric. Fig. 13. Gate current fluctuation versus stress time for an Al O sample stressed by a constant voltage of 03.4 V. The stress field is calculated from physical thickness. Fig. 12(a) (c) demonstrates the EOT, the gate leakage current under gate injection, and C versus anodization time, respectively. It can be found that the optimal process condition is around 5.0 min. For an anodization time less than 5.0 min, the incompletely oxidized Al would spike into and react with the Si-substrate during the high temperature annealing (650 C). This may result in the silicate formation to spoil the interfacial property and lower the permittivity of the gate dielectric. A longer anodization time within 5.0 min will introduce more complete anodization of ultrathin Al film such that the C decreases with anodization time. For an anodization time longer than 5.0 minutes, excessive anodization may consume more Si atoms to grow thicker SiO. Consequently, more traps at the SiO Si-substrate interface will be created [27] and the C is therefore increased with the anodization time. The turn around points with the lowest EOT,, and C in Fig. 12 indicate the optimal oxidation time for minimum surface damage. Therefore, the results from Fig. 12 imply that the process condition can be well controlled to acquire the desired oxide and interface properties by adjusting the parameters of anodization. IV. CONCLUSION Room-temperature anodization for preparing high- gate dielectrics is proposed in this work. Both dc and dac anodization are implemented to produce ultrathin gate dielectrics. Al O with an effective dielectric constant including interlayer of and a leakage current with three orders of magnitude smaller than SiO under EOT are achieved. The dielectric stack is composed of Al O and interlayer with almost equal thickness. The distortion and hysteresis of C V curves with respect to SiO are not obvious. The tunneling mechanism in Al O is dominated by F-N tunneling with an effective electron mass of O. Substrate injection gate current density under deep depletion of MOS structure is adopted to monitor the anodization level and interface property. The saturation current behavior indicates that Al film can be properly anodized on P-Si. The proposed capacitance model well explains the relationship between saturation current density and C. The model also proves that the current level biased in the inversion region is controlled by the interface state density. The process control can be achieved by monitoring the saturation current density. From the constant voltage stress, charge trapping in Al O is not significant at a field of 7.7 MV/cm. It is believed that the application of the method proposed in this paper to new materials is possible and is worth studying. REFERENCES [1] J. H. Lee, K. Koh, N. I. Lee, M. H. Cho, Y. K. Kim, J. S. Jeon, K. H. Cho, H. S. Shin, M. H. Kim, K. Fugihara, H. K. Kang, and J. T. Moon, Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD- Al O gate dielectric, in IEDM Tech. Dig., 2000, pp

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Houssa, A. Stesmans, M. Naili, and M. M. Heyns, Charge trapping in very thin high-permittivity gate dielectric layers, Appl. Phys. Lett., vol. 77, pp , Aug [29] X. Guo, X. Wang, Z. Luo, T. P. Ma, and T. Tamagawa, High quality ultra-thin (1.5 nm) TiO =Si N gate dielectric for deep sub-micron CMOS technology, in IEDM Tech. Dig., 1999, pp Szu-Wei Huang was born in Taiwan, R.O.C., in He received the B.S. degree in electronic engineering from Feng-Chia University, Taichung, Taiwan, in He is currently pursuing the Ph.D. degree in graduate institute of electronics engineering at National Taiwan University, Taipei, Taiwan. Currently, his research interests focus on the MOS devices and high-k gate dielectrics. Jenn-Gwo Hwu (SM 99) was born in Taiwan, R.O.C., on August 29, He received the B.S. degree in electronic engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1977 and the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), Taipei, in 1979 and 1985, respectively. Presently, he is a Professor with the Department of Electrical Engineering, NTU. He joined the faculty of NTU in His research work is mainly on the preparation of reliable ultrathin gate oxide and the related MOS devices. He has experience in teaching the courses of circuits, electronics, solid-state electronics, semiconductor engineering, MOS capacitor devices, radiation effects on MOS system, and special topic on oxide reliability. Prof. Hwu was a recipient of the 1986, 1998, 1999, and 2001 Excellent Teaching Award sponsored by NTU. In 1988, 1989, 1990, 1991, and 1993, he was a recipient of the Excellent Teaching Award sponsored by the College of Engineering, NTU. In 1991, he was also a recipient of the Outstanding Teaching Award sponsored by the Ministry of Education, R.O.C.