SoC Signal Integrity and Power Delivery Design Challenges and Solutions. Charlie Chen. Charlie Chen

Transcription

1 SoC Signal Integrity and Power Delivery Design Challenges and Solutions

2 Outline Motivation Signal Integrity Issues and Solutions Parasitics Estimation Coupling Noise Estimation Noise Filtering and Optimization Power Delivery Issues and Solutions IR, Ldi/dt, and Resonance issues Solutions Conclusion

3 Rambus memory technology delayed By Michael Kanellos Staff Writer, CNET News.com February 23, 1999, 6:10 p.m. PT PALM SPRINGS, California--Computers using the Rambus memory standard and the latest version of Intel's Accelerated Graphics Port have been delayed until late in the third quarter, By Intel Stephen said today, Shankland a delay that will temporarily slow down parts of the Intel world. Staff Writer, CNET News.com September 24, 1999, 12:45 p.m. PT Intel to delay new chipset as Rambus reels update Intel has canceled a planned Monday unveiling of a new chipset that would have enabled the first use of next-generation Rambus memory in PCs, computer makers say. Samsung halts production of Rambus memory chips "The Intel 820 launch will not happen Monday," said Jon Weisblatt, a spokesman for Dell Computer. The 820 "Camino" chipset By Michael is a package Kanellos of chips necessary to use Rambus memory. Staff Writer, CNET News.com September 30, 1999, 6:05 p.m. PT "Dell engineers have determined that the 820 platform is not production-quality ready," Weisblatt said. Now that PCs using Rambus memory are delayed, Samsung has halted production of the new type of memory chips until the recent problems are solved. Samsung, which has made more Rambus memory chips than anyone else to date, said that the suspension of manufacturing is a direct result of Intel's decision earlier this week to delay the release of its 820 chipset, the part that will allow Pentium III processors to "speak" to the next-generation memory. The problems occur when all three of the memory slots on a Rambus motherboard are filled

4 Bluetooth must chew through pricing, tech constraints By Stephanie Miles Staff Writer, CNET News.com January 21, 2000, 4:50 a.m. PT Bluetooth, By David Lammers the EE Times much-hyped (05/10/00, 5:45 wireless p.m. EST) technology developed to do away with awkward cables and cumbersome wires, must overcome serious obstacles before it can become widely used, according to a new study... Intel recalls boards with memory translator chip SANTA CLARA, Calif. Intel Corp.'s long-suffering effort to establish a market for the Rambus memory architecture took another unexpected turn on Wednesday (May 10), when Intel announced that it would replace motherboards that have a defective memory translator hub (MTH). "It has to be reduced to a single chip, and it has to be sold for under $10." The MTH, however, has caused system noise issues that, according to a statement from Intel, "can cause some systems to intermittently reset, reboot, and/or hang. In addition, the noise issues, under extreme conditions, potentially can cause data corruption."

5 Source:Intel Journal

6

7 IEDM 0.13 um Interconnect Delay M1-M5

8 IEDM Micron, 6 Layer Technology M6 M5 M4 M3 M2 M1

9 Source:Intel Journal Noises Category

10 Measurement Indut+Cap Noises

11 Source:Intel Journal Technology vs. Coupling Cap

12 Source:Intel Journal (Noise-induced) Timing Induced Noises

13 Motivation Crosstalk also creates timing uncertainty Accurate Modeling is necessary Source:Celestry

14 Noise-aware Timing Analysis Start from the minimum window and then iteratively enlarge it Start from the maximum window and then iteratively shrink it Source:Jacon Cong

15 Noises Analysis: Metrics Rule of Thumb: Cx/Ctotal < 18% Devgan s model [ICCAD 97] Elegant, Elmore-like formula for peak noise Assume infinite ramp => too pessimistic estimation, esp. when aggressor slew is small => noise could even be larger than Vdd! Charge-sharing based (e.g., [Vittal & Marek-Sodawska, TCAD 97], [Nakagawa+, HPJ 98]) Cannot differ near-source versus near-sink coupling 2-PI Modeling [D. Pan 01] reduce the coupling model to a two PI model Ignore the distributed effect Hierarchical moments calculation and its applications to repeater insertion [ 01] Accurate, take distributed coupling effect into consideration harder to implement Source:Jacon Cong

16 Crosstalk Noises Model Aggressor net C x Victim net Ls Lc Le Cl tr Rd Rs Cx Re Cs1 Cs2 Ce1 Ce2 Cl

17 Source:Intel Journal Noise Timing Filtering & Frequency

18 Noises Reduction Repeater Insertion Repeater is one of the most effective and widely-used noise killer Not only filter out noises but also reduce inductance loops Shielding Shielding significantly reduced the x-cap and X-induct noises Spacing and net reordering Spacing is effective for Xcap-noise reduction Sizing Upsizing driver, repeaters, and interconnects for X-cap noise reduction, Downsizing for X-induct reduction Net-reordering Reorder the net to separate noise mutual-sensitive nets

19 Source: Locality effects of Capacitance

20 X-Cap/Ctotal for 0.13um Tech 1 Ccouple/Ctotal Ratio Vs. Spacing M6 Ccouple/Ctotal Ratio M5 M4 M3 0.7 M M SPACING S (um)

21 Source:Intel Journal Repeater: The noise killer

22 Noise Reduction

23 Source:Intel Journal Repeater Bay Idea

24 Repeater Insertion Sink 1 is critical, where to insert repeater? B A C Depends on Loads at receivers 1, 2 and 3 Required arrival times and slopes Polarity of the signals at the receivers 1 2 3

25 Repeater Insertion Insert repeaters An RLC tree Library of buffers Repeater insertion points C B A

26 Dynamic Programming Framework Back propagation the net Enumerate all the possible solutions in every node Prune out sub-optimal solution t 0 t 1 B A t 2 t 3 t 4

27 Hierarchical Delay Computation Transfer function can be computed hierarchically [charlie chen] A H AB (s) B Y 2 (s) H BC (s) C C H AC (s) = H AB (s) H BC (s)

28 Hierarchical Transfer Function Computation Transfer function can be computed using simple voltage-dividence rule V 1 (s) Y 1 (s) V 2 (s) Y 2 (s) V 2 (s) = V 1 (s) H 12 (s) Y 1 (s) Y 1 (s)+ Y 2 (s)

29 Frequency Dependent Effects Skin Effect Impedence R Proximity Effect L f Loop Inductance Impedence jωl Return Paths R 1 / jωc f

30 Skin Effects Skin Depth δ = 1 πfµσ Cu Al um I 1 / e f

31 Retarded Effect Retarded Copuling 150 ps 1 inch Light speed: 3x10 8 m/sec= 300 um/ps For dielectic constant=3.8, around 150 um/ps It takes light more than 150ps to traverse 1 inch on VLSI What about Package, PCB?

32 Frequency Dependent Effects Inductance Resistance Inductance, Henry 3.5E E E E C 25 C 100 C Resistance, Ohm C 25 C 100 C Frequency, MHz Frequency, MHz Source:Jacob White

33 Transmission Line? Not Applicable Return Path Transmission line assumes Return path is known Uniform current distribution No coupling

34 Where are the return paths?

35 Interconnect Explore SPICE-Compatible PEEC RLC extraction

36 Capacitance Extraction Methods Formulae based Use simple analytical formulae to capture the dominate capacitance Library based Pre-characterization of various geometries 2.5D Divide the 3D extraction into successive 2D extraction problem 3D Field solver based Utilize Q=CV, use the charge distributions to find out the capacitance values Random work algorithms

37 3D Capacitance Extraction l i q i From Q C i, j = Q j = Cv = 2 n= 1 q j, n + - a i a i l j r l k q j a k q k

38 Method of Moments: Capacitance Matrix inversion is n 3 Φ( r) = Φ = n i= 1 1 4πε P q ij i S ' ρ( r') ds' r r' If there are n charg es:q i + - a i a i l i q i l j r Pi P P P i,1,1 i,2 1,1 j,1 1,1 j,2 1,1 P P i,1 i,2 i,2 1,2 j,1 1,2 j,2 1,2 P P P P P P i,1 j,1 i,2 j,1 j,1 j,1 j,2 j,1 P P P P i,1 j,2 i,2 j,2 j,1 j,2 j,2 j,2 q q q q i,1 i,2 j,1 j,2 i' i' j' j' = q j

39 Interconnect Explore: l t d w An Integrated Hierarchical Inductance and Capacitance Extraction based on PEEC Simultaneous 3-D capacitance and partial inductance extraction Valid for wide range of frequency; can capture frequency-dependent effects such as return paths, skin and proximity effects Significantly improve the efficiency and accuracy over hierarchical and multipole methods Target: Full-chip level power delivery and clock net extraction

40 Hierarchical & Multipole Speed-up Hierarchical refinement and Multipole Expansion Dynamic adaptive mesh: On the fly-discretization (only when necessary) Far field interaction Near field interaction

41 Bags of Tricks Efficient Preconditioned CG and GMRES to solve large scale dense matrix No matrix inversion Iterative improving the solution: speed up over 100X than Gaussian elimination Fast converge (when matrix is not ill conditioned) Windowing Extract only near by capacitance to reduce complexity

42 Runtime of Interconnect Explore

43 Memory Requirement of Interconnect Explore

44 Inductance Modeling Issues Loop inductance is hard to find (except for ideal cases) due to return paths issues Partial Element Equivalent Circuits (Ruehli 1972) FastHenry: Use RL to find the effective loop inductance Too many small coupling terms Kill the performance of sparse matrix based solver Randomly throw out smaller terms will causes nonpassive circuit

45 PEEC (Partial Equivalent Element Circuit) l t d w Given geometry, PEEC generate SPICE-compatible partial inductance (instead of loop inductance) and capacitance Valid through a wide range of frequency. [Ruehli]

46 Partial Inductance Extraction for Parallel Equal-length l s l s s l s l m l ph M k t w l m l ph L Grover mutual self ln ) ~ 0.2 ( ) ( ln ) ~ 0.2 ( ) ( : µ µ l l w s t m in all l t w s when s l l ph M t w l l ph L l s mutual self µ, ), (,, 1 2 ln ~ 0.2 ) (, ln ~ 0.2 ) ( <<

47 Partial Inductance Extraction for Skewed Parallel-Case 1 is indepent of 0, 0 )) ( ) ~ 0.5(( ) ( 0, )) ( ~ 0.5(( ) (, 0 )) ( ) ~ 0.5(( ) (, 0 s M d or when s M M M M ph M d m M M M ph M d M M M M ph M d ij d m d l d d m l ij m l m l ij d m d l d d m l ij > = + + < < + = + + > l m d s

48 Partial Inductance Extraction for Skewed Parallel-Case 2 l d s m e de <> 0, M ij ( ph ) ~ 0.5(( M m+ d + M m+ e ) ( M d + M e )) de = 0, M ij ( ph ) ~ 0.5(( M l + M m ) M l m )

49 Log(x) Values X in log scale X in linear scale

50 Long Range Inductance Effects and L -1 M7 M5 L Matrix (far/near=16%) (Unit:pH/10um) M7: M5: L -1 Matrix (far/near=0.8%) (Diagonal Dominate) (Can delete smaller terms and passive) M7: M5:

51 Idea: Use L -1 instead of L Since L -1 is not only positive definite but also diagonal dominate. Throw out off-diagonal terms will remain positive definite & diagonal dominance. [Devgan] The smaller terms decrease dramatically, so the accuracy may not be affected too much. Diagonal dominance is also a way to see whether your inductance formulae is accurate Cross-layer inductance (coupling, return paths) should be considered

52 Loop Inductance definition L P2,2 L P5,5 L P3,3 S1 S2 L P4,4 L P1,1 L P6,6 3 3 L = M s 1 i i= 1 j= 1, j 6 6 L s 2 = M i i= 4 j= 4, j M s = M 1, s2 3 6 i= 1 j= 4 i, j

53 Loop Inductance Examples L loop = L 1,1 t S G t L 2,2 ~ 0.2 l(ln( (t l w 1 ~ 0.2 l(2ln t 1 s M + s + w 1,2 w 1 2 s )(t + w 2 M 2 3), + 2,1 w 2 when Sign Rule: Same Direction (+) Inverse Direction (-) ) + ) let l = 1000, s = 1.2, t + w = 1.8, then, loop ind Accurate = 459 ph, less than 5% error t 1 3) = t 2, w = 1 = w 2 438pH

54 Observation Partial Self and Mutual Inductance are not scaleable However, Loop inductance is scaleable!! To minimize loop inductance, design a near wide return path to maximize the mutual inductance Repeater Insertion is still one of the most effective way to reduce inductance noises

55 Loop Inductance Examples 3 l 1 2 G S G t 2 L loop Net = ~ compare ~ L L L Assume equal return current. 1,1 1,1 1,1 to + L ~ 0.5* L + 0.5* L + 0.5* L 2,2 Difference 2,2 : 2,2 2,2 2M 1,2 0.5M M 2,3 1,3 2M 0.5M 1,2 3, M 0.5M 2,3 1, M 2,3 s ~ 0.1l ln w t + NewL 329 ph,109ph reduction!! loop =

56 Mutual Loop Inductance Example 1 2 l 3 S1 d 1 d 2 S2 G t 2 M d 3 Assume all return current goes through ground loop s1, s2 = M1,2 M1,3 M 3,2 + L3,3 ~ 0.2lln d 1 d 2d ( w + t) To minimize the mutual inductance: increase d 1, w+t, reduce d 2 and d 3

57 Inductance Filtering t r Z drv Rl Ll + - Cl CL 2 l < R 2πfLl L C ( Rl + Z > 2 ~ 4 drv ), where f = 0.34 / t r [Shen Lin]

58 Inductive vs. Capacitive Coupling Noises 1000um M7 40fF gcap G V V Without inductance V s V V V G With inductance

59 Ground Return Paths M7 G G G G s G G G G 90% return through the next ground line!!

60 Ground Return Paths (40 Z drv, 40fF ground Cap) M7 G V V V s V V V G Without gcap, Far side return With gcap, Far side return

61 Outline Motivation Signal Integrity Issues and Solutions Parasitics Estimation Coupling Noise Estimation Noise Filtering Power Delivery Issues and Solutions IR, Ldi/dt, and Resonance issues Conclusion

62 Power Consumption P C V 2 f, where C = Capacitance ~ Area V = Supply Voltage f = Operation Frequency

63 Motivation: Power fluctuation sources increase significantly T IR-drop: V = I x R = (P /Vdd ) x R T L di/dt: V = L di/dt roughly proportional to L(I x f) = L (P x f / Vdd ) I : consuming current f : clock frequency P : power dissipation Vdd : supply voltage T Other noises such as resonance and electromigration also affect power grid reliability Power delivery quality becomes a critical issue

64 Power Delivery Problem (not just California) Source: Shekhar Borkar, Intel

65 Power Density & Supply Current Trend

66 Packaging Advancements: Organic, C4 Bump, Pin side Decap

67 Standby Power Trend

68 0.18 um Leakage Current I DS (A/ m) 1E-02 1E-04 1E-06 1E-08 V DS = 1.5V V DS = 0.05V 1E-10 1E-12 PMOS L G = 150 nm NMOS L G = 130 nm V GS (V)

69 Dual Vt Technology

70 Power Delivery Issues Power fluctuation sources IR Drop: Maximum instant current consumption L di/dt Drop: Maximum instant differential current consumption Mutual Disturbance: RF-digital disturbs each other Substrate noise issues emerging Resonance fluctuation Design difficulties Accurate modeling: involved 3-D Maxwell equation solving SPICE Simulation: large scale dense matrix simulation due to inductive coupling (how far) Current envelope estimation problem:how much and when De-coupling Capacitance: Need systematic modeling and estimation for its impact on power fluctuation Design Modeling: return path issues

71 Simultaneous Switching Noise (Power Dip/Ground Bounce) IR+Ldi Ldi/dtdt

72 [Shen lin] di/dt and LC Resonance

73 C4 bump and Power Grid Design

74 Capacitance Return Path GND Vdd

75 Long return paths GND Vd d

76 Return path Gap

77 Quasi-3D Parallel Return Path Simplification Previous study show that almost all return current Go back from the parallel (multi-layer) shields and calculate the effective loop inductance for each wire

78 Design for Return Path Power Ground Power For Pentium IV, every 5 signals will have a return path at top mental layers

79 Utilize Mutual Inductance l i V M 12 1,2 = I R + L jωi + M jωi 1 1,1 1 1,2 negative Voltage drop reduced 2 l j r

80 Micro-architecture Change to Reduce L di/dt The relationship of FPU states Conventional Design Inactive state Active state Recent Work Inactive state Active state Step Power Our Idea on N-cycle Inst. Prediction Inactive Active state Subactive state state Ramping time Busy time Busy time [Shen lin]

81 Power Dip Impact Delay C=0.05p C=0.5p No decoupling capacitor Input C=5p C=50p Ideal power supply

82 Decap Reduces Power Noises C=0.05 p C=0.5p C=5p No decoupling capacitor C=50p Ideal power supply

83 Decoupling Capacitance!!! Damping factor is frequency dependent Depends on the position as well (R, C) How much is enough? Capacitance Module1 I Module3 I VDD Module2 I Module4 I GND

84 The Effect of C to Reduction Ratio Larger C is better. In the middle region, decoupling capacitance helps efficiency. R1 R2 VDD ± C Module I

85 Intrinsic De-coupling Capacitance Modeling Estimation based on a typical inverter, Chaudhry, et. al. VLSI India 2000 Decoupling capacitance of a typical inverter 1 ( C gdp + C gdn ) + ( C gsp + C gdn ) *(1 2 SF ) Scale it up for all the devices in a block/chip Difficulty with this model Series R is difficult to be considered Does not scale linearly with total size due to complex gate and circuit topologies [Shen lin]

86 Frequency Domain Analysis R1 R2 VDD ± C Module I After Fourier transformation, any signal can be decomposed into the summation of sinusoidal functions We can assume the sinusoidal current waveform and find the damping factors for specific frequency By superposition theorem, the voltage drop is summation of the response of each sinusoidal current source

87 Reduced Model R1 R2 VDD ± C Module I θ = cos -1 φ = cos ω C ω C R1 (R1// R2) 2 2 V = I ( R1+R2) IR Drop ω C 1+ ω ( R1// R2) 2 C 2 R1 2 2 Damping Factor ( θ - φ)

88 The Effect of R2 to Damping Factor Cω = Cω = 1 10 Cω = Cω = 1 Fixed (R1+R2) Smaller R2 is better. This means when the distances between module and power pin are the same, closer capacitor is better. R1 R2 VDD ± C Module I

89 Decap Simulation Results C1355 from ISCA85 benchmark Simulated by HSPICE About 25 gates per row Increase size of gates and width of transistors 50 time (Practical layout reach 1,000 gates per row) Metal Resistance 0.7Ω/ Decap 30fF/µm 2

90 Layout To P/G Supply Standard Cell To P/G Supply To P/G Supply Vdd GND To P/G Supply

91 Floorplanning without Decap Insertion

92 Floorplanning with Decap Insertion Aside

93 Floorplanning with Decap Insertion Inside

94 Simulation Results Decap inside Decap in Both Sides No Decap (a) Decap inside Decap in Both Sides No Decap (b)

95 Simulation Results Maximum Delay Improvement Area Overhead Without Decap ns - - Decap Beside ns 2.26% 10.67% Decap Inside ns 10.73% 12.63%

96 Efficient Power Delivery Analysis

97 Power Delivery Analysis Issues: Size Does Matter Power fluctuation sources IR Drop: Maximum instant current consumption L di/dt Drop: Maximum instant differential current consumption Mutual Disturbance: RF-digital disturbs each other Analysis Difficulties Fill-ins: Grid structure and mutual coupling s will introduce a lot of fill-ins -> Kill the performance of most sparse matrix based simulators Design Modeling: inductance and return path issues Block current modeling: millions of devices

98 Power Grid Analysis Challenges More than 40-million transistors on a chip Sparse direct method takes super linear time to solve a matrix. Introduce large amount of fill-ins Slow and huge memory requirement SPICE3 takes 6 hours to finish DC analysis for an 80,000-node circuit How about more than millions? Iterative Methods are promising!!

99 Efficient Analysis Methods Hierarchical Analysis and sparsification Partition into smaller blocks to speed analysis [David] Generate compact model for high level analysis Nonliner-Linear Iteration [simplex, David] Decouple gate simulation from power grid simulation Multigrid [Sani Nasif] Use less denser (but wider) grid to capture the dominate effect Develop sparsficiation algorithm to deal with non-regular grid Iterative Methods [] Reduce fillins and tradeoff runtime, accuracy, and memory

100 Efficient Analysis Techniques Hierarchical analysis (David and ) global nodes global grid ports Internal nodes ports Internal nodes ports Internal nodes local grid I = AV+S P/G network and devices are considered separately [Shen lin]

101 MultiGrid Techniques Model Reduction for ASIC block [Shen lin]

102 Hierarchical Analysis

103 Direct and Iterative Methods for Ax=b problem Sparse Direct Methods LU factorization Large amount of fill-ins cause it slow and huge memory requirement Forward- and backward- substitutions Iterative Methods Only matrix multiplications No fill-in Excellent for dense matrix Convergence ratio depends on matrix condition # Forward Euler Methods No matrix solving, only substitutions Linear time Time-Step limited by the stability limit

104 Iterative Methods Classifications Stationary methods: Jacobi, gauss-seidel, SOR, SSOR Nonstationary methods: CG, MINRES, GMRES, CGNE General Minimum RESidual (GMRES) Suitable for solving non-symmetric matrices Has to store and orthonormalize with many previous search directions (slower and more memory required) Less # of iterations Conjugate Gradient (CG) Only has to store and orthonormalize with the last search direction (faster and fewer memory required) Symmetric positive definiteness (s.p.d.) required Converging rate depends on the condition number

105 Conjugate Gradient Methods A popular iterative method to solve large scale dense matrix Instead of inverting matrix, it keep guess new values to minimize the residue: r=ax-b Finite Convergence for symmetric positive definite matrix, maximum n steps Closed related to Krylov Subspace Methods Convergence is depend on the condition number λ max / λ min

106 Preconditioning How to improve condition number? The matrix with the best condition number (which is 1) is the identity matrix (CG converge in one iteration) If we multiply both size of the equation with A -1, then we can solve the equation in one iteration Ax M = b Ax = M 1 1 However, the whole idea is to avoid finding A -1 Instead, we multiply a matrix which is closed to A -1 The question is how? b

107 WPCG (Wisconsin Preconditioned Conjugate Gradient) Use Cholesky Decomposition instead of LU (save 50% runtime) Incomplete version: A=GG T +E, where E is the error of this approximation If E is small enough, then we can anticipate G -1 G -T A ~ I How to find good G: perform Cholesky Decomposition while ignoring some small terms to reduce fillins Use Conjugate gradient method to avoid orthonormalize previous vectors More than 100X faster than SPICE with less than 0.1% of error Immediately available!

108 WPCG IR-Drop Analysis Runtime Comparison

109 Fill-ins Comparison

110 Fast Linear Circuit Simulation by Transmission-Line Modeling Method

111 Promising Method: TLM-ADI Method

112 Runtime Comparison

113 Reference Hierarchical analysis of power distribution networks, Min Zhao, Rajendran V. Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry and David Blaauw Pages Al Ruehli, Inductance Calculations in a Complex Integrated Circuit Environment, IBM J. Research and Development, A. Deutsch, H. Smith, et al, When are Transmission-Line Effects Important for On-chip Interconnects? IEEE Trans. Microwave Theory Tech., 1997., Yehea Ismail, Eby Friedman, et al, figures of Merit to Characterize the Importance of On-chip inductance, Proc. 35 th Design Automation Conference, 1998., C.K Chang, John Lillis, Shen Lin, and N. Chang, Interconnect Analysis and Synthesis,, Yu-Min Lee, Charlie Chung-Ping Chen, "Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method," IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2001 Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee and Charlie Chung-Ping Chen, "Linear Time Hierarchical Capacitance Extraction Without Multipole Expansion," International Conference on Computer Design Tsung-Hao Chen, Charlie Chung-Ping Chen, "Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods", in the IEEE/ACM Design Automation Conference (DAC), 2001 [Jun at Las Vegas, Nevada].

114 Thank you