ABSTRACT. MORGENSEN, MICHAEL P. High-Frequency FET Modeling in GaN with Dispersion Effects. (Under the direction of Professor D. W. Barlage).

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1 ABSTRACT MORGENSEN, MICHAEL P. High-Frequency FET Modeling in GaN with Dispersion Effects. (Under the direction of Professor D. W. Barlage). Techniques used to model a field-effect transistor s equivalent circuit parameters are investigated and applied to an on-wafer AlGaN/GaN HFET using high-frequency S-parameters. Analysis of a THRU line allowed substrate permittivity characterization, improving parasitic capacitance estimation. Drain-source output admittance dispersion was observed in the measured devices. This dispersion phenomena was attributed to parallel conduction and was primarily present for low drainsource bias. Dispersion complicated parameter calculation and required modification of commonly used model extraction techniques. Effective mobility was also estimated by only using information contained in the S-parameter measurements. Small-signal parameter temperature dependence was also investigated to determine each parameter s associated temperature coefficient.

2 High-Frequency FET Modeling in GaN with Dispersion Effects by Michael Morgensen A thesis submitted to the Graduate Faculty of North Carolina State University in partial fullfillment of the requirements for the Degree of Master of Science Electrical Engineering Raleigh, North Carolina 2008 APPROVED BY: Dr. Mark Johnson Dr. Kevin Gard Dr. Douglas Barlage Chair of Advisory Committee

3 ii BIOGRAPHY Michael Morgensen was born in High Point, North Carolina to Thomas and Jean Morgensen. He entered North Carolina State University as an undergraduate in the fall of 2001 and graduated with a B.S. in Electrical Engineering. He continued his studies by enrolling in the Ph.D. program at NCSU beginning in the fall of 2005 where he continues to perform research in the area of device characterization. He has greatly benefitted from internships at Marvell Semiconductor in 2004, 2006 and RF Micro Devices in 2007.

4 iii ACKNOWLEDGMENTS I would first like to acknowledge and thank Dr. Barlage for giving me the opportunity to attend graduate school and for his continued encouragement. My cousin, Benjamin Niu, is also owed much thanks for his role as a mentor. Others that deserve special mention include Dr. Johnson and Dr. Gard, whose time taken to serve on my committee is very much appreciated. Also, my current and former research group members Dr. Lei Ma, Merve Ozbek, Jaehoon Park and Matt Veety are thanked for all their hard work and help.

5 iv TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES vi vii 1 Introduction Background Overview of work Substrate permittivity Matched lossless transmission line Transmission line loss Unmatched transmission line Permittivity results Correlation coefficient Error analysis for α Parasitics Simplifications Overview of capacitance methods EM simulation Reverse cold-fet Parasitic capacitance results Overview of series resistance methods DC technique for MESFET s Forward cold-fet Non-ideal cold-fet modeling Series resistance results Bias-independent analysis Bias-dependent series resistances Summary Dispersion g m dispersion Output admittance dispersion High-frequency considerations Trapping Intrinsic element extraction De-embedding Intrinsic extraction Y DS Y gm Y GS and Y GD

6 v Choosing the appropriate model Results DC and RF comparison f T, f max Definition of model error Optimization Effective mobility Basic derivation Universal mobility curves Comparison with existing methods Extraction with S-parameters Fringing capacitance and channel length Results Parameter temperature dependence Parameter results Threshold shift Temperature-dependent mobility System calibration temperature considerations Conclusion Bibliography Appendices A Y, Z, and S-parameters A.1 Z-parameters A.2 Y-parameters A.3 S-parameters A.3.1 Relation to power A.3.2 Generalized S-parameters B Calibration B.1 Probe Calibration C Matlab scripts C.1 Non-linear least-squares fit for dispersion data C.1.1 dispersion function.m

7 vi LIST OF TABLES Table 2.1 Measured and corrected permittivity Table 2.2 Theoretical and corrected permittivity Table 3.1 Parasitic capacitance values Table 3.2 Summary of series resistance results Table 4.1 Transconductance models

8 vii LIST OF FIGURES Figure 2.1 THRU structure used for obtaining ε e. Distance between probe marks is 150 um.. 4 Figure 2.2 Mismatched THRU line. Under S 21 conditions reflections occur Figure 2.3 The bottom circuit represents the measured behavior Figure 2.4 Simulation results showing difference in measured phase and magnitude as interpreted directly from S 21 of each structure Figure 2.5 Phase and loss information from measured S 21 and with correction; Z 0 = 72 Ohms. 12 Figure 3.1 The two sources of parasitics for a 2-finger FET Figure 3.2 A complete small-signal model. The dotted box encloses the intrinsic FET circuit. 16 Figure 3.3 photo of 0.7um x 80um T-gate FET and drawn structure in Momentum Figure 3.4 Simplified parasitic capacitances are between metals in absence of a lower ground plane Figure 3.5 Low-frequency small-signal model for a fully depleted FET with V ds = Figure 3.6 Alternate small-signal model for a fully depleted FET with finger and pad capacitances combined (V ds = 0) Figure 3.7 Cold-FET capacitances, V ds = Figure 3.8 Forward-biased MESFET-like structure (a = α) Figure 3.9 Simplifications for a forward-biased gate Figure 3.10 Heavily forward-biased FET with V ds = 0. Typical α = Figure 3.11 Simplified equivalent circuit after parasitic capacitance de-embedding Figure 3.12 Simplified equivalent circuit for Z 22 calculation Figure 3.13 Solid line, extrinsic Z-parameters; dashed line, parasitic capacitances removed. Resistances are estimated at the greatest frequency and forward bias applied in the classical forward cold-fet technique (in this V gs = 3V) Figure 3.14 Estimates for g ds and C 22 from α

9 viii Figure 3.15 Solid line: correction using parameter A; dashed line: from Z-parameters with parasitic capacitances removed. The method involving A was not useful for V gs < 6V, which was likely due to a failure of the assumed small-signal model to accurately describe the channel conditions Figure 4.1 Cross-section of the HFET analyzed in this work Figure 4.2 Output admittance dispersion and g m dispersion due to additional VCCS g m,rf Figure 4.3 Forms of Y gm assuming different models using an identical cutoff frequency of 2 GHz Figure 4.4 Dispersion as described by equation 4.7. g ds = 2 ms, C ds = 25 ff, R RF = 100 Ohms, C RF = 200 ff Figure 4.5 Theoretical behavior of α; with dispersion, fitting α in the linear region will overestimate g ds by approximately 1/R RF Figure 4.6 Measured behavior of α clearly showing non-linear behavior due to dispersion Figure 5.1 Complete small-signal model Figure 5.2 After removal of inductances Figure 5.3 After subtraction of capacitances Figure 5.4 Final intrinsic circuit. After subtraction of series resistances Figure 5.5 Circuit model for Y ds Figure 5.6 Forms of Y gm Figure 5.7 Forms of Y gs,y gd Figure 5.8 Chosen small-signal model; for V ds 6V the effects of R RF and C RF are negligible. 51 Figure 5.9 Model parameters as a function of bias at V ds = 0V Figure 5.10 Dispersive parameters as a function of bias at V ds = 0V Figure 5.11 Model parameters as a function of frequency at V ds = 6V. Most parameters were extracted at 3 GHz; G gs,g gd,g ds at low frequency. How flat the parameter is with frequency is an indicator of model and parasitic accuracy Figure 5.12 Model parameters as a function of bias at V ds = 6V

10 ix Figure 5.13 The intrinsic/corrected transconductance differs from the discrete derivative using measured DC Id-Vg data Figure 5.14 Unity gain frequency at V ds = 6V Figure 5.15 Direct extraction error as a function of gate bias; solid line: V ds = 0V; dashed: V ds = 6V Figure 5.16 Data access components used to load the measured data alongside the simulated circuit Figure 5.17 Optimization goals and S-parameter simulation Figure 6.1 The mobility-fet small-signal model valid at V ds = 0 (cold-fet conditions) Figure 6.2 Measured parameters needed for mobility; 90% of C gg at -10V is the estimate for the fringing capacitance Figure 6.3 Charge sheet density and effective mobility after direct calculation; µ close to pinch-off is not considered accurate Figure 6.4 Universal mobility curve (smoothed using a 5 point moving average) as a function of effective transverse electric field Figure 7.1 Series resistances calculated from the parameter A discussed in Chapter Figure 7.2 Cold-FET temperature coefficients Figure 7.3 Temperature coefficients during on conditions Figure 7.4 Example plot explicitly showing the temperature dependence of the transconductance from -10 to 3V on the gate Figure 7.5 The unity gain frequency also shifted downward with temperature Figure 7.6 DC current measurement over temperature and resulting threshold shift Figure 7.7 Downward dependence of mobility on increasing temperature; the TC is a function of the gate bias Figure 7.8 Mobility and its associated parameters reconstructed from temperature coefficient information; plots (a) and (b) for T = 30,60,90 C Figure 7.9 Chosen network analyzer calibration scheme Figure A.1 2-port FET

11 x Figure A.2 Applied and reflected voltage waves Figure B.1 Forward error model Figure B.2 Reverse error model Figure B.3 Calibration with an ISS shifts reference plane to probe tips Figure B.4 The four SOLT calibration structures present on an ISS Figure B.5 Full 12-term error model obtained by combining the forward and reverse models. The DUT s S-parameters have an i subscript

12 1 1 Introduction The focus of this experimental thesis is on small-signal parameter extraction for an Al- GaN/GaN HFET. Measurement in the 1 to 10 GHz range requires the low-frequency FET model to be modified such that it includes additional components that describe leakage, transconductance delay, and dispersion, if necessary. Due to the geometry and useful frequency range of the devices measured, S-parameters are the means of characterization. While GaN transistors have already been modeled and are currently sold commercially, this work investigates parameter temperature dependence and dispersion phenomena. Dispersion is an undesirable feature that reduces gain by reducing output resistance. It is more common to heterogeneous structures and devices that suffer from trapping effects. By understanding the origin and electrical behavior of the dispersion phenomena better devices can be fabricated and more useful circuits designed. 1.1 Background Accurate determination of a transistor s small-signal elements are needed in order to design useful circuits at a variety of frequencies. Knowledge of the transistor s frequency response is crucial for such things as the development of matching networks that directly determine the noise or gain characteristics of an amplifier. One way to accomplish this characterization is through analysis of a device s S-parameters. S-parameters contain both magnitude and phase information making them capable of completely characterizing a device with resistive and reactive components without the need for any other measurements. Until the late 1980 s, these small-signal elements (or equivalent circuit parameters) were

13 2 typically obtained through numerical optimization. The measured sets of S-parameters were fit to an AC equivalent circuit that best represented the physical device, and an error function was optimized over a large number of iterations. A problem with this approach was that the numerical optimizer could produce non-physical parameter values [1]. Another problem was the large computation time involved in dealing with a set of 15 or so independent parameter variables [2]. Since this time, transistors measured with S-parameters are commonly described using various 2-port matrices. These matrices are described in Appendix A and allow the circuit parameters to be extracted using simple expressions. Nnumerical optimization is only performed at a later step if additional accuracy is desired. Dispersion in GaN is an important topic which stems from the expectation of highperformance GaN microwave power amplifiers. Unfortunately, dispersion in GaN HEMT s is a common problem where the dispersive output admittance reduces PAE (power-added efficiency). Dispersion also manifests in the response of the drain current to an applied gate voltage. A typical amplifier in its off state will have the drain set to a particular bias and the gate kept below threshold, with the gate pulsing for a short period of time to enable drain-current flow. When a device suffers from dispersion, the resulting drain current pulse has amplitude that reduces as the pulse applied to the gate becomes smaller [3]. A first step in dealing with this behavior lies in the characterization of the dispersion phenomena over frequency using S-parameters. 1.2 Overview of work Chapters 2 and 3 concern themselves with finding values for the parasitic circuit elements present in the measured data. Two chapters are spent on this subject since parasitic elements have a large effect on the intrinsic transistor parameters that are of interest. The goal of small-signal parameter extraction is not only to create an accurate model, but also obtain accurate element values. Chapter 4 discusses dispersion and the forms it can take. If dispersion effects are ignored, the drain-source capacitance and conductance will be severely overestimated. A modification to the small-signal model that describes the dispersive output admittance is presented along with equations that solve for all new unknowns. Chapter 5 then uses the techniques and results from Chapters 3 and 4 to analyze the intrinsic small-signal circuit. Results for each parameter as a function of V gs are shown. Field-effect mobility is discussed and calculated in Chapter 6, while Chapter 7 repeats the work of all chapters to analyze the effects of temperature on small-signal parameters.

14 3 2 Substrate permittivity At its most fundamental level, relative permittivity relates the electric flux density (or electric displacement density) D ( C m 2 ) with the electric field intensity E ( V m) in a particular medium. Knowledge of this quantity is required in order to obtain accurate capacitance estimates from EM simulation. GaN s low-frequency static permittivity is approximately 9.5 and decreases with frequency to a steady value in the terahertz range [4]. For accurate modeling, it is necessary to know the correct substrate permittivity that will be input to the EM simulator. This is accomplished through measurement of an on-wafer THRU structure that allows one to determine an effective permittivity ε e accounting for the distribution of the E and H fields partially in the air and partially within the substrate [5]. The structure shown in Figure 2.1 is considered to be a co-planar waveguide with ε e = ε r+1 2 [6]. It will be shown that knowledge of the structure s S-parameters over frequency give an estimate for relative permittivity. For accurate results, measurement should be done at high enough frequencies to overcome the error caused by the capacitance modeling the transition from probe tips to waveguide [7, 8]. 2.1 Matched lossless transmission line For the case of a lossless transmission line with characteristic impedance equal to the reference impedance of the network analyzer, only a phase change affects a wave traveling from end to end.

15 4 Figure 2.1: THRU structure used for obtaining ε e. Distance between probe marks is 150 um. V 2 = V + 1 e jθ (2.1) S 21 = e jθ (2.2) Therefore, measurement of the phase of S 21 gives the electrical length of the line, θ. This value is linear versus frequency for a lossless line and is related to the propagation velocity, v p = c εe. 2.2 Transmission line loss θ = βl (2.3) = ω L (2.4) v p = ω ε e L (2.5) c ( ) c dθ 2 ( ) c dθ 2 ε e = ε r = 2 1 (2.6) L dω L dω If one considers a lossy line, the lossless propagation constant β is replaced by the complex propagation constant γ = α + jβ. There are several sources of substrate loss that can cause the analysis to change slightly.

16 5 1. Dielectric loss Phase lag between D, E ε r = ε r jε r γ = jω µ 0 ε 0 (ε r jε r ) Phase lag between B, H µ r = µ jµ γ = jω µ 0 ε 0 (µ r jµ r ) 2. Finite conductivity of dielectric [9] σ 0, acts like a complex permittivity ε = ε rε 0 jσ/ω γ = jωµσ ω 2 µε For 1), γ can be expanded in a Taylor series to give expressions for α and β provided ε r ε r [10]. This approximation indicates that α has a frequency dependence. γ = jω µ 0 ε 0 (ε r jε r ) k 0 = ω c = ω µ 0 ε 0 (2.7) = jk 0 ε r jε r (2.8) ε r 2 k ε r 0 + j ε rk 0 (2.9) = α + jβ (2.10) Another common approximation for low-loss lines involves the transmission line parameters. A transmission line can be drawn with lumped elements that scale with transmission line length. R conductor loss G dielectric loss C electric field storage L magnetic field storage

17 6 Analysis of the lumped element circuit gives a propagation constant and characteristic impedance defined as γ = (R + jωl)(g + jωc) (2.11) R + jωl Z 0 = (2.12) G + jωc Rearranging γ and expanding in a Taylor series under the assumption that R ωl, G ωc gives a frequency-independent α [11]. α 1 2 ( ) R + GZ 0 Z 0 (2.13) β ω LC (2.14) R,L,G, and C can be determined if both γ and Z 0 are known, accomplished by multiplying or dividing the two quantities and taking the real and imaginary parts as necessary [12]. 2.3 Unmatched transmission line For a matched line, the exciting signal experiences no reflections when transitioning between the measurement probes and the THRU. However, when the characteristic impedance of the THRU no longer matches the reference impedance of the source/load, the transmission line is said to be unmatched. In this case there is a reflection Γ where each probe makes contact with the line resulting in a standing wave. These reflections cause the magnitude of the measured S 21m to no longer equal unity and also change with frequency. Most importantly, the measured phase is corrupted from the true value that would be measured if the test system s reference impedance was matched to the line. To better demonstrate the effects of mismatch, two simple circuits were simulated. The circuit between ports 3 and 4 describe what s actually measured in a 50 Ohm network analyzer. The circuit comprised of ports 1 and 2 is the ideal measurement condition. As predicted, the magnitude and phase behavior plotted worsens as the Z 0 of the transmission line moves farther from the reference impedance.

18 7 50 Ohm reference impedance L G G S Z0 = 50 S G G Figure 2.2: Mismatched THRU line. Under S 21 conditions reflections occur. Term Term1 Num=1 Z=100 Ohm TLIN TL2 Z=100 Ohm E=60.0 F=5 GHz Term Term2 Num=2 Z=100 Ohm Term Term3 Num=3 Z=50 Ohm TLIN TL1 Z=100 Ohm E=60.0 F=5 GHz Term Term4 Num=4 Z=50 Ohm Figure 2.3: The bottom circuit represents the measured behavior.

19 8 1.1 S 21 of 100 Ω (S 21 ) S 21 of 50 Ω (S 43 ) 0 S 21 of 100 Ω (S 21 ) S 21 of 50 Ω (S 43 ) magnitude phase (degrees) f (GHz) (a) f (GHz) (b) Figure 2.4: Simulation results showing difference in measured phase and magnitude as interpreted directly from S 21 of each structure.

20 9 The as-measured circuit is mathematically described using generalized S p -parameters [13]. These account for mismatch of a two-port network with respect to the source and load reference impedances. Solution for the true S 21 that would be measured under ideal conditions requires knowledge of both S p11 and S p21 for a lossy unmatched line. ( ) 1 ΓS (1 ΓL S 22 )(S 11 Γ S S p11 = ) + S 12tS 21 Γ L 1 Γ (2.15) S (1 Γ S S 11 )(1 S 22t Γ L ) S 21 S 12 Γ L Γ S ( ) (1 ΓS ) 1 Γ L (1 ΓS S p21 = S 2 )(1 Γ L 2 ) 21 1 Γ S (1 Γ L ) (2.16) (1 Γ S S 11 )(1 Γ L S 22 ) S 21 S 12 Γ L Γ S Unfortunately, this method requires tedious separation of the real and imaginary parts of both equations and results in a system of four non-linear equations that must be solved numerically [14]. Furthermore, one must know the characteristic impedance of the transmission line in order to compute Γ. Measurement of Z 0 is achieved through conversion of the measured S-parameters to ABCD parameters [15]. following form: A = (1 + S 11)(1 S 22 ) + S 21 S 21 2S 21 (2.17) B = Z re f (1 + S 11 )(1 + S 22 ) S 21 S 21 2S 21 (2.18) C = 1 Z re f (1 S 11 )(1 S 22 ) S 21 S 21 2S 21 (2.19) D = (1 S 11)(1 + S 22 ) + S 21 S 21 2S 21 (2.20) Analysis of the ABCD parameters of a lossy transmission line shows that they are of the A C B D = coshγl Z 0 sinhγl Y 0 sinhγl coshγl (2.21) It is much more desirable to use the ABCD parameters for obtaining α and β than to perform numerical solution of S 21 from the generalized parameters. Here, parameters B and C are used since they were prone to less measurement noise than A and D.

21 10 B Z 0 = C γ = 1 [ ] L sinh 1 BC (2.22) (2.23) α = R[γ] (2.24) β = I[γ] (2.25) Now that α and β are known, a least-squares fit over the desired frequency range can be applied to the corrected data (corrected for mismatch and loss by conversion to ABCD parameters) in order to obtain the true effective permittivity [16]. If the extracted α indeed has a linear frequency dependence then a complex substrate permittivity can be modeled. However, this may not be the exact loss mechanism as other mechanisms may be in play such as substrate conductivity or the finite conductivity of the metal line itself. 2.4 Permittivity results The final values of ε r depend on the statement that ε e = ε r+1 2, which was derived for a CPW line with very thick substrate. Table 2.1: Measured and corrected permittivity Source Type Value related R ε r Measured ε e ε e j0.44 Corrected ε e ε e j0.32 ADS contains the program LineCalc which is capable of determining the electrical characteristics of transmission lines given a set of physical parameters. Coplanar waveguide without a lower ground plane is one of the supported lines. For a 150 um long line, with a gap of 47.5 um, center conductor width of 52.5 um, relative permittivity of 8.0, substrate height of 1000 um and conductor thickness of 0.2 um at 5 GHz, LineCalc predicts values that are close to the measurement

22 11 results. The conductor and substrate heights are approximations and contribute some error to the attenuation. Table 2.2: Theoretical and corrected permittivity Source Z 0 (Ohms) θ (degrees) ε e attenuation (-db) LineCalc Corrected

23 Measured Corrected phase (degrees) ε e = 5.12 ε e = f (GHz) (a) α (m 1 ) Measured Measured Fit Corrected Corrected Fit ε e = 0.15 ε e = f (GHz) (b) Figure 2.5: Phase and loss information from measured S 21 and with correction; Z 0 = 72 Ohms.

24 Correlation coefficient The correlation coefficient R can be calculated whenever data is fit to a line. The closer this value is in magnitude to 1, the more linearly correlated the measured data is [16]. Calculation of this coefficient gives confidence in the relative permittivities that are calculated assuming a linear ω dependence. R = n n i=1 x iy i ( n i=1 x i)( n i=1 y i) n( n i=1 x2i ) ( n i=1 x i) 2 n( n i=1 y2i ) ( n i=1 y i) 2 (2.26) Error analysis for α The extraction of α is more difficult than that of β. If the loss is very low, then the degradation in magnitude of S 21 may be very minor. The network analyzer used to perform the S-parameter measurements gave data that was trusted to within three significant digits. The reason for this tolerance is that RF calibration is partially verified by measuring the THRU response on an impedance standard substrate. The magnitude of S 21 is expected to be ±0.02 db. Conversion of this value to voltage loss/gain is and Therefore, it is expected that the measured S-parameters can at least fluctuate within 99.7% 100.2% of their true value. The measured and corrected S 21 were found to vary between [0.996,0.998]. There are two ways to get better values for α using the techniques described in this chapter: 1. Fabricate longer THRU structures The measured loss will be greater at all frequencies due to an increase in L. 2. Measure higher in frequency For a complex permittivity under the condition of ε r ε r, α is linearly related to ω. The measured loss will be greater at higher frequencies. Higher loss structures will also allow more accurate characterization of the transmission line parameters [17].

25 14 3 Parasitic small-signal elements Accurate determination of the FET s small-signal parameters is impossible without accounting for the undesirable electrical components present in its layout. These components are termed parasitics or extrinsic elements and cause the device to not perform as idealized. Accurate removal of these components is crucial for comparing the intrinsic performance of different transistors. The undesirable electrical elements arise from two sections of the physical layout [18, 19]: 1. Input/output pad Inductance Capacitance 2. Gate/drain/source fingers Resistance Very narrow gate finger (typically small) Channel and contact resistance of drain and source Metal self-inductance (primarily gate and drain) Metallization or finger capacitance between gate, drain, and source Scales linearly with total width for multi-fingered structures of identical unit width The input and output pads are technically a distributed transmission line. However, at the frequencies of interest a lumped element model is sufficient that ignores transmission line loss [20].

26 15 S G D S Figure 3.1: The two sources of parasitics for a 2-finger FET. Such a network of lumped components is shown in Figure 3.2. The intrinsic circuit is drawn within the dotted box. 3.1 Simplifications There are two main simplifications that can be made depending on the measurement frequency. Only one set of parasitic capacitances are drawn since the inter-finger capacitances are often lumped together with the pad capacitances or simply ignored. Scaling techniques or dummy FETs can theoretically isolate pad from inter-finger capacitance, but there is ambiguity in the amount of effective inter-finger capacitance due to the presence of a channel depletion region [18]. If ignored, the finger capacitances will be embedded within the intrinsic FET depletion capacitances. EM simulation will show that these are theoretically small when compared to the pad capacitances, minimizing any error regardless of how they are handled.

27 16 C pgd Port 1 L pg R g Lpd C pgs Y GS + V gs - Y GD Y gm V gs R d C pds Y DS Port 2 R s L s Figure 3.2: A complete small-signal model. The dotted box encloses the intrinsic FET circuit. Similarly to the parasitic capacitances, the pad and finger inductances are often lumped together as shown in Figure 3.2. Extraction of these inductances will only be briefly mentioned in the following discussions. Since the devices used in this work displayed predominantly capacitive behavior over all gate biases, the inductances could not be extracted. Furthermore, inductances for um-scale on-wafer RF structures are often determined in the frequency range well over 10 GHz. The network analyzer used in this work was frequency limited and thus the inductances were ignored in the final modeling procedure. A variety of methods used to quantify these parasitics will now be discussed.

28 Overview of capacitance methods EM simulation A T-gate FET from a 0.7 um AlGaN/GaN HFET analyzed in this thesis is pictured in Figure 3.3. The T-gate structures were the focus of this work since they were less prone to gate-drain breakdown than 2-finger FETs located elsewhere on the wafer. Once the physical dimensions of the device are known it can be replicated within Agilent Momentum. Momentum is an electromagnetic simulator utilizing the method of moments to determine S-parameters for planar circuits [21]. (a) (b) Figure 3.3: photo of 0.7um x 80um T-gate FET and drawn structure in Momentum. Crucial to accurate simulation is knowledge of the substrate dimensions, conductor thickness, and substrate relative permittivity. The T-gate FET shown in Figure 3.3 is basically GaN on an insulating sapphire substrate. When this wafer is measured it sits on an ungrounded chuck. Therefore, a thick substrate value was used without a lower ground plane. Relative permittivity was obtained via analysis of an on-wafer THRU line discussed in Chapter 2. It is important to point out that the methodology presented here is specifically targeted for analysis of parasitic capacitances, not inductances. A simplified drawing is shown in Figure 3.4 that describes the origin of each for an on-wafer FET without a lower ground plane. The Y-parameters of the structure in Figure 3.3 were simulated in order to provide esti-

29 18 Source C pgs C pds Gate Drain C pgs C pds Source C fgs C fgd Figure 3.4: Simplified parasitic capacitances are between metals in absence of a lower ground plane. mates. C pgs +C f gs = Y 11 +Y 12 ω C f gd = Y 12 ω C pds = Y 22 +Y 12 ω (3.1) (3.2) (3.3) An interesting note for a 1-finger device is that by observation the total drain-source parasitic capacitance should be lower than that between gate-source and gate-drain. This is because there is no drain-source finger capacitance. Also, there is no gate-drain pad capacitance because of the T-gate layout. Both these things are not true for a multi-fingered device that has another metalization layer or source air-bridge. The resulting values for C f gs,c f gd are not completely present in the actual device due to

30 19 the presence of a depletion region [18]. The amount calculated here should be multiplied by an unknown fraction that depends on gate and drain bias. Due to the unknown value of this fractional quantity, it is necessary to compare the EM simulation results with reverse cold-fet measurements. If the EM values are greater than the total capacitances observed from cold-fet measurements below pinch-off, then they are too large and must be downsized Reverse cold-fet The favored FET technique for de-embedding the extrinsic components is the cold-fet method [1]. It originates from qualitatively examining the 2-D cross-section of the FET at zero drain-source bias. In this state, the channel is symmetric on either side of the gate and the g m current generator can be ignored thus creating a passive network. The reverse cold-fet depletes the entire channel between source and drain with a large negative voltage at or below pinch-off. The small-signal model is then simplified to nothing but capacitors at low frequency. The value of the parasitic series components are ignored by noting that at low frequency the capacitances dominate. C pgd C fgd Port 1 C pgs C fgs C gs C gd C fds Port 2 C ds C pds Figure 3.5: Low-frequency small-signal model for a fully depleted FET with V ds = 0. I[Y 11 +Y 12 ] = ω(c pgs +C f gs +C gs ) (3.4) I[Y 22 +Y 12 ] = ω(c pds +C f ds +C ds ) (3.5) I[Y 12 ] = ω(c pgd +C f gd +C gd ) (3.6)

31 20 Scaling Unfortunately, the depletion capacitances C gs,c gd,c ds are included in each expression and are bias-dependent. These depletion capacitances scale with width. As mentioned earlier, the gate/source/drain finger capacitances also scale with width. By examining multi-fingered FETs of the same unit width the following description of the above small-signal model holds [18], I[Y 11 +Y 12 ]/ω = C pgs + ( C f gs +C gs) Wtot (3.7) I[Y 22 +Y 12 ]/ω = C pds + ( C f ds +C ds) Wtot (3.8) I[Y 12 ]/ω = C pgd + ( C f gd +C gd) Wtot (3.9) From these equations, it is seen that a plot of each equation versus total gate width (or number of fingers) results in a line whose intercept is equal to the pad capacitance. Even if done at multiple gate-biases, each line should share the same intercept. The only downside of this approach is that the capacitance between the various metal fingers cannot be isolated. In this case, these values will be lumped with the intrinsic FET s capacitances after the final extraction. A source of confusion arises when the small-signal model in Figure 3.6 is drawn. In this model, all parasitic components are lumped into general parasitic terms C pgs,c pgd,c pds. The method of parasitic extraction determines if the finger capacitances are analyzed. C pgd Port 1 C ds C pgs C gs C gd C pds Port 2 Figure 3.6: Alternate small-signal model for a fully depleted FET with finger and pad capacitances combined (V ds = 0). 3.3 Parasitic capacitance results

32 21 Table 3.1: Parasitic capacitance values ADS Momentum (ff) Value Cold-FET (ff) V gs = 10V C pgs +C f gs 14.9 C pgs +C f gs +C gs,dep 29.5 C f gd 3.9 C f gd +C gd,dep 18.1 C pds 13.7 C pds +C ds,dep C gs,total C gd,total C ds,total 60 (ff) Reverse cold FET values extracted here V gs (V) Figure 3.7: Cold-FET capacitances, V ds = 0.

33 Overview of series resistance methods Series resistances are exclusive of the channel resistance, R ch (also referred to as g ds ). They can be quite large and negatively effect device performance, making them an important focus when developing a small-signal model. Their presence also causes disagreement between DC- and RF-determined values for transconductance and output resistance DC technique for MESFET s A useful approach to obtain an estimate for source and drain resistances is described in [22]. This method is only applicable to MESFET-like structures with gates that can conduct. Therefore, MOSFET s and MISFET s are not valid structures for this technique. G S R G D R S R ch a R ch (1-a ) R D Figure 3.8: Forward-biased MESFET-like structure (a = α). Assuming the gate is forward biased, the drain and gate voltages can be written, V ds = I d (R ch + R s + R d ) + I g (αr ch + R s ) (3.10) V gs = V diode + (R s + αr ch )(I d + I g ) (3.11) = nkt ( ) q ln Ig + (R s + αr ch )(I d + I g ) (3.12) I s where α is a number between 0 and 1 that represents the fraction of gate current flowing through the channel. For a symmetric device it can be set to 0.5. R ch is the channel resistance. The diode parameters can be found by examining the linear region of ln(i g ) vs V gs for low gate currents. The unknowns are: R s,r d,r ch. One DC sweep and one AC measurement are required to obtain all unknowns.

34 23 1. Hold I g constant, sweep I d The slope of V gs vs I d gives R s + αr ch The slope of V ds vs I d gives R ch + R s + R d 2. Measure S-parameters for sufficiently large V gs Extract G ds = 1/R ch from Z-parameters. Since G ds is gate bias dependent, the channel conductance has to be extracted at a similar gate bias as produced by step Forward cold-fet While the reverse cold-fet can apply to other device types, the forward cold-fet is unique to the FET s with a Schottky gate. A large gate bias is applied that turns-on the gate-channel Schottky diode and S-parameters are taken at high frequency. The 2-D cross section under the gate changes to a very small depletion region. Cgs and Cgd are combined into one capacitance in parallel with a resistor that models the Schottky diode under RF conditions. The pad capacitances are ignored by arguing that the forward-biased Schottky provides a much higher conductive path [1]. The smallsignal model is drastically altered in the form of: g diode g gd C diode L pg R g C gd R d L pd Port 1 g gs C gs G ds C ds Port 2 R s R ch (1-a) L s R ch a Figure 3.9: Simplifications for a forward-biased gate.

35 24 L pg R g g diode R ch (1-a ) R d L pd Port 1 C diode Port 2 R cha R s L s Figure 3.10: Heavily forward-biased FET with V ds = 0. Typical α = 0.5.

36 25 Z-parameters usefully describe this circuit, since the real and imaginary parts isolate the parasitic series inductances and resistances. By writing the Z-parameters it becomes immediately obvious how to isolate each parasitic component of interest provided several assumptions are made. Ideally, the real parts of the Z-parameters are invariant with frequency and the imaginary parts are linear with frequency. Z 11 = R g + R ch α + R s + [ R diode 1 + (ωr diode C diode ) 2 + jω R 2 diode L pg + L s C ] diode 1 + (ωr diode C diode ) 2 (3.13) R g + nv th I g + R s + R ch α + j(ωl pg + L s ) (3.14) Z 12 = R ch α + R s + jωl s (3.15) Z 22 = R d + R ch + R s + j(ωl pd + L s ) (3.16) This is the classic forward cold-fet analysis for MESFET-like structures. It is common for the R ch term in each equation to be dropped if it is deemed negligible. The simplification made in the real part of Z 11 is valid at either very high frequency or the condition ωr diode C diode 1 and R diode R g. The imaginary part is written for ωr diode C diode 1 such that the capacitive effect diminishes Non-ideal cold-fet modeling Often, the capacitive effect of the gate-source and gate-drain depletion regions cannot be overcome while applying a non-destructive gate-bias. As a result, the real part of each Z-parameter changes with frequency and the small-signal model drawn in Figure 3.10 is invalid. In this situation it is more useful to analyze the small-signal model in Figure This model assumes the parasitic capacitances have first been de-embedded. By manipulating the imaginary part of Z 22, the real parts of the Z-parameters can be written in a convenient form [23]:

37 26 R g R d Port 1 G ds C gs C gd C ds Port 2 R s Figure 3.11: Simplified equivalent circuit after parasitic capacitance de-embedding. R d C ds +C gd C gs /(C gd +C gs ) G ds Port 2 R s Figure 3.12: Simplified equivalent circuit for Z 22 calculation.

38 27 [ ( Z 22 = R s + R d + jω C ds + C ) ] 1 gdc gs + G ds (3.17) C gd +C gs = R s + R d + G ds jωc 22 G 2 ds + ω2 C22 2, C 22 = C ds + C gdc gs C gd +C gs (3.18) ω I[Z 22 ] = G2 ds + ω 2 C 22 C 22 (3.19) Therefore, a plot of ω I[Z 22 ] versus ω2 should be linear with slope equal to C 22 and intercept related to R ch = 1/G ds. Together, C 22 and R ch are combined to form a function A. The reason for this becomes clear once the real part of each Z-parameter is written. R[Z 11 ] = R g + R s + C 2 gd (C gd +C gs ) 2 R ch 1 + ω 2 R 2 ch C2 22 (3.20) = R g + R s + C 2 gd (C gd +C gs ) 2 A (3.21) R g + R s A (3.22) C gd R[Z 12 ] = R s + A (3.23) C gd +C gs R s A (3.24) R[Z 22 ] = R d + R s + A (3.25) R ch A = 1 + ω 2 R 2, R ch = 1 (3.26) ch C2 22 g ds R g = R[Z 11 Z 12 ] A (3.27) R d = R[Z 22 Z 12 ] 1 2 A (3.28) R s = R[Z 12 ] 1 2 A (3.29) The small-signal model is drawn for V ds = 0; in this state, the channel region is uniform and it is assumed that C gs C gd, giving rise to the factors of one-half and one-fourth. Extraction of the function A at multiple gate biases has the advantage of quantifying series resistances that are bias-dependent [23]. Two observations are made with respect to gate leakage and measurement capability.

39 28 Leakage resistances The gate-source and gate-drain leakage paths increase with increasing gate-bias as the Schottky barrier is overcome. At low frequencies these resistances represent a lower-impedance path than C gs and C gd. As a result, the Z-parameters written above are not valid until higher frequencies. For a typical gate-source leakage resistance of 80 kohms and associated C gs of 80 ff, the reactance drops below the resistance at 25 MHz. Hardware frequency limitations When the network analyzer is able to take measurements out to the point where A = R ch 0, then the calculation of A can be avoided. Each Z-parameter will settle to a 1+ω 2 R 2 ch C2 22 final value. 3.5 Series resistance results Bias-independent analysis The estimated channel conductance using Equation 3.19 was 30 Ohms. Half this value was subtracted from each appropriate equation. R g = R[Z 11 Z 12 ] 1 2 R ch (3.30) R d = R[Z 22 Z 12 ] 1 2 R ch (3.31) R s = R[Z 12 ] 1 2 R ch (3.32)

40 29 real[z 11 Z 12 ] Vgs real[z 22 Z 12 ] Vgs real[z 12 ] Vgs Figure 3.13: Solid line, extrinsic Z-parameters; dashed line, parasitic capacitances removed. Resistances are estimated at the greatest frequency and forward bias applied in the classical forward cold-fet technique (in this V gs = 3V).

41 Bias-dependent series resistances The FET measured in this work suffered from dispersion, thus changing the cold-fet small-signal model of Figure For reasons explained in the chapter on dispersion, Figure 3.11 is still assumed valid at high frequency. The following values of C out and g ds were then extracted by fitting α to a line between 7 and 10 GHz g ds (ms) C 22 (ff) V gs (V) V gs (V) Figure 3.14: Estimates for g ds and C 22 from α.

42 R g (Ohms) R d (Ohms) Vgs (V) Vgs (V) R s (Ohms) Vgs (V) Figure 3.15: Solid line: correction using parameter A; dashed line: from Z-parameters with parasitic capacitances removed. The method involving A was not useful for V gs < 6V, which was likely due to a failure of the assumed small-signal model to accurately describe the channel conditions.

43 32 Table 3.2: Summary of series resistance results Resistance Method 1 (Ohms) Method 2 (Ohms) Method 3 (Ohms) R g R d R s Summary The bias-dependence of the series resistances proved weak and a bias-independent value was deemed appropriate. This value was calculated by taking the average over gate bias. The three possible methods are now summarized and the results shown in Table Forward cold-fet measurement. R g,r d, and R s from the real parts of Z 11 Z 12,Z 22 Z 12, and Z 12 minus half the estimated channel resistance at the appropriate forward bias on the gate (using extrinsic Z-parameters). 2. Forward cold-fet measurement with parasitic capacitance de-embedding. R g,r d,r s obtained the same as above after capacitance subtraction from extrinsic Y- parameters. 3. cold-fet measurement with parasitic capacitance de-embedding and calculation of the parameter A. Explains any frequency-dependence of the forward Z-parameters and is performed at every bias point.

44 33 4 Dispersion Dispersion in FET s generally refers to atypical frequency behavior of the transconductance or the output admittance block. Two potential sources of dispersion are trapping effects or a parallel conduction mechanism. The latter occurs primarily in devices constructed by the stacking of heterogeneous materials, particularly HFET s/hemt s. In the case of an AlGaN/GaN HFET, high-frequency signals can propagate through the AlGaN layer as well as the 2DEG that forms at the AlGaN/GaN interface after a critical 2DEG charge density develops [24, 25]. This is similar phenomena as seen in GaAs HEMT s [26]. Source Gate Drain AlGaN 2DEG GaN Sapphire Figure 4.1: Cross-section of the HFET analyzed in this work. If the real and imaginary parts of the intrinsic admittance Y ds both exhibit a large frequency dependence, then the device suffers from output admittance dispersion. This can be modeled by

45 34 - V dg + Port 1 + Y GD g m,rf V dg R RF Port 2 Y GS V gs - g m V gs g ds C ds C RF Figure 4.2: Output admittance dispersion and g m dispersion due to additional VCCS g m,rf. adding a resistance (R RF ) and capacitance (C RF ) in parallel with g ds and C ds [27]. Depending on the frequency behavior of Y gm, the small-signal model can also have an additional current generator, g m,rf [28]. This voltage-controlled current source is placed in parallel with the dispersive resistance element and has a controlling voltage, v dg. It is important to note that these circuit modifications simply model the electrical behavior of the device and do not necessarily indicate the physical dispersion mechanism. 4.1 g m dispersion For the case of transconductance dispersion, the admittance term Y gm described in Chapter 5 takes on a new form with an imaginary part that can be manipulated to form a straight line. Y gm = Y 21 Y 12 (4.1) jωc RF R RF = g m g m,rf 1 + jωc RF R RF (4.2) ω I[Y gm ] = 1 ( τ 1 RF g ) ω2 τ RF, m,rf τrf = C RF R RF (4.3) Therefore, if the slope (m) and intercept (c) are extracted from a plot of I[Y gm ] versus ω2, then ω