High-k Gate Dielectrics for Future CMOS Technology

Transcription

1 Hih-k Gate Dielectrics for Future CMOS Technoloy T.P. Ma Yale University, Center for Microelectronics, and Department of Electrical Enineerin New Haven, CT Introduction Hih-k dielectrics are bein actively pursued by the semiconductor industry to replace as the ate dielectric for future enerations of CMOS transistors. The 24 ITRS [] calls for ate dielectrics of less than nm in equivalent ide thickness (EOT) in the near future, with a very low ate leakae current. Most experts believe that only some sort of hih-k ate dielectrics will be able to fulfill these requirements. The first roup of hih-k dielectrics that was proposed to replace in recent years consisted of silicon nitride or silicon ynitride [2,3]. The concept of usin a hih-k dielectric s larer physical thickness to achieve the same EOT so as to reduce the tunnelin leakae current was clearly presented in [2], and the search for the best hih-k ate dielectric has continued ever since. As a result of intense research efforts throuhout the world, sinificant proress has been made, and there is a clear understandin of the important scientific as well as technoloical issues that need to be resolved before a viable hih-k ate dielectric technoloy may be implemented in production. Amon these issues, the ate leakae problem seems to be mostly under control, as essentially all research roups have reported hih-k ate leakae currents several orders of manitude lower than their counterparts of the same EOT s. In contrast, other issues such as thermal stability, interfacial layer control, EOT control, reactions with poly, and metal ate electrodes are still posin varyin derees of challenes that require more R&D to overcome, and this talk will ive an overview of these challenes and the proress that has been made by various R&D roups. Because of the space limitation, this extended abstract cannot cover all of the research results that will be reviewed at the oral presentation; instead, only a few examples will be iven here in this written document, and an emphasis will be iven on the electrical characterization of hih-k ate stacks because of the author s expertise. Materials and Processin Related Issues Fiure shows a schematic cross-section of a MOSFET, where some key reions surroundin the hih-k ate dielectric are hihlihted. Of these reions, the hihk/substrate interface is of utmost importance, as it could sinificantly affect the over-all EOT of the ate stack, as well as the MOSFET s electrical properties and reliability. nce it was suested that and ZrO 2 should be thermodynamically stable on [4], these two dielectrics quickly replaced TiO 2 and Ta 2 O 5 as the favorite hih-k dielectrics amon various R&D roups. Later on it was found that an interfacial layer inevitably formed between or ZrO 2 and substrate, despite the theoretical thermodynamic predictions. By then, the momentum was so hih that the R&D community decided to lock in the system (as it has a more stable interface with than ZrO 2 ), and tried to use silicate or nitridation to stabilize the interface [7]. milarly, the electrode/hih-k interface is also very important, as the formation of an interfacial layer there normally lowers the effective dielectric constant, and could cause deraded electrical performance. In severe cases, the so-called Fermi-level pinnin phenomenon could occur which adversely affects the threshold voltae [5]. Thus, proper enineerin of the electrode/hih-k interface is another important issue that is bein actively pursued. In addition to the two interfaces described above, the bulk of the hih-k film must be thermally stable. While no consensus has reached, many hold the opinion that the hih-k ate dielectric must be either amorphous or sinle crystalline. nce the viability of sinle-crystalline hih-k ate dielectric is still in the distant future, amorphous hih-k ate dielectric has become the desired form, instead of the polycrystalline alternative. This is primarily based on the uniformity arument. Essentially, it is known that some properties, such as the dielectric constant and leakae current, are different between the crystalline reions and the rain boundaries, and therefore one would expect sinificant non-uniformities of EOT, threshold voltae, and ate leakae distributions in hihdensity interated circuits containin numerous small-size devices, of which some devices may contain primarily crystalline hih-k ate dielectrics while others are primarily around rain boundaries. Given the requirement for an amorphous hih-k ate dielectric, the rankin of as a desired hih-k ate dielectric drops considerably, because it tends to crystallize at a relatively low process temperature (< 5 C) [6]. In order to overcome this problem, one may add Al in to form HfAlO [6], or use Hf ynitride, Hf silicate, or nitrodized Hf silicate [7-9]. All of these approaches raise the crystallization temperature at the expense of reducin the dielectric constant. Fiure 2 shows that the dielectric constant is reduced, and the bandap is increased, with the addition of Al in, alon with an increase in the crystallization

2 temperature. Chare Trappin and Mobility Deradation It is now well known that the channel mobility in a hih-k ated MOSFET is typically lower than its - ated counterpart. nce it is also well known that hih-k ated MOSFET tends to have more ide chare and interface traps than its -ated counterpart, it s not surprisin that many attribute the deraded channel mobility to Coulomb scatterin by ide chare and interface traps. Upon more careful examination, however, we found that part of the deradation may arise from the soft optical phonons in the hih-k ate dielectric that act as remote phonon scatterin centers and reduce the channel mobility, which is consistent with the theory proposed by Fischetti et al [] In the course of our study of channel mobility to determine the possible scatterin mechanisms, we found that the conventional methodoloy used to obtain the channel mobility in hih-k ated MOSFET ives rise to very lare errors, due to the trappin of carriers. Basically, the use of the conventional split C-V method to extract the carrier concentration in the conduction channel over estimates that concentration due to trappin of carriers, which results in an underestimate of the channel mobility []. This error could be as hih as 3-5%, based on the typical interface trap density of hih /cm 2 to low 2 /cm 2 []. Therefore, we have introduced a modified split C-V method to more accurately extract the channel mobility [], and this methodoloy is briefly depicted in Fi. 3. It should be noted that trappin/detrappin time constants for some of the hih-k ate dielectrics, includin and Al 2 O 3, are much shorter than those for [2], and therefore the DC measurement methodoloy commonly used for MOS devices with ate dielectric will likely to miss these traps. A transient (pulsed) measurement methodoloy has been introduced to reveal more fully the traps in hih-k ate dielectrics [2]. Usin the more accurately determined mobility data, we have analyzed the possible scatterin mechanisms that may have caused the deraded mobility in hih-k ated MOSFETs, and concluded that Coulomb scatterin indeed plays a critical role in reducin the channel mobility in hih-k ated MOSFET, as expected. Fiure 4 shows the stron correlation between the channel mobility and the density of interface traps which serve as Coulomb scatterin centers. In addition, we have also athered evidence that supports the remote phonon scatterin theory proposed by Fischetti, et al []. Fiure 5 shows that, compared to its counterpart, the sample made of as the ate dielectric suffers from additional source of phonon scatterin, which can be attributed to the remote soft optical phonons in the layer Inelastic Electron Tunnelin Spectroscopy (IETS) This section introduces a novel technique to probe phonons, traps, microscopic bondin structures, and impurities in hih-k ate dielectrics with a versatility and sensitivity that are not matched by other techniques. This technique is called the Inelastic Electron Tunnelin Spectroscopy (IETS), which basically takes the 2 nd derivative of the tunnelin I-V characteristic of an ultrathin MOS structure. The basic principle of the IETS technique is illustrated in Fi.6, where one can see that, without any inelastic interaction, the I-V characteristic is a smooth curve, and its 2 nd derivative is zero. When the applied voltae causes the Fermi-level separation to be equal to the characteristic interaction enery of an inelastic enery loss event for the tunnelin electron, then an additional conduction channel (due to inelastic tunnelin) is established, causin the slop of the I-V characteristic to increase at that voltae, and a peak in its 2 nd derivative plot, where the voltae location of the peak corresponds to the characteristic enery of the inelastic interaction, and the area under the peak is proportional to the strenth of the interaction. In a typical MOS sample, there are more than one inelastic mode, as a wide variety of inelastic interactions may take place, includin interactions with phonons, various bondin vibrations, bondin defects, and impurities. Therefore, Fi.7 is shown to represent the typical IETS spectrum that one expects to see. Fiure 8 shows an actual IETS spectrum taken on an Al/ / sample, where the features below 8 mev correspond to phonons and phonons, and the features above 2 mev correspond to Hf- and phonons. The sinificance of this IETS spectrum is that it confirms the stron electron-phonon interactions involvin optical phonons in, and that the phonons have very similar enery rane as phonons which we know are a source of scatterin centers that derade the channel mobility. Therefore, these data indirectly support Fischetti s remote phonon scatterin model []. Fiure 8 also shows features correspondin to Hf-- O and phonons. nce these phonons have much hiher eneries than kt at room temperature, they are not effective scatterin centers at room temperature. IETS can also be used to probe electronic traps in ate dielectrics. Fiure 9 shows stress-induced trap features in a set of Al/ / samples, where one can see the increase of trap density as the electrical stress time increases. We have found that it s possible to reveal the spatial locations and eneries of these traps by analyzin the IETS spectra in both voltae polarities [3], and the details of which will be presented at the conference. 2

3 Acknowledment The author would like to thank former and current raduate students, Wenjuan Zhu, Whye-Kei Lye, Wei He, and Miaomiao Wan, for their contributions to this paper, and SRC and Sematech for their financial support. References. The national technoloy roadmap for semiconductors technoloy needs: Semiconductor Industry Associations (SIA), Kukesh Kahare, Xiewen Wan, and T.P. Ma ``Extendin Gate Dielectric Scalin Limit by Use of Nitride or Oxynitride', 995 International Symposium on VLSI Technoloy, Kyoto, Japan, June 6-8 (995). 3. T. P. Ma, Makin licon Nitride Film a Viable Gate Dielectric, IEEE Transactions on Electron Device, Vol.45, pp68-69, K.J. Hubbard, and D.G. Schlom, Thermodynamic stability of binary ides in contact with silicon, J. Mater. Res., Vol., No., p , C. Hobbs, L. Fonseca, V. Dhandapani, et al. Fermi Level Pinnin at the Poly/Metal OixdeInterface". In Diest of IEEE VLSI Technoloy Symposium, pp. 8-9, Kyoto, W. Zhu, T. Tamaawa, M.Gibson, T. Furukawa, and T.P. Ma, Effect of Al inclusion in on the physical and Electrical Properties of the Dielectrics, IEEE Electron Device Letters, vol.23(), 649 (22). 7. Jack C. Lee, H. J. Cho, C. S. Kan, S. J. Rhee, Y. H. Kim, R. Choi, C. Y. Kan, C. H. Choi, and M. Akbar, Hih-K Dielectrics and MOSFET Characteristics, IEDM Tech. Di., p.95 (23). 8. M. Koyama, A. Kaneko, T. Ino, M. Koike, Y. Kamata, R. Iijima, Y. Kamimuta, A. Takashima, M. Suzuki, C. Hono, S. Inumiya, M. Takayanai and A. Nishiyama, Effects of nitroen in HfON ate dielectric on the electrical and thermal characteristics, IEDM Tech. Di. p.849 (22). 9. L. P. Rotondaro, M. R. Visokay, J. J. Chambers, A. Shanware, R. Khamankar, H. Bu, R. T. Laaksonen, L. Tsun, M. Doulas,R. Kuan, M. J. Bevan, T. Grider, J. McPherson, L. Colombo, Advanced CMOS Transistors with a Novel HfON Gate Dielectric, Symp. VLSI Tech., p.48 (22).. M. Fischetti, D. Neumayer and E. Carttier, Effective electron mobility in inversion layers in MOS systems with a hih-k insulator: the role of remote phonon scatterin, J. Appl. Phys., Vol.9, pp.4587, 2. W.J. Zhu, J.P. Han, and T.P. Ma, Accurate measurement of mobility in MOSFETs made with ultra-thin hih-k dielectrics, IEEE Trans. Electron Devices, Vol.ED-5, No., pp.98-5 (24) 2. Kerber, E. Cartier, R. Deraeve, Ph. Roussel, L. Pantisano, T. Kauerauf, G. Groeseneken, H.E. Maes, U. Schwalke, Chare Trappin and Dielectric Reliability of O2 / Al2O3 Gate Stacks with TiN Electrodes", IEEE Transaction on Electron Devices, Vol. 5, No. 5, pp , (23). 3. Miaomiao Wan, Wei He, and T.P. Ma, Electron Tunnelin Spectroscopy Study of Traps in Hih-k Gate Dielectrics: Determination of Physical Locations and Enery Levels of Traps, to be published in Applied Physics Letters Cross-sectional View of a MOSFET Spacer Hih -k Gate Dielectric Stack Source Substrate Drain Gate electrode, poly Upper interfacial reion Bulk hih -k film Lower interfacial reion Fi. Cross-sectional view of a MOSFET with hih-k ate dielectric Crystallization Temperature ( o C) HfAlO, ~8nm Al Percentae (%) Al Percentae (%) Al inclusion in results in: hiher crystallization temperatur larer bandap, but lower dielectric constant Fi.2 Crystallization temperature, bandap, and dielectric constant as a function of Al concentration. C c /Area (x -8 F/cm 2 ) I d (µa) Bandap (ev) 2 8 Dielectric Constant Mobility from Split CV -Interface trap correction for mobility extraction Ideal 5 w/o N it V V (V) V 2 Measured With N it (a) V (V) (c) µ µ 2 Q inv (µc/cm 2 ) Ideal w/o N it 5 Q Q 2 Measured With N it (b) With N it Correction W/O N it Correction (d) Q inv (µc/cm 2 ) Q, not Q 2, should be used for mobility extraction C c /Area (x -8 F/cm 2 ) Effective Mobility µ eff (cm 2 /V-s) eff L w I ( V ) d d inv V Q ( V ) Fi.3 Illustration of the modified split CV method for extractin the carrier concentration and channel mobility. µ = 3

4 Mobility vs Interface Traps as Coulomb Scatterin Centers µ eff (cm 2 E eff =.MV/cm 6 nmosfet , 7 o C HfAlO, 7 o C, 6 o C HfAlO, 6 o C D it from Swin (x 3 cm -2 ev - ) The effective mobility is hihly correlated with the interface trap density, suestin that Coulomb scatterin is one major deradation mechanism for these hih-k dielectrics Fi. 4 Channel mobility is stronly correlated to the interface trap density Scatterin Rate due to Phonons The difference between HfO2 and O2 is attributed to /µ ph (cm 2 /V-s) soft optical phonons in.85mv/cm.75mv/cm.65mv/cm difference between HfO. 2 and Temperature (K) The scatterin rate by the additional soft optical phonons in is a weak function of temperature, which is consistent with theoretical calculation. Fi.5 Additional phonon scatterin in HfO2-ated MOSFET is attributable to soft optical phonons in. Scatterin Rate (x 3 s - ) Inelastic Electron Tunnelin Spectroscopy An Inelastic Tunnelin Event at E=eV = hν Causes (a) I-V to increase slope; (b) a step in di/dv; (c) a peak in d 2 I/dV 2 I di/dv d 2 I/dV 2 Various Inelastic Modes in the Barrier (Left) May Be Reflected in IETS (Bottom Riht) Elastic Elastic Inelastic ev=hν d 2 I dv 2 Elastic Inelastic V IETS probes phonons, bondin vibrations, impurities, and Traps Fi.6 Inelastic interaction causes a slope increase of I-V, a step in di/dv, and a peak in 2 nd derivative, all occurrin at the voltae correspondin to the characteristic enery. Fi.7 Typical IETS spectrum (lower riht curve) reveals the various inelastic modes depicted in the enery diaram on the left. IETS (A. U.) IETS (A.U.) IETS nals for / -Hf IETS (A. U.) -Hf IETS Reveals Stress-Induced Traps d 2 I/dV 2 (A.U.) After 8s.2V stress After 2s.2V stress Oriinal Increasin Stress Traps Voltae (mv) Voltae (mv) Lower enery peaks are and phonons; Hiher enery peaks are and O-Hf phonons IETS has hih sensitivity in detectin traps. Fi. 8 IETS spectrum for Al/HfO2/ sample, revealin phonons between 5 and 75 mev, and, - phonons at hiher eneries. Fi. 9 IETS spectrum for Al/HfO2/ sample, showin stress-induced trap features. 4

5 Hih-k Gate Dielectrics for Future CMOS Technoloy MOS Transistor Gate Stack T.P. Ma Yale University Center for Microelectronics Spacer Hih-k Gate Dielectric Stack Gate electrode, poly Poly or Metal Upper interfacial reion Bulk hih-k film Contributors: Wendy Zhu, Wei He, Mukesh Khare Source Substrate Drain Lower interfacial reion Year of Production DRAM ½ Pitch ITRS Gate Stack Parameters Physical Gate Lenth MPU/ASIC (nm) Equivalent physical ide thickness for MPU/ASIC T (nm) Gate dielectric leakae at C (ma/µm) Hih-performance 24 9 nm nm nm nm nm Tunnelin current increases exponentially with decreasin ide thickness Equivalent physical ide thickness for low standby power T (nm) Gate Dielectric Leakae (pa/µm) LSTP Thickness control EOT (% 3s) <± 4 <± 4 <± 4 <± 4 <± 4 Taur, IEEE Spectrum, July 999 Metal/Oxide/Semiconductor (MOS) Transistor Speed Increases with Chare Carryin Capacity, Q. Q = CV Dielectric constant where C = ε /d Oxide thickness To Increase C: Decrease d Increase ε (ε = k ε o ) Hih-k dielectrics First viable hih-k ate dielectric 3 N 4 Thermal Oxide J ε : 3.9 ε ni : nm c exp( φ 2 3 b V T licon Nitride C = ε T ε ni = 2.ε ) 4 nm T physical = 2.T EOT 4 nm licon Nitride has 2nm of Equivalent Oxide Thickness (EOT)

6 licon Nitride Shows Lower Gate Tunnelin Currents (Theoretical) Nitride ε=6.5 Top View of JVD System Gate Current Density(A/cm 2 ) A A A 4 A : Oxide : Nitride Dielectric Yale Group, VLSI Technoloy Symposium, June 995 JVD licon Nitride on Capacitance ( X pf ) JVD licon Nitride EOT = 4.5 nm Ave. N = 6 X /cm 2 /ev it Gate Voltae ( V ) lo(j/e 2 ) JVD Nitride Physical Thickness: 8.9nm Equivalent Oxide Thickness: 5.nm /E (cm/mv) Fowler-Nordheim Plot of Current Throuh JVD licon Nitride Gate Current Density (A/cm 2 ) Comparison of Measured Gate Leakae Current 2 2 A - 2 A 4 A A A 39 A Oxide JVD nitride Dielectric

7 Transistor Characteristcs of Sematech s.5 um Technoloy with 2. nm JVD licon Nitride Drain Current [Id, A] W/L=/.5 µm Vd=.5 V Vd=5mV S.S.=72. mv/dec. Dielectric Constants of Some Hih-k Materials Drain Current [Id, ma] W/L=/.5 µm V - Vth.5V.V.5V Drain Voltae [Vd, V] -4 Gm x T (ms x Å ) Gate Voltae [V, V] W/L=/.5 µm T eq, =2.5 nm Vd=.-.7V step =.4V V - Vt ( V ) Karamcheti et al., MRS Fall Meetin, Nov. 999 Challenes of Hih-k Dielectrics EOT Control Thermal Stability Mobility & Threshold Voltae Trappin Induced Instability Challenes of Hih-k Dielectrics EOT Control Thermal Stability Mobility & Threshold Voltae Trappin Induced Instability (After Garfunkel)

8 Challenes of Hih-k Dielectrics EOT Control Thermal Stability Mobility & Threshold Voltae Trappin Induced Instability Counts (A.U.) crystallizes between 3 and 4ºC () nm 5 o C 4 o C 3 o C As-deposited Theta (deree) Thermal stability of hih-k ides Hf-aluminate films rown at RT by jet-vapor deposition (T.P.Ma, Yale U.) w. 6.8 at% Al As-deposited film: Low leakae and low EOT Amorphous Thin interfacial layer Broad ELNES Annealed film (7 C/N 2 ): Leaky, increased EOT Partially crystallized Thicker interfacial layer Narrower ELNES CCD Counts (a.u.) CCD Counts (a.u.) O K-ede p p 2 as-deposited Enery Loss (ev) O K-ede p p 2 p 3 annealed Enery Loss (ev) Challenes of Hih-k Dielectrics Deradation of Channel Mobility in Hih-k Gated MOSFETs EOT Control Thermal Stability Mobility & Threshold Voltae Trappin Induced Instability Mobility (cm 2 /V-s) 4 FG 4 C FG 5 C 3 FG 6 C Universal 2 NMOS W/L = 5/ µm EOT ~ 3 Å.5.5 Effective Field (MV/cm) Mobility (cm 2 /V-s) ON Universal No anneal FG anneal.5.5 Effective Field (MV/cm)

9 Common Errors in Measurin Hih-k Gated MOSFET Mobility Trappin causes overestimation of carriers and thus underestimation of mobility Hih ate leakae current that results in underestimation of mobility at hih fields Mobility of -Gated MOSFET -Effect of Trappin Mobility (cm 2 /V-s) With N it Correction nmosfet, W/L=2µm/5µm KHz 5 PDA temperature w/o N 7 o C it Correction 6 o C Q inv (µc/cm 2 ) Corrected curves are hiher Both show a peak, as predicted by scatterin theory Scatterin mechanisms Mobility of nmosfet with various ate dielectrics Mobility (cm 2 /V-s) nmosfet After N it correction Universal Mobility, 7 o C HfAlO, 7 o C, 6 o C HfAlO, 6 o C (a) Coulomb scatterin due to trapped chare in dielectrics (b) Coulomb scatterin due to ionized impurities in depletion layer (d) Surface rouhness scatterin (e) Phonon scatterin due to lattice vibration Effective Vertical Field (MV/cm) The mobility of nmosfet with are much hiher than the one of and HfAlO. The mobility of nmosfet with or HfAlO annealed at 7 o C are hiher than the one annealed at 6 o C The relation between mobility and interface trap density Remote Phonon Scatterin µ eff (cm 2 E eff =.MV/cm nmosfet, 7 o C HfAlO, 7 o C, 6 o C HfAlO, 6 o C D it from Swin (x 3 cm -2 ev - ) The hiher the interface trap density, the lower the effective mobility, indicatin that coulomb scatterin is one major deradation mechanism of these hih-k dielectrics

10 Temperature dependence of mobility µ eff (cm 2 /V-s) with Correction Universal Mobility, w/o Correction Effective Vertial Field (MV/cm) Temperature: 2K 6K 2K 24K 28K 32K Effective mobility for is lower than universal mobility even after interface correction. µ (cm 2 /V-s) Extraction of mobility limited by phonon scatterin 2 8 nmosfet, T=24K µ SR 6 4 µ ph µ coul 2 µ eff Effective Field (MV/cm) µ = ph µ eff µ coul µ sr The mobility limited by phonon is extracted accordin to Matthiessen s rule. Temp. dependence of mobility limited by phonon scatterin µ ph (cm 2 /V-s) nmosfet E eff =.65MV/cm E eff =.75MV/cm E eff =.85MV/cm Temperature (K) Mobility limited by phonon scatterin for sample is much lower than that for sample The difference between HfO2 and O2 is attributed to soft optical phonons in /µ ph (cm 2 /V-s) MV/cm.75MV/cm.65MV/cm difference between HfO. 2 and Temperature (K) The scatterin rate by the additional soft optical phonons in sample is a weak function of temperature, which is consistent with theoretical calculation. Scatterin Rate (x 3 s - ) The scatterin rate due to optical phonons: [ N R + ( N R + ) u( E ηω )] τ op Where N R = is phonon occupation number ηω / kt e u(x) is the unit step function. ) For ηω < E (2N τ 2) For op When ηω << kt ηω > kt τ op R x e + + ) = x e T τ op constant ηω where x = kt Challenes of Hih-k Dielectrics EOT Control Thermal Stability Mobility & Threshold Voltae Trappin Induced Instability

11 V base Drain current instability A. Kerber, E. Cartier et al., EDL 23 Chemical ide / 5 nm HfO 2 2 / N 2 PDA / poly ate Gate Voltae time Drain Current (µa) 5 up traces identical 5 V V Base =-.5V D =.V FET: x µm Gate Instability is unacceptably lare Vt-instability in scaled / stacks: Comparison to delta V T (V) O 3 clean, 3 nm, PDA: N 2 6 O C for min 4 nm, no PDA SC/SC2, 3 nm, 4 nm, 6 nm, no PDA Operatin 4.5nm condition Detection limit E _max (MV/cm) All / stacks studied show comparable instability Instability is much larer than for control Drain Current (µa) Pulsed and DC measurements O 2 3 clean, 4 nm, PDA: O 2 at 5 O C Pulsed: open symbols 5 DC: (up-trace) solid symbols delta V T FET: 5 W= µm L= µm V D =.V shifted up-trace Gate delta V T (V) Operatin condition V t instability due to charin is underestimated by DC measurements Charin is leakin out durin slow measurements For application, pulsed result more relevant. Pulsed DC E _max (MV/cm) Stress and sense measurements lo (Stress Time (s)) Lifetime Extraction Chare Trappin vs TDDB Trappin -year lifetime from trappin 8 nmosfet 6 V th =5mV B 4 TaN 2 V A OP =.4V poly -2 V OP =.63V V STRESS -V th (V) T 63 (s) TDDB 9 -year lifetime from TDDB 8 B 7 TaN nmosfet A V OP =2.9V 3 poly 2 V OP =2.4V V STRESS -V th (V) It is chare trappin rather than TDDB that limits device lifetime. Examples of Innovative Approaches Ultra Rapid Thermal Annealin Inelastic Electron Tunnelin Spectroscopy (IETS) MAD Examples of Innovative Approaches Ultra Rapid Thermal Annealin Inelastic Electron Tunnelin Spectroscopy (IETS) MAD

12 Atmospheric Hot Gas Annealin Concept - Wafer Holder o Non-Contact (usin hih-speed He as) o Controlled Scannin o Active, feedback coolin Inherent Advantaes for Hot Gas RTP Hot Gas Stream o ~7, de C o Inert as (He) o Lare heat flux rane o Hih stability / uniformity Wafer Heat transfer by as conduction, not surface toporaphy/material dependent Very Rapid Heatin Very Rapid Cool-down Temperture [derees C] Wafer Heatin & Coolin at 5x 7 W/m 2 for 3msec - GaAs Time [msec] Front surface Back surface Examples of Innovative Approaches Ultra Rapid Thermal Annealin Inelastic Electron Tunnelin Spectroscopy (IETS) MAD Inelastic Electron Tunnelin Spectroscopy An Inelastic Tunnelin Event at E=eV = hν Causes (a) I-V to increase slope; (b) a step in di/dv; (c) a peak in d 2 I/dV 2 Various Inelastic Modes in the Barrier (Left) May Be Reflected in IETS (Bottom Riht) I di/dv d 2 I/dV 2 Elastic Elastic Inelastic ev=hν d 2 I dv 2 Elastic Inelastic V IETS probes phonons, bondin vibrations, impurities, and Traps

13 IETS Spectrum of / Interactions Detectable by IETS Substrate licon Phonons Gate Electrode Phonons Dielectric Vibrations (Phonons) Impurity Bondin Vibrations Trap States G i [Arbitrary Units] mV Wave Number [cm - ] mV 53.6mV licon phonons licon phonons 59.4mV 63.4mV 55 6 modes modes Voltae Bias [Volts] 65 75x -3 IETS (Arbitrary Units) phonons and vibration modes phonons vibrations enter text here 5 65 W/O HF Vapor 2 enter text here With HF Vapor -F mode (a) (b) IETS (LA) (TA) (LO) (TO) W/O HF Vapor With HF Vapor (a) (b) mv: TA mode 44 mv: LA mode 53 mv: LO mode 59 mv: TO mode mv: LO mode (Rockin) 44 mv: AS mode (Asymmetric Stretch) 5 mv: AS2 mode (Asymmetric Stretch) 55 mv: LO3 mode (Symmetrric Stretch) 65 mv: P-O mode Voltae (mv) IETS can detect structure chanes caused by different processin conditions. (a) / without HF vapor pre idation cleanin (b) / with the HF vapor pre idation cleanin Voltae (mv) IETS of Thermal / and CVD 3 N 4 / IETS of Al/ / IETS (Arbitrary Units) 8.x - 4.x x - -8.x - -.2x -9 ( TA ) -F Donor ( LA ) ( LO ) ( TO ) ( LO ) 65 mv 78 mv -H 3 N 4 -N -H ( LO4 ) ( LO3 ) 3 N 4 Al/H fo 2 /S i 6 o C annealin in N 2 Monoclinic 33.7m v M onoclinic M onoclinic 9m v 53.3mv M onoclinic 7.m v Tetraonal 67.m v Monoclinic 2m v Al-O H f-o Posivite B ias(volt)

14 Theoretical (LDA and GGA) and experimental (Raman and IETS) of phonon modes in Remote Phonon Scatterin Modes (cm-) Monoclinic Bu Monoclinic A,B Monoclinic B Monoclinic A Monocli nic B Moniclin ic B Tetraon al LDA , GGA , Raman , IETS 27 (33.7mv) 4 (5mV) 572 (7mv) 725 (9mv) 822 (9mv) 637 (79mv) 536 (66.4mv) ---Xinyuan Zhao and David Vanderbit,, Physical Review B,vol. 65, 22 IETS (A.U.) IETS (A. U.) IETS nals for / Voltae (mv) IETS (A. U.) -Hf -Hf Voltae (mv) Lower enery peaks are and phonons; Hiher enery peaks are and O-Hf phonons Mobility Reduction due to Soft Phonon Scatterin Source e Gate Dielectric O2 HfO2 Bond strenth Stron bond Weak bond Optical phonon enery ( mev) 38 34, 48, 7 Rate of emission/absorption Low Hih phonon Static permittivity ε /εo Optical permittivity ε /εo Electron phonon couplin Low Hih strenth Mobility limited by remote phonon scatterin Hih Low Gate Dielectric p- Substrate Drain ated MOSFET miht have reduced mobility due to soft phonon scatterin. A) Phonon eneries close to kt at room temp. ε ε B) Scatterin strenth ( ε + ε )( ε + ε ) si [M. Fischetti, et.al, J. Appl. Phys.,Vol.9, p4587, 2] si IETS (A.U.) IETS sensitive to process variations for Al/ / structure ().4E-7.2E-7.E-7 8.E-8 6.E-8 4.E-8 2.E-8.E+ Post-deposition annealin: Furnace vs. RTA RTA Furnace anneal -2.E-8 ~5A HfO -4.E-8 2 6C N 2 2min ~25A 6C RTA N 2 2min -6.E Voltae (mv) IETS sensitive to process variations for Al/ / structure (2) Hf ~5Å N 2 6C 3mins ~Å N 2 6C 3mins + WV 6C 2mins Thermal Oxide Reference

15 IETS sensitive to process variations for Al/ / structure (3) peaks stroner with increasin PDA temperature Linked to more crystallization at hiher temperatures. IETS (A. U.).E-7 8.E-8 6.E-8 4.E-8 2.E-8.E+ 6C 5C 4C 3C Voltae Stress Induced Effect Features at.7v and.6v indicate trap assisted tunnelin. IETS (A.U.) Increasin Stress O riinal, Forw ard Bias After 2s 2.5 V Stress After 2s 2.5 V Stress After 6s 2.5 V Stress Trap or defect Assisted Tunnelin Al-O -Hf Trap or defect Assisted -2.E-8 ~25A RTA in N Voltae (mv) Voltae Stress Induced Effect (Reverse Bias) IETS (A.U.) Increasin Stress Oriinal, Reverse Bias After 2s 2.5 V Stress After 2s 2.5 V Stress After 6s 2.5 V Stress -Hf Trap Assisted Tunnelin Trap Related Effect from IETS I G i Trap Assisted Tunnelin Chare Trappin Backround I-V V Trap Assisted Tunnelin Chare Trappin V IETS Reveals Stress-Induced Traps Stron Trap Assisted Tunnelin Effect Revealed by IETS d 2 I/dV 2 (A.U.) After 8s.2V stress After 2s.2V stress Oriinal Increasin Stress Traps IETS (A. U.) / Stressed at.6v 8s Trap Trap IETS has hih sensitivity in detectin traps Forward-bias trap features are stroner than reversebias ones, due to asymmetry of the barrier.

16 Determinin Trap Enery and its Physical Location from Forward and Reverse IETS * x t V t * x ----By Wei,He x t is the physical location of the trap (assume total physical thickness is x ). ev t is the trap enery above the Fermi level (at zero bias). V f is the forward bias voltae required for the Fermi level to reach the trap. V r is the reverse bias voltae required for the Fermi level to reach the trap. Assume non-uniform dielectric constant: ε=ε(x). x V t = V f V r / (V f +V r ) where d d t = d V f / (V f +V r ) = dx/ε(x) d t = xt, dx/ε(x) V f Vr * Trap Enery and its Physical Location for a Particular Trap IETS (A. U.) / Stressed at.6v 8s Trap Trap The EOT of the dielectric is ~2.5 nm. V f =.58 V V b =.32 V V =.2 V d =.36 The trap is located ~.9 nm from the dielectric/ interface Conclusion Extensive R&D Efforts for Hih-k Gate Dielectrics Are Needed to Realize EOT << nm Low Gate Leakae Current Good Thermal Stability Desired V T for Both Channels Hih Drive Current and Transconducctance Good Reliability Worldwide IC Sales (C. Osburn)

17 N-Channel and P-Channel Transistors with < 2nm (EOT) of RTCVD licon Nitride as Gate Dielectric (a) (b) Fi. 2 Drain current characteristics of transistor with <2nm (EOT) of RTCVD silicon nitride as ate dielectric: (a) NMOSFET, (b) OMOSFET [2]. Son, et al., IEDM Technical Diest, Dec. 998 (Adapted from Mobility measurement E. Garfunkel) Effective mobility: µ eff = Conventional Q L w inv = d C I ( V ) d V Q Inversion chare density: inv ( V ) (V - V ) T Split CV: inv V = Q C ( V ) dv c C c is not step function of V at V T => need split CV Standard split CV method is inadequate for hih-k dielectrics with hih N it Problem. N it can respond to ac sinal C ( Cinv + Cit ) C c= C + C + C + C dv = ( dq + dq ) / C inv Problem 2. N it can respond to dc sinal inv D Solution: Hiher frequency for split CV Solution? it trap C c V Eit C Cit Cinv CD Ec EF Ev Gate Dielectric substrate N it response to ac sinal N it response to DC sinal Ideal V C c /Area (x -8 F/cm 2 ) I d (µa) Mobility from Split CV -Interface trap correction for mobility extraction V (V) Q inv (µc/cm 2 ) Ideal Ideal 5 w/o N w/o N it it V V 2 Measured With N it (a) µ Q Q 2 Measured With N it With N it Correction C c /Area (x -8 F/cm 2 ) 5 (b) 3 µ 2 5 W/O N it Correction (c) (d) V (V) Q inv (µc/cm 2 ) Q, not Q 2, should be used for mobility extraction 2 Effective Mobility µ eff (cm 2 /V-s) µ = eff L w I ( V ) d d V Q inv ( V )

18 Mobility from Split CV (cont d) -Interface trap correction for mobility measurement At hih frequencies, ate-channel capacitance CCinv C c= C + C + C inv D dqinv Cinv = C C inv where dψ s C D is the same with or w/o interface traps Gate Dielectric for the same Q inv At same C c, Q extracted from ideal C c and Q 2 from measured C c contain the same amount of mobile inversion chare, while Q 2 contains extra interface trapped chare V E it E c E F E v substrate Mobility of -Gated MOSFET -Effect of Interface Traps Mobility (cm 2 /V-s) With N it Correction nmosfet, W/L=2µm/5µm KHz 5 PDA temperature w/o N 7 o C it Correction 6 o C Q inv (µc/cm 2 ) Corrected curves are hiher Both show a peak, as predicted by scatterin theory Difference between interface traps causes mobility underestimation and mobility deradation Hall Mobility vs Effective Mobility from split CV µ Hall Source Gate Dielectric e 2 p- Substrate Drain : Chare trappin causes carrier loss and mobility underestimation 2: Trapped chare causes Coulomb scatterin and mobility deradation Mobility (cm 2 /V-s) µ eff µ eff-correction µ µ Hall eff-no-correction nmosfet, poly ate Q inv (x -6 C/cm 2 ) Normalized Inversion Chare Density Electrical Stress Alters the Modes But Leaves the Phonons Unchaned.7 Q inv /C inv (V) split CV w/o correction Hall effect.2 split CV. with correction V -V T (V) phonons Increasin Stress modes

19 IETS can detect chanes caused by elctrical stress IETS reveals chanes in / interface after AC stress. Possible explanation is that AC stress breaks weak bonds and cause positive chares at the interface. The positive chares will modify the bondin structure for O2 near the interface. A:Initial; B-D:After 3, 4, 5 sec +.5V khz square wave stress; E:After 3 sec +2V us khz pulses; F: After 3 sec -2V us khz pulses. Increasin AC Stress Bias Polarity Dependence Electrons have hiher probability to interact with a vibration located near the positively biased electrode. Bias Polarity Dependence of IETS for Al/ / Results suest sinificantly different microstructures near Al- interface and - interface. / interface is more -like. /Al interface is more -like. 8.E- 6.E- ~5A JVD on, annealed in N 2 6C 3min 4.E- 2.E- -Hf IETS (A.U.).E+ -2.E- -4.E- Forward Bias -6.E- -8.E- Reverse Bias -.E Voltae (mv)