Intrinsic Reliability Projections for a Thin JVD Silicon Nitride Gate Dielectric in P-MOSFET

Transcription

1 4 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 1, MARCH 2001 Intrinsic Reliability Projections for a Thin JVD Silicon Nitride Gate Dielectric in P-MOSFET Igor Polishchuk, Student Member, IEEE, Qiang Lu, Student Member, IEEE, Yee-Chia Yeo, Student Member, IEEE, Tsu-Jae King, Member, IEEE, and Chenming Hu, Fellow, IEEE Abstract A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si 3 N 4 gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As the result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si 3 N 4 gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability. Index Terms Dielectric wearout, JVD silicon nitride, lifetime projections, stress-induced leakage current, trap generation. I. INTRODUCTION THE equivalent oxide thickness of the gate dielectric in CMOS integrated circuits is expected to scale below 1.5 nm by the year 2004 [1]. The use of SiO thinner than 1.5 nm will not be feasible for some applications due to the high dielectric leakage current. The reliability requirements for the gate dielectric may impose an even stricter limit on the oxide scaling [2]. Several materials with higher dielectric constants are being investigated as possible replacements for SiO. High- materials such as Ta, Hf, and Zr oxides have recently attracted a lot of attention [3] [5]. However, the instability of these materials during high-temperature processing steps remains a major challenge. Silicon nitride, on the other hand, can be easily integrated into CMOS processes and is likely to become the first material to be used as an alternative gate dielectric. Transistors with nitride gate dielectrics as thin as 1.4 nm (equivalent oxide thickness) and a channel length of 80 nm have been successfully fabricated [6]. Good performance of these devices has been reported. However, it is still necessary to demonstrate good reliability of these devices before Si N can be confidently put forward as a replacement for SiO in the gate stack. Gate nitride reliability research has so far been primarily focused on examining the time-dependent dielectric breakdown (TDDB) [7], [8]. A comprehensive TDDB study with area and Manuscript received February 20, 2001; revised March 8, This work was supported by the Semiconductor Research Corporation under Contract SRC , and in part by SRC/Sematech through the FEP Center. The work of I. Polishchuk was supported in part by NIST and SRC. The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA USA ( igorp@eecs.berkeley.edu). Publisher Item Identifier S (01) fractional scaling for silicon nitride has yet to be conducted. Nevertheless, long lifetime and high breakdown field for thin nitride dielectrics have been reported, thus indicating that hard dielectric breakdown might not present a serious concern for the reliability of the thin nitrides. It has also been noted that the reliability of the thin oxides is limited not by the TDDB but by the the time-dependent dielectric wearout (TDDW) effects, such as gradual increase in the gate leakage current [9], [10]. One can expect that TDDW will also play a significant role in thin nitrides as well. This illustrates the need to investigate possible TDDW effects, such as stress-induced leakage current (SILC), shift, mobility, and subthreshold swing degradation for Si N. It has been observed that the degradation of the SiO transistor characteristic due to both hot-electron stress [11] and Fowler Nordheim stress (FN-stress) [12] typically follows a power-law dependence on time. In this paper, we found that the degradation in the gate leakage current, threshold voltage, subthreshold swing, and mobility in the transistors with jet vapor deposited (JVD) nitride follows the same kind of power-law dependence. Moreover, we propose a set of empirical models that describe the dependence of the device degradation rate on the FN-stress voltage. These models can be used to make extrapolations of dielectric wearout over a 10-year period under low operating voltages. II. EXPERIMENT The devices were fabricated by a LOCOS dual-poly CMOS process at UC Berkeley. The gate nitride was formed by jet vapor deposition [13] followed by an 800 C 5 min anneal in the ambient at Yale University. Results of the Auger depth profile analysis [13] show that the composition of the deposited film is uniform, without a distinct oxygen-rich interfacial layer. The relative atomic concentrations of Si, N, and O in the film are equal to 41%, 46%, and 13%, respectively. These numbers indicate that all the Si bonds are satisfied by either N or O, with 84% of those bonds being satisfied by the nitrogen atoms. While JVD material at hand is not technically a stoichiometric Si N, its low oxygen content clearly sets it aside from a class of gate dielectrics known as oxynitrides. Keeping this caveat in mind, we shall hereafter refer to the dielectric material as nitride or Si N. A quantum simulator [14] was used to extract the equivalent oxide thickness of 1.4 nm and the substrate doping concentration of cm from the C V characteristic. The threshold voltage of long-channel P-MOSFETs is 0.45 V, which coincides with the value for an 80-nm gate-length device reported in [6] /01$ IEEE

2 POLISHCHUK et al.: INTRINSIC RELIABILITY PROJECTIONS FOR A THIN JVD SILICON NITRIDE GATE DIELECTRIC 5 (a) Fig. 1. Gate current evolution under constant-voltage stress. Stress voltages vary from 02:7 Vto04V. The total charge fluence for each of the devices is indicated on the right-hand side. Even though the leakage current increases under higher gate bias stress, no hard dielectric breakdown is detected. Constant voltage FN-stress has been used in this study to predict the reliability of the gate nitride under low operating voltages. A stress voltage ranging from 2.7to 4 V was applied to the gate of m m p-mosfets, with the source, drain, and substrate grounded. This type of stressing should result in the realistic predictions of the gate dielectric reliability. This is because transistors in the integrated circuits are subjected to constant voltage stress rather than constant current stress and are typically biased into inversion rather than accumulation. The substrate series resistance is approximately 1 k and does not affect the results of the stress measurement as long as the magnitude of the stress voltage remains below 4 V. (The stress current at Vis50 A which corresponds to a 50-mV voltage drop across this series resistance.) Constant voltage stress was interrupted from time to time to allow the monitoring of the changes in the gate leakage current, threshold voltage, subthreshold swing, and transconductance as functions of stress time. Stress-induced leakage current (SILC) is defined here as the difference between the values of for a stressed and a fresh transistor. The value of SILC at V was used to quantify the increase in gate leakage current. The values of,, and were obtained from the drain current versus gate voltage characteristics taken at a low drain bias mv. Transconductance values measured at V were used to monitor the deterioration of the low field mobility due to stress-generated interface traps. (b) (c) Fig. 2. Comparison between (a) gate leakage current, (b) transconductance, and (c) I V characteristics for fresh and stressed transistors. III. RESULTS While it is not the purpose of this paper to determine the exact time to breakdown, we considered it necessary to present a limited amount of data to illustrate the behavior of the gate dielectric under FN-stress. Fig. 1 shows the evolution of the gate leakage current under constant-voltage stress. Stress at low gate biases of 2.7 V and 3 V leads to a very modest increase in the gate current known as SILC. Stress at higher gate biases of 3.3 V and 3.6 V leads to a more dramatic increase in the gate leakage current, sometimes referred to as soft breakdown. In practice, however, we do not detect any abrupt changes in Fig. 3. Changes in I, g, S, and V all follow the same t dependence on stress time for a wide range of stress voltages. the dielectric conductance and therefore are not able to distinguish clearly between SILC and soft breakdown. Furthermore,

3 6 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 1, MARCH 2001 (a) (b) (c) (d) Fig. 4. Equation (1) provides good fit for (a) 1V, (b) 1g, (c) 1S, and (d) 1I as functions of stress time for various stress voltages. we have not observed a hard dielectric breakdown, characterized by an abrupt jump in conduction by a few orders of magnitude, in any of the samples stressed at gate biases as high as 4V. The bottom curve in Fig. 1 shows no appreciable increase in the gate leakage current at 2.7 V for a total stress-charge fluence of C/cm. Now we shall turn to the main subject of this paper a study the degradation in MOSFET parameters under constant-voltage FN-stress. Fig. 2 shows that the gate leakage current,, and all increase and decreases as the result of FN-stress. While the circuits are not expected to fail due to the gate nitride breakdown, the degradation in the device performance needs to be addressed. The degradation of the aforementioned parameters is commonly attributed to the creation of various types of traps in the gate dielectric. Thus, one might expect the changes in one of the parameters to be correlated to the changes in the other parameters. The changes in,,, and do indeed follow the same power-law dependence as shown in Fig. 3. Furthermore, the same power-law dependence applies to the results obtained under both high ( 3.6 V) and low ( 2.7 V) stress voltages. This observation suggests that the following empirical model can be put forward. It would predict the degradation in MOSFET parameters at a low operating voltage as a function of time Fig. 5. s vary exponentially with the stress voltage. the stress voltage. The proposed model provides a good fit to the experimental data for,,, and [Fig. 4(a) (d)]. The values of the are extracted from Fig. 4 and plotted in Fig. 5 as functions of the stress voltage. Each of the s depends exponentially on the stress voltage [11], [12] mv Here denotes a MOSFET parameter (such as, for example). is observed in Fig. 3, the factor depends on the stress voltage, and denotes the absolute value of (1) mv dec (2)

4 POLISHCHUK et al.: INTRINSIC RELIABILITY PROJECTIONS FOR A THIN JVD SILICON NITRIDE GATE DIELECTRIC 7 In these expressions, the stress voltage is measured in volts. The changes in the threshold voltage, transconductance, and subthreshold swing all have similar dependence on the stress voltage. This similarity can be attributed to the fact that the build-up of the interface traps is primarily responsible for the deterioration of these three parameters. In contrast, the changes in the gate leakage current have a different stress voltage dependence, because a different type of traps (bulk traps in this case) is primarily responsible for the increase in the gate leakage. The International Technology Roadmap for Semiconductors predicts that, by the year 2004, when the equivalent oxide thickness of the dielectric will scale to below 1.5 nm, the circuit supply voltage will be between 0.9 and 1.2 V depending on the application. Clearly, the higher supply voltage imposes a stricter limit on the reliability. V and sec (10 years) were used to project the degradation of the JVD nitride transistors. The results are summarized in Table I. The increase in the gate leakage current becomes negligible at low operating voltages due to the strong voltage dependence of as seen in (2). The deterioration in other parameters might, to a degree, affect the device performance, but will remain well within the acceptable boundaries. IV. DISCUSSION The TDDW model for Si N presented in this paper resembles the TDDW model for SiO proposed earlier by Qian and Dumin [15], which predicts that the number of traps generated by FN-stress follows an exponential dependence on the applied electric field and a power-law dependence on the stress time. Exponential dependence of trap generation rate on voltage can be explained by either a thermochemical reaction [16] or a voltage-driven process taking place in a dielectric [17], [18]. Similar mechanisms are perhaps responsible for trap generation in SiO and Si N. The origins of power-law dependence on time are uncertain. The hydrogen-atom diffusion model [19] has been proposed to explain the power-law dependence with. However, a range of values of from 0.2 to 0.75 has been observed. Instead, a simple statistical model could explain the power-law dependence of defect generation. 1 1 Suppose there is a certain number, N, of weak (strained) bonds in the dielectric layer and these bonds are broken under a constant voltage stress with a time constant. Then the number of defects generated over time t is 1N = N (1 0 e ). In this basic model, the number of traps generated is a linear function of time for t and saturates for t. In reality, however, various traps are likely to have different time constants. Although there is currently no clear physical evidence for any particular mechanism responsible for these different time constants, we believe that a number of mechanisms could be responsible. For example, the variations in the trap position within the dielectric and/or the fact that different bonds can be strained to different degrees might give rise to different time constants. Interestingly enough, regardless of what this distribution is, the number of traps generated is a power-law (or nearly a power-law) function of time. If one assumes a power-law distribution of, for example, (i.e., the number of weak bonds with time constants between and + d is K d ), it can be easily shown, by integration over all s that the number of traps generated will also have a power-law dependence on time as 1N = K 1 0 e d = 00(010 n)kt where 0 is the gamma function. In our case, n +1=0:3, and 0(00:3) is a negative number, so the right-hand side of equation is positive. TABLE I PROJECTED CHANGES IN THE MOSFET PARAMETERS OVER A 10-YEAR DEVICE LIFETIME UNDER AN OPERATING VOLTAGE OF 1.2 V V. CONCLUSION The intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD gate nitride has been investigated. It has been confirmed that thin JVD nitride is not susceptible to hard dielectric breakdown at low operating voltages. At the same time, a drift in MOSFET performance due to the FN-stress has been observed. A model that describes the degradation of the MOSFET parameters as a function of time and stress voltage has been proposed. This model allows the prediction of the device degradation operating under a low supply voltage over a long period of time. According to these projections, the degradation of the device performance remains well within the allowed range. Thus, from the reliability perspective, JVD nitride is a viable successor to SiO as the transistor gate dielectric. ACKNOWLEDGMENT Devices were fabricated at the Microfabrication Laboratory at the University of California, Berkeley. The authors also acknowledge X. Wang, X. Guo, and Prof. T.-P. Ma from Yale University for JVD film deposition. REFERENCES [1] The International Technology Roadmap for Semiconductors, Semiconductor Industry Association, [2] J. H. Stathis and D. J. DiMaria, Reliability projection for ultrathin oxides at low voltages, in IEDM Tech. Dig., 1998, pp [3] B. H. Lee et al., Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application, in IEDM Tech. Dig., 1999, pp [4] H. F. Luan et al., High quality Ta O gate dielectric with T < 10A A, in IEDM Tech. Dig., 1999, pp [5] W.-J. Qi et al., MOSCAP and MOSFET characteristics using ZrO gate dielectric deposited directly on Si, in IEDM Tech. Dig., 1999, pp [6] Q. Lu et al., Comparison of 14Å T JVD and RTCVD silicon nitride gate dielectrics for sub-100 nm MOSFET s, in Int. Semiconductor Device Research Symp., 1999, pp [7] M. Khare, X. W. Wang, and T. P. Ma, Highly robust ultrathin gate dielectric for giga scale technology, in Symp. VLSI Tech. Dig. Papers, 1998, pp [8] K. Sekine et al., Highly-integrity ultrathin silicon nitride film grown at low temperature for extending scaling limit of gate dielectric, in IEDM Tech Dig., 1999, pp [9] Y. Wu, X. Qi, D. Bang, G. Lucovsky, and M.-R. Lin, Time dependent dielectric wearout (TDDW) technique for reliability of ultrathin gate oxides, IEEE Trans. Electron Devices, vol. 20, pp , June [10] C.-Y. Chang et al., Reliability of ultrathin gate oxides for ULSI devices, Microelectron. Reliab., vol. 39, pp , [11] C. Hu et al., Hot-electron-induced MOSFET degradation model monitor, and improvement, IEEE Electron Device Lett., vol. ED-32, pp , [12] K. Okada, H. Kubo, A. Ishinaga, and K. Yoneda, A new prediction method for oxide lifetime and its application to study dielectric breakdown, in IEDM Tech. Dig., 1998, pp

5 8 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 1, NO. 1, MARCH 2001 [13] T. P. Ma, Making silicon nitride film a viable gate dielectric, IEEE Trans. Electron Devices, vol. 45, pp , Mar [14] [Online]. Available: [15] D. Qian and D. J. Dumin, A comprehensive physical model of oxide wearout and breakdown involving trap generation, charging, and discharging, in IEEE Int. Integrated Reliability Workshop Final Report, Lake Tahoe, CA, USA, Oct , 1998, pp [16] J. W. McPherson, V. K. Reddy, and H. C. Mogul, Field-enhanced Si Si bond-breakage mechanism for time-dependent dielectric breakdown in thin-film SiO2 dielectrics, Appl. Phys. Lett., vol. 71, pp , [17] P. E. Nicollian, W. R. Hunter, and J. C. Hu, Experimental evidence for voltage driven breakdown models in ultrathin gate oxides, in Int. Reliability Phys. Symp., 2000, p. 7. [18] M. A. Alam, J. Bude, and A. Ghetti, Field acceleration for oxide breakdown Can an accuate anode hole injection model resolve the E and 1/E controversy?, in Int. Reliability Phys. Symp., 2000, p. 21. [19] D. Arnold, E. Cartier, and D. J. DiMaria, Theory of high-field electron transport and impact ionization in silicon dioxide, Phys. Rev. B, vol. 49, no. 15, pp , Apr Tsu-Jae King (S 89 M 91) received the B.S., M.S., and Ph.D. degrees in electrical engineerin from Stanford University, Stanford, CA. At Stanford, her research involved the seminal study of polycrystalline silicon-germaniom films and their applications in MOS technologies. She joined the Xerox Palo Alto Research Center, Palo Alto, CA, as a Member of Research Staff in 1992 to research and develop polycrystalline silixon thin-film transistor technologies for high-performance display and imaging applications. She joined the faculty at the University of California, Berkeley, in August 1996 where she is presently an Associate Professor of Electrical Engineering and Computer Sciences, and the Faculty Director of the UC Berkeley Microfabrication Laboratory. Her research activities are in sub-100-nm MOS devices and technology and thin-film materials and devices for integrated microsystems and large-area electronics. she has authored or co-authored over 100 papers and holds 4 U.S. patents. Dr. King is a member of the Electrochemical Society, the Materials Research Society, and the Society for Information Display. She has served on committees for many technical conferences including the Device Research Conference, the International Conference on Solid State Devices and Materials, and the International Electron Devices Meeting. Igor Polishchuk (S 98) received the B.Sc. degree in physics from the California Institute of Technology, Pasadena, in 1997 and the M.S. degree in electrical engineering from the University of California, Berkeley, in He is currently working toward the Ph.D. degree at the University of California, Berkeley. His research interests include reliability of ultrathin gate oxides and high-k dielectrics, metal gate technology, and carrier transport modeling in MOS devices. Mr. Polishchuk received the California Fellowship in Microelectronics in 1997 and currently holds the SRC/NIST Graduate Fellowship. Qiang Lu (S 01) received the B.S. degree in physics from Peking University, China, in He is currently a graduate student with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. His research interests include high-k dielectrics and metal gate materials for MOS devices and oxide reliability. Yee-Chia Yeo (S 98) received the B.Eng. degree with first class honors and the M.Eng. degree from the National University of Singapore (NUS), both in electrical engineering. He is currently working toward the Ph.D. degree in electrical engineering at the University of California, Berkeley. He has worked on the characterization of lasers for low-cost optoelectronics at the British Telecommunications Laboratories, Ipswich, U.K., and also on the study of GaN-based quantum-well lasers at NUS. His research interests include MOS device physics, sub-100-nm device fabrication, strained SiGechannel MOSFETS, metal gates, and advanced gate dielectrics M. Yeo was awarded the 1995 IEE Prize, the 1996 Lee Kuan Yew Gold Medal, and the 1996 Institution of Engineers, Singapore (IES) Gold Medal for being the best undergraduate in electrical engineering at NUS. He is also the recipient of the Overseas Graduate Scholarship from NUS. Chenming Hu (S 71 M 76 SM 83 F 90) received the B.S. degree from Taiwan University in 1968 and the M.S. and Ph.D. degrees from the University of California, Berkeley. He is the TSMC Distinguished Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley. His research areas include microelectronic devices and technology and device modeling for circuit simulation. He has authored or co-authored five books and over 600 research papers. Prof. Hu is a member of the National Academy of Engineering, a fellow of the Institute of Physics, an honorary professor of the Chinese Academy of Science, and an Adjunct Professor of Peking University. He leads the development of the MOSFET model BSIM3v3, the industry standard model for IC simulation and the recipient of an R&D 100 Award. He received the 1997 Jack A. Morton Award for contributions to the physics of MOSFET reliability. He has received the University of California at Berkeley s highest honor for teaching, the Distinguished Teaching Award, the Monie A. Ferst Award of Sigma Xi, the W. Y. Pan Foundation Award, the National Technology University Outstanding Teaching Award, and DARPA Most Significant Technological Accomplishment Award for codeveloping the FinFET transistor structure. He is a member of the editorial boards of the Journal of Semiconductor Science and Technology and of the Journal of Microelectronics Reliability.