EE194-EE290C. 28 nm SoC for IoT

Transcription

1 EE194-EE290C 28 nm SoC for IoT Ref: Communic:on Systems y A. Bruce Crlson, Pul B. Crilly nd Jnet C. Rutledge CMOS VLSI Design y Neil H. Weste nd Dvid Money Hrris Timing Lirry Formt Reference, Cdence Design System hsps:// Synopsys Design Compiler User Guide

2 Bit Synchroniz:on Crrier Frequency nd Phse Frme Synchroniz:on Synchroniz:on

3 Synchroniz:on PN sequence genertor. m 1 m 2 m 3 m 4 m Output sequence

4 Synchroniz:on Autocorrel:on of PN sequence. R s (τ) 1 -T c T c (N-1)T c (N+1)T c 1/N NT c τ

5 Synchroniz:on Frme Synchroniz:on Premle Strt of messge Messge its t

6 Synchroniz:on Frme Synchroniz:on/Premle Detec:on... K K-1 K-2 K-N... c 1 c 2 c n Σ V K N v k = c i k i i=1

7 Mtl Exmple openexmple('comm/msksignlrecoveryexmple') MSKSignlRecoveryExmple

8 Trnsmission Gte Mux q Nonrestoring mux uses two trnsmission gtes - Only 4 trnsistors S D0 D1 S Y S

9 D Ltch q When CLK = 1, ltch is trnsprent - D flows through to Q like uffer q When CLK = 0, the ltch is opque - Q holds its old vlue independent of D q.k.. trnsprent ltch or level-sensitive ltch CLK CLK D Ltch Q D Q

10 D Ltch Design q Multiplexer chooses D or old Q D CLK 1 0 Q Q D CLK CLK CLK Q Q CLK

11 D Ltch Oper:on Q Q D Q D Q CLK = 1 CLK = 0 CLK D Q

12 D Flip-flop q When CLK rises, D is copied to Q q At ll other times, Q holds its vlue q.k.. positive edge-triggered flip-flop, mster-slve flip-flop CLK CLK D D Flop Q Q

13 D Flip-flop Design q Built from mster nd slve D ltches CLK D CLK QM CLK Q CLK CLK CLK CLK CLK D Ltch QM Ltch Q CLK CLK

14 D Flip-flop Oper:on D QM Q CLK = 0 D QM Q CLK = 1 CLK D Q

15 Rce Condi:on q Bck-to-ck flops cn mlfunction from clock skew - Second flip-flop fires lte - Sees first flip-flop chnge nd cptures its result - Clled hold-time filure or rce condition CLK1 CLK1 CLK2 CLK2 D Flop Q1 Flop Q2 Q1 Q2

16 Setup nd Hold Time Voltge Clock Setup Time Hold Time Time

17 Non-overlpping Clocks q Non-overlpping clocks cn prevent rces - As long s non-overlp exceeds clock skew q We will use them in this clss for sfe design - Industry mnges skew more crefully insted φ 2 φ 1 D QM Q φ 2 φ 2 φ 1 φ 1 φ 2 φ 1 φ 1 φ 2

18 Scn In Cell scn_in chip_in _int phi phi scn_i0o1 0 1 scn_i0o1 lod phi phi_out phi_out D Q D Q phi scn_i0o1_out lod_out scn_out _int scn_out scn_out_int lod D Q chip_in_int chip_in

19 Scn Out Cell phi phi scn_i0o1 lod phi_out phi_out scn_i0o1_out lod_out scn_in 0 chip_out 1 phi scn_i0o1 D Q D Q phi scn_out

20 Scn In-Out Cell phi phi scn_i0o1 lod scn_in 0 chip_out 1 phi scn_i0o1 phi_out phi_out D Q D Q phi scn_i0o1_out lod_out scn_out _int scn_out scn_out_int lod D Q chip_in_int chip_in

21 Gte Lyout q Lyout cn e very time consuming - Design gtes to fit together nicely - Build lirry of stndrd cells q Stndrd cell design methodology - V DD nd GND should ut (stndrd height) - Adjcent gtes should stisfy design rules - nmos t ottom nd pmos t top - All gtes include well nd sustrte contcts

22 q Uniform cell height q Uniform well height q M1 V DD nd GND rils q M2 Access to I/Os q Well / sustrte tps q Exploits regulrity Stndrd Cells

23 Coping With Complexity q How to design System-on-Chip? - Mny millions (even illions!) of trnsistors - Tens to hundreds of engineers q Structured Design q Design Prtitioning

24 Structured Design q Hierrchy: Divide nd Conquer - Recursively system into modules q Regulrity - Reuse modules wherever possile - Ex: Stndrd cell lirry q Modulrity: well-formed interfces - Allows modules to e treted s lck oxes q Loclity - Physicl nd temporl

25 Design Pr::oning q Architecture: User s perspective, wht does it do? - Instruction set, registers - MIPS, x86, Alph, PIC, ARM, q Microrchitecture - Single cycle, multi-cycle, pipelined, supersclr? q Logic: how re functionl locks constructed - Ripple crry, crry look-hed, crry select dders q Circuit: how re trnsistors used - Complementry CMOS, pss trnsistors, domino q Physicl: chip lyout - Dtpths, memories, rndom logic

26 HDL q Hrdwre Description Lnguges - Widely used in logic design - Verilog nd VHDL q Descrie hrdwre using code - Document logic functions - Simulte logic efore uilding - Synthesize code into gtes nd lyout Requires lirry of stndrd cells

27 Verilog Exmple module fulldder(input,, c, output s, cout); c sum s1(,, c, s); crry c1(,, c, cout); endmodule cout s c fulldder crry sum module crry(input,, c, output cout) cout s ssign cout = (&) (&c) (&c); endmodule

28 Circuit Design q How should logic e implemented? - NANDs nd NORs vs. ANDs nd ORs? - Fn-in nd fn-out? - How wide should trnsistors e? q These choices ffect speed, re, power q Logic synthesis mkes these choices for you - Good enough for mny pplictions - Hnd-crfted circuits re still etter

29 Exmple: Crry Logic q ssign cout = (&) (&c) (&c); c c g1 g2 g3 x y z g4 cout p1 c c n1 p3 n3 p2 i3 i1 n2 p4 i4 p5 cn n5 i2 n4 p6 n6 cout Trnsistors? Gte Delys?

30 Gte Level Netlist module crry(input,, c, output cout) wire x, y, z; nd g1(x,, ); nd g2(y,, c); nd g3(z,, c); or g4(cout, x, y, z); endmodule c c g1 g2 g3 x y z g4 cout

31 Trnsistor Level Netlist module crry(input,, c, output cout) wire i1, i2, i3, i4, cn; trnif1 n1(i1, 0, ); trnif1 n2(i1, 0, ); trnif1 n3(cn, i1, c); trnif1 n4(i2, 0, ); trnif1 n5(cn, i2, ); trnif0 p1(i3, 1, ); trnif0 p2(i3, 1, ); trnif0 p3(cn, i3, c); trnif0 p4(i4, 1, ); trnif0 p5(cn, i4, ); trnif1 n6(cout, 0, cn); trnif0 p6(cout, 1, cn); endmodule p1 c c n1 p3 n3 p2 i3 i1 n2 p4 i4 p5 cn n5 i2 n4 p6 n6 cout

32 SPICE Netlist.SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF.ENDS

33 q Floorpln q Stndrd cells - Plce & route q Dtpths - Slice plnning q Are estimtion Physicl Design

34 MIPS Floorpln

35 MIPS Lyout

36 Synthesized Controller q Synthesize HDL into gte-level netlist q Plce & Route using stndrd cell lirry

37 Design Verific:on q Friction is slow & expensive q Deugging chips is very hrd - Limited visiility into opertion q Prove design is right efore uilding! - Logic simultion - Ckt. simultion / forml verifiction - Lyout vs. schemtic comprison - Design & electricl rule checks q Verifiction is > 50% of effort on most chips! Specifiction Architecture Design Logic Design = = Function Function = Function Circuit Design = Function Timing Power Physicl Design

38 VLSI Flow q Design Compiler (DC) Synopsys tool Design Compiler op:mizes designs to provide the smllest nd fstest logicl represent:on of given func:on. It comprises tools tht synthesize your HDL descrip:ons into op:mized, technology-dependent, gte-level designs.

39 Fric:on & Pckging q Tpeout finl lyout q Friction - 6, 8, 12 wfers - Optimized for throughput, - not ltency (10 weeks!) - Cut into individul dice q Pckging - Bond gold wires from die I/O pds to pckge

40 Tes:ng q Test tht chip opertes - Design errors - Mnufcturing errors q A single dust prticle or wfer defect kills die - Yields from 90% to < 10% - Depends on die size, mturity of process - Test ech prt efore shipping to customer

41 MIPS R3000 Processor q 32-it 2 nd genertion commercil processor (1988) q Led y John Hennessy (Stnford, MIPS Founder) q KB Cches q 1.2 µm process q 111K Trnsistors q Up to MHz q 66 mm 2 die q 145 I/O Pins q V DD = 5 V q 4 Wtts q SGI Worksttions

42 Trnsistor s Switches q We cn view MOS trnsistors s electriclly controlled switches q Voltge t gte controls pth from source to drin g = 0 g = 1 nmos g d s d s OFF d s ON pmos g d s d s ON d s OFF

43 CMOS Inverter A Y 0 1 V DD 1 0 A Y A Y GND

44 CMOS NAND Gte A B Y Y A B

45 CMOS NOR Gte A B Y A B Y

46 Complementry CMOS q Complementry CMOS logic gtes - nmos pull-down network - pmos pull-up network -.k.. sttic CMOS pmos pull-up network inputs output Pull-up OFF Pull-down OFF Z (flot) 1 Pull-up ON nmos pull-down network Pull-down ON 0 X (crowr)

47 Series nd Prllel q nmos: 1 = ON q pmos: 0 = ON q Series: oth must e ON q Prllel: either cn e ON () g1 g OFF OFF OFF ON g g () ON OFF OFF OFF g1 g (c) OFF ON ON ON g1 g (d) ON ON ON OFF

48 Conduc:on Complement q Complementry CMOS gtes lwys produce 0 or 1 q Ex: NAND gte - Series nmos: Y=0 when oth inputs re 1 - Thus Y=1 when either input is 0 - Requires prllel pmos q Rule of Conduction Complements - Pull-up network is complement of pull-down - Prllel -> series, series -> prllel A B Y

49 Signl Strength q Strength of signl - How close it pproximtes idel voltge source q V DD nd GND rils re strongest 1 nd 0 q nmos pss strong 0 - But degrded or wek 1 q pmos pss strong 1 - But degrded or wek 0 q Thus nmos re est for pull-down network

50 Pss Trnsistors q Trnsistors cn e used s switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degrded 1 g s g = 0 d Input g = 0 Output 0 degrded 0 s d s g = 1 d 1 g = 0 strong 1

51 Trnsmission Gtes q Pss trnsistors produce degrded outputs q Trnsmission gtes pss oth 0 nd 1 well g g g = 0, g = 1 g = 1, g = 0 Input Output g = 1, g = 0 0 strong 0 g = 1, g = 0 1 strong 1 g g g g g g

52 Tristtes q Tristte uffer produces Z when not enled EN A Y 0 0 Z 0 1 Z A EN Y A EN Y EN

53 Non-restoring Tristte q Trnsmission gte cts s tristte uffer - Only two trnsistors - But non-restoring Noise on A is pssed on to Y EN A Y EN

54 Tristte Inverter q Tristte inverter produces restored output - Violtes conduction complement rule - Becuse we wnt Z output A A A EN EN Y Y Y EN = 0 Y = 'Z' EN = 1 Y = A

55 Mul:plexers q 2:1 multiplexer chooses etween two inputs S D1 D0 Y S 0 X X X 0 D0 D1 0 1 Y 1 1 X 1

56 Gte-Level Mux Design q How mny trnsistors re needed? 20 Y = SD + SD 1 0 (too mny trnsistors)