Degrading Precision Arithmetic for Low Power Signal Processing

Transcription

1 Degrding Precision Arithmetic for Low Power Signl Processing Mssimo Petricc, Gin Crlo Crdrilli, Alberto Nnnrelli (1), Mrco Re nd Pietro Albicocco Deprtment of Electronics, University of Rome Tor ergt, Rome, Itly (1) DTU Informtics, Technicl University of Denmrk, Kongens Lyngby, Denmrk Abstrct Sometimes reducing the power dissiption of resource constrined electronic systems, such s those built for deep-spce probes or for werble devices is top priority. In signl processing, it is possible to hve n cceptble qulity of the signl even introducing some errors. In this work, we nlyze two methods to degrde the precision of rithmetic opertions in DSP to sve power. The first method is bsed on disbling the lower (lest-significnt) portion of the dtpth by clock-gting nd forcing zeros. The second method is bsed on lowering the supply voltge nd re-designing the crry-chins in the dtpth to dpt to the incresed delys. I. INTRODUCTION It might be desirble in some cses to decrese the precision of Digitl Signl Processing (DSP) system to sve power/energy when given level of qulity is sufficient for the ppliction. The power dissipted in circuit composed of N CMOS cells (gtes) is N ( P TOT = 2 int DD C Li E ) N i i f clk DD Ii lek i=1 } {{ } dynmic i=1 } {{ } sttic where DD is the power supply voltge, C Li is the cpcitive lod connected to the output of ech gte, E int i (internl energy) ccounts for the short-circuit currents in the trnsistors nd the power dissipted in the switching of the internl nodes, i is the cell s switching ctivity nd f clk is the clock frequency. In ddition to the dynmic prt, sttic power dissiption due to device lekge (I lek is device s lekge currents) must be ccounted in deep sub-micron CMOS technologies. Expression (1) suggests number of wys to reduce the power dissiption. Some of the prmeters of (1) re cell librry dependent nd cnnot be modified t design time: E int nd I lek. In this work, we focus on reducing the power dissiption by lowering the supply voltge DD,nd by reducing the switching ctivity i in some nodes of the circuit. The ide to disble prt of the logic to reduce the switching ctivity for low power by hving vrible word-length or processing dpted to the chrcteristics of the signl is not new [1], [2], [3]. (1) On the other hnd, by reducing the supply voltge the power dissiption decreses qudrticlly, but circuits get slower. By crefully designing the crry propgtion logic in dders, it is possible to obtin ccurte results t lower supply voltges [4], [5]. In our DSP system, we ssume fixed-point numbers normlized in [, 1.) represented in two s complement by n bits nd with dynmic rnge 2 n. In such systems, degrding the precision mens to reduce the dynmic rnge to 2 n k by introducing n (dditionl) error in the representtion. This low-power driven degrdtion cn be obtined in two wys: I DPA-I By disbling the logic in the rithmetic opertions producing the lower prt (lest-significnt bits) of the dynmic rnge. II DPA-II By lowering the supply voltge, nd consequently incresing the circuit delys, nd cusing limited crry-propgtion (error) into the most significnt prt (reduced dynmic rnge). We illustrte the two methods in the next sections. II. DPA-I: DISABLED LOGIC IN LEAST-SIGNIFICANT S Here we show the trdeoffs between loss of precision nd power dissiption for two schemes pplied to FIR filters. We cn reduce the switching ctivity by either clock-gting pths strting from register or by forcing zeros, or ones, in combintionl logic. By considering FIR filter in trnsposed form (Fig. 1), we cn consider two different pproches: 1) To use clock gting in the registers holding the lestsignificnt (LS) portion of x(t) nd y(t k) (dely line) to freeze the LS prt. The vlue of coefficients k does not chnge unless different filter msk is loded. 2) To force zeros, for exmple by driving the synchronous reset of the LS prt of the flip-flops. In both cses the level of degrdtion cn be chnged by setting the clock-gting (individul flip-flop resets) control signls. First, we show the bit detil in the two filter opertions (ddition nd multipliction) for the two cses bove /1/$ IEEE 1163 Asilomr 21

2 x(t) n n 1 y(t) Z 1 Z 1 Z 1 1 Fig. 1. FIR filter in trnsposed form. freezing forcing-to- k P sve [%] ɛ men P sve [%] ɛ men < < < < < < < < < < < < < < 2 18 A. DPA-I Addition As n exmple, we use n 8-bit dder in which the dynmic rnge is reduced to 4 bits. The error-free 8-bit ddition A B = S is reported below A :. B :.b b b b b b b b = S :.s s s s s s s s By disbling the logic by forcing zeros we obtin the sme effect s trunction: A :. B :.b b b b = S :.s s s σ where σ indictes the sum bit tht might be ffected by the error 1. The mximum error is ɛ mx = 2 (2 k 1) 2 n where k is the number of bits disbled in the ddends out of n. In the specific exmple the mximum error is If we freeze the 4 LSBs, the frozen bits (mrked χ in the following) preserve the lst vlue before the freezing. In this cse, we obtin A :. χ χ χ χ B :.b b b b χ χ χ χ = S :.s s s σ σ σ σ σ nd the error is constnt until the LSBs of both ddends re frozen. B. DPA-I Multipliction For the multipliction X A k we consider 4 4 multiplier in which two bits of multiplicnd X nd multiplier A k re disbled. The error-free scheme is X : x x x x X 1 : x x x x X 2 : x x x x X 3 : x x x x P : p p p p p p p p 1 Clerly crry which is propgted to the bits mrked s might be generted in bit σ. ɛ men is divided by TABLE I ERROR/POWER SAING TRADEOFFS BETWEEN FREEZING AND FORCING-TO- METHODS. By forcing zeros on the 2 LSBs of X nd A k,wehve X : X : X 2 : x x X 3 : x x P : p ρ ρ ρ Exmple: = 225 = (111 1) 2 [ ] = 144 = (11 ) 2 ɛ mx = 81 = (11 1) 2 For this cse the error is ɛ mx = (2 k 1) [2(2 n 1) (2 k 1)] 2 2n On the other hnd, if the 2 LSBs of X re frozen (ll bits of A k re constnt - frozen - during filtering), we hve X : x x χ χ X 1 : x x χ χ X 2 : x x χ χ X 3 : x x χ χ P : p ρ ρ ρ ρ ρ ρ ρ where bits mrked ρ show the positions ffected by errors. Exmple: 4 15 = 6 = (11 11) 2. Lst X before freezing X =15 [4 (11) 2 ] 15 = 15 = (11 11) 2 ɛ = 45 = (1 11) 2 C. DPA-I Filter Experiment To compre the two DPA-I methods (freezing, nd forcingto-), we implemented 16-tp low-pss FIR filter with 1-bit input x nd coefficients k, nd output dynmic rnge of 2 bits which ensures error-free processing. For the two methods, we disble bits with grnulrity k for x nd k,nd2k for the y dely line. The results in terms of power sving nd men error with respect to the error-free filter re reported in Tble I. The power svings re similr for the two methods nd the error is better for the bit-freezing solution. 1164

3 4 bit CPA 4 bit CPA c 4 c c 4 CPA8b s 7 s 6 s 5 s 4 s 3 s 2 s 1 s c 4 t 2 2 t Fig. 2. Exmple of 8-bit dder. t 2 CPA8b III. DPA-II: LOWER SUPPLY OLTAGE Fig. 3. Dely of dder for supply voltge t DD (top) nd 2 (bottom). By reducing the supply voltge the power dissiption decreses qudrticlly, but the dely increses. By keeping the system clocked t the nominl rte nd by lowering the supply voltge errors might pper in the dtpth degrding the precision. A. Adder Exmple We illustrte the method with n exmple of 8-bit crrypropgte dder A B = S. By splitting the 8-bit dder into two 4-bit portions s shown in Fig. 2, we cn represent the bit-level ddition lgorithm s A : B : b 7 b 6 b 5 b 4 b 3 b 2 b 1 b c 4 c = S : s 7 s 6 s 5 s 4 s 3 s 2 s 1 s where c 4 is the crry-out of the lest-significnt portion on the dder. By disconnecting c 4,forS we get n error 2 4 for the combintions of input which generte c 4 =1. Generlizing, if the n-bit dder (n even) is split into two equl prts, by disconnecting c n the error is either or 2 n 2. 2 By considering the propgtion delys of the dders in Fig. 2, the dely of c 4 is close to the dely of the mostsignificnt bit of the 4-bit dder s 4. We ssume tht the mximum dely of the 4-bit dder is the dely of c 4 : t. Becuse the two 4-bit dders re identicl, the mximum dely of the 8-bit dder is t CPA8b = t t 2 t. If the supply voltge is reduced from DD to 2 such tht the dely doubles t 2 =2 tdd in the 8-bit dder of Fig. 2 there is not enough time to propgte c 4 through the 4-bit dder of the most significnt portion. In other words, there is time only to propgte the crry inside 4-bit dder. This is equivlent to disconnecting c 4 in Fig. 2. A timing digrm is shown in Fig. 3. Summrizing, if the circuit is clocked t T clk = CPAnb, the dder is error-free when operting t DD, while it might hve n error ɛ 2 n 2 when operting t 2 < DD. B. SPICE Chrcteriztion To test the DPA-II method, we consider 2-bit dder implemented s A regulr 2-bit crry-propgte dder, clled CPA2b in the following, which is synthesized to obtin the mximum speed. A scheme with two cscded 1-bit dders, similr to the dder of Fig. 2, clled CPA2 1b, inwhichthetwo identicl 1-bit dders (CPA1b) re lso synthesized to obtin the mximum speed. The dders re synthesized by Synopsys Design Compiler in 9 nm librry of stndrd cells with nominl supply voltge DD =1.. The synthesized netlist is then converted into SPICE netlist nd simulted with Synopsys Nnosim. Dt in Tble II show the dependency DD -dely for the dders. CPA2b CPA2 1b CPA1b DD t MAX t MAX t MAX [ ] [ps] rtio [ps] rtio [ps] rtio TABLE II MAXIMUM DELAYS FOR DIFFERENT DD. Tble II shows tht t DD =.7 the dely is more thn doubled for ll dder schemes. By compring the delys of CPA2 1b nd CPA1b, we notice tht the totl dely in CPA2 1b (two cscded CPA1b stges s in Fig. 2) is bout 1% shorter thn two times the dely of CPA1b. C. Power-Precision Trde-off The next step is to chrcterize the error when DD is lowered to.9,.8 nd.7. This is done by operting the two dder schemes t the mximum frequency (1/t MAX ) under reduced DD nd evluting the error t the output. The histogrms of the error distribution re shown in Fig. 4. In the histogrms, the br in position k indictes the occurrences of errors with mgnitude 2 k 1 <ɛ<2 k. For exmple, ɛ = 2 < 2 11 will contribute to br

4 35 3 Architecture: ADDER 1x2 24ns, Supply Power:.9 Architecture: ADDER 1x2 24ns, Supply Power:.8 Architecture: ADDER 1x2 24ns, Supply Power: DD =.9 DD =.8 DD = ) Architecture: ADDER 2x1 35ns, Supply Power:.9 Architecture: ADDER 2x1 35ns, Supply Power:.8 Architecture: ADDER 2x1 35ns, Supply Power: DD =.9 DD =.8 DD = b) Fig. 4. Trde-off Error- DD (t mx speed). ) CPA2b. b)cpa2 1b. 35 Architecture: ADDER 1x2 35ns, Supply Power:.8 35 Architecture: ADDER 1x2 35ns, Supply Power:.7 3 DD =.8 3 DD = Fig. 5. Trde-off Error- DD for CPA2b t rte of 35 ps per opertion. For implementtion CPA2b from Fig. 4., it is cler (brs re clustered in most-significnt bits) tht even for smll reduction of DD the error becomes uncceptble. From Tble II for DD =.9, the dely is incresed by 55 ps (22%) nd 24 ps is not enough time to propgte the crry in the most-significnt prt. On the other hnd, for CPA2 1b (Fig. 4.b) most of the errors occur becuse the crry between the two cscded 1- bit dders c 1 is not propgted in the upper 1-bit dder for DD =.9.8.For DD =.7, the crry propgtion is limited within both portions of CPA2 1b. This experimentl result confirms the theoreticl nlysis of Section III-A. However, becuse CPA2b is fster thn CPA2 1b, we cn compre the error distribution for both schemes when clocked t the sme rte (the dely of CPA2 1b, 35 ps). The histogrms for CPA2b clocked t 35 ps re shown in Fig. 5. The histogrm for DD =.9 produced no errors nd it hs been omitted in the figure. The dt of Fig. 4.b nd Fig. 5 together with the respective power dissiption figures re reported in Tble III. Tble III shows the verge power dissiption for the given DD vlues, the number of vectors with errors (# ɛ) for ech experiment out of the 1, tested input combintions (rndomly distributed), the mximum error (ɛ mx ), nd the verge error ɛ men ) for the 1, combintions. From the dt in Tble III, we cn derive the following conclusions: 1) Scheme CPA2b is error-free t DD =.9 with power svings of bout 15%. 2) For DD =.8 the verge error in CPA2 1b is significntly smller lthough the power dissipted by CPA2b is slightly lower. 3) For DD =.7 both schemes give high verge error nd both re prcticlly unusble t the rte of one ddition per 35 ps. 1166

5 CPA2b CPA2 1b T C DD Power Error Power Error [ps] [mw ] rtio # ɛ ɛ mx ɛ men [mw ] rtio # ɛ ɛ mx ɛ men , < ,288 2,851 < , < , ,676 < ,424 32,926 < 2 16 Totl number of vectors is 1, Note: rtio DD 2 TABLE III SUMMARY OF TRADE-OFFS FOR CPA2b AND CPA2 1b SCHEMES. Moreover, for the CPA2 1b scheme, the verge error for DD =.8.9 is the sme lthough the number of errors is much higher (three times) in the.8 cse. This result cn be explined s t DD =.8 most of the input combintions fil in propgting the crry in the upper 1-bit dder nd the errors re clustered round the lest-significnt bits of the upper prt (2 1, 2 11 ) s shown in Fig. 4.b. At DD =.9 on the other hnd, the circuit is fster (bout 25%) nd there is time to propgte the crry beyond the lest-significnt bits of the upper dder. This lst result shows tht by designing the crrypropgtion chin ccording to the vilble time slck (due to the reduction of DD ) we cn control the error propgtion in the bits of different weight. This result lso confirm, tht hving fster dder under reduced supply voltge does not gurntee the best precision when compred to n dder which is slower, but hs crry-chin designed to tolerte some extr ltency. REFERENCES [1] P. Lrsson nd C. J. Nicol, Self-djusting bit precision for low-power digitl filters, Proc. of IEEE Symposium on LSI Circuits, p , June [2] S. Yoshizw nd Y. Miyng, Use of rible Wordlength Technique in n OFDM Receiver to Reduce Energy Dissiption, IEEE Trnsctions on Circuits nd Systems-I, vol. 55, no. 9, pp , Oct. 28. [3] A. Bonnno, A. Bocc, A. Mcii, E. Mcii, nd M. Poncino, Dt-Driven Clock Gting for Digitl Filters, Proc. of 19th Interntionl Workshop on Power And Timing Modeling, Optimiztion nd Simultion (PATMOS 29), pp , Sept. 29. [4] S.-L. Lu, Speeding up processing with pproximtion circuits, IEEE Computer Mgzine, vol. 37, no. 3, pp , Mr. 24. [5] D. R. Kelly, B. J. Phillips, nd S. Al-Srwi, Incresing Throughput of RISC Architecture Using Arithmetic Dt lue Specultion, Proc. of 43rd Asilomr Conference on Signls, Systems, nd Computers, pp , Nov. 29. I. CONCLUSIONS AND FUTURE WORK It is possible to trdeoff precision with power dissiption in DSP systems. The first method proposed is bsed on the reduction of the circuit switching ctivity by selectively disbling the lest-significnt bits. The ppliction of bitfreezing or forcing-to- to FIR filters leds to power svings of bout 3% with n error roughly hlf-wy the mximum precision. Similr power consumption reductions cn be obtined by lowering the power supply voltge nd mking sure tht the crry-chins re designed to obtin trget error distribution. Furthermore, the results obtined for DPA-II suggest to investigte further in the design of dders with configurble crry-chins to dpt to the extr ltency introduced by reduced supply voltge. 1167