The Influence of Interface and Semiconductor Bulk Traps Generated Under HEFS on MOSFET`s Electrical Characteristics

Transcription

1 Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 The Influence of Interfce nd Semiconductor Bulk Trps Generted Under HEFS on MOSFET`s Electricl Chrcteristics Snj Aleksić, Dnijel Pntić, nd Drgn Pntić Astrct - In this pper, the impct of defects (donor nd cceptor trps) which re generted t the Si/SiO 2 interfce nd in semiconductor ulk, when the gte oxide is exposed to high electric field stress (HEFS), on n-chnnel MOS nd VDMOS trnsistors electricl chrcteristics is nlysed nd simulted. Tking the dvntge of simultion, it ws shown how nd why the generted trps ffect on n-chnnel MOS nd n-chnnel VDMOS electricl chrcteristics. 1 Keywords TCAD, trps, HEFS, interfce, ulk, MOS. I. INTRODUCTION The stility nd reliility of MOSFET`s electricl chrcteristics is one of the most importnt requirements tht re requested in the process of device nd circuit design. It is known tht under the influence of different effects, such s irrdition, high temperture (NBTI) or high electric field stress (HEFS), the neutrl or chrged defects (trps) re generted t the Si/SiO 2 interfce, s well s in the semiconductor nd gte oxide ulk [1-3]. The formed trps my cuse the temporl degrdtion of the electricl chrcteristics of semiconductor device, which finlly ffects on the relile opertion of the electronic circuit nd device, where the MOSFETs re integrted. Over the lst few decdes numer of the physicl models for the instility explntions hve een proposed [4,5]. The mjority of these models hve no ility to nlyse influence of the ll generted trps, considering tht these very complex processes re still not well understood, since it is necessry to tke into ccount the impct of lrge numer of prmeters. Using the possiilities provided y Silvco TCAD simultion tools, in which the dvnced physicl models re incorported [6,7], the ility to seprte nlyse the influence of different prmeters, models nd mechnisms, on the device electricl chrcteristics is offered. The effects of interfce nd semiconductor ulk trps generted under the HEFS on the electricl chrcteristics of n-chnnel MOS nd VDMOS trnsistors re investigted in this pper. 1 Snj Aleksić nd Drgn Pntić re with the Deprtment of Microelectronics, Fculty of Electronic Engineering, University of Niš, Aleksndr Medvedev 14, Niš, Seri, E-mil: {snj.leksic, drgn.pntic@elfk.ni.c.yu }. Dnijel Pntić is with High School of Electricl Engineering Nikol Tesl, A. Medvedev 20, Niš, Seri, E-mil: dnijel@etstesl.ni.c.rs. II. NUMERICAL MODEL The presence of chrged defects or trps t the Si/SiO 2 interfce, or in oxide nd semiconductor ulk hs significnt impct on the device electricl chrcteristics. These trps re chnging the density of spce chrge nd the potentil distriution in the device structure nd lso hve the influence on the recomintion sttistics nd crriers moility. The fct is tht the mount of ulk nd interfce chrged trps increses significntly when the devices re exposed to high electric field or rdition (HEFS), nd in these cses n ccurte simultion of the electricl chrcteristics of semiconductor devices requires to tke into considertion the influence of spce chrge tht comes from stress induced chrge trps. There re three different mechnisms which dd spce chrge directly into the right hnd side of Poisson s eqution in ddition to the ionized donor nd cceptor impurities, nd these re interfce fixed chrge, interfce trp nd ulk trp sttes. Interfce fixed chrge is controlled y the interfce oundry condition, while the interfce nd ulk chrged trps, Q IT nd QIB re dded directly into the Poisson`s eqution: div ε ϕ) = q( n p N N ) ( Q Q ) (1) ( D A IT BT Associted energy of interfce nd semiconductor trps lies in foridden gp nd exchnge chrge through the emission or cptured electrons with conduction nd vlence nd. The net chrge Q tht comes from the presence on IT DT AT ionized donor-like ( N ) nd cceptor-like ( N ) trps t Si/SiO2 interfce is defined s: Q q( N N ) = Q Q ) (2) IT = DT AT DT AT In the cse when the ssocited energy of donor-like trp (DT) lies in foridden gp ner the ottom of conduction nd it releses n electron nd ecomes positive chrged. The increse of positive chrge (Q IT ) t the Si/SiO 2 interfce reduces the threshold voltge V TH of n-chnnel MOSFET (Fig. 1). Contrry, cceptor-like trp (AT) is ionized (negtively chrged) when its energy level lies ner the top of vlence nd. In tht cse, AT is filled with n electron, nd the presence of Q IT t the interfce would cuse n increse in the threshold voltge of n-chnnel MOSFET (Fig. 1). The chnges of chrge t the Si/SiO 2 interfce lso ffects on other electricl chrcteristics such s: lekge current I L, sturtion current I SAT, etc. 59

2 Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 A. n-chnnel MOS trnsistor interfce trps Fig. 1. The schemtic representtion of DT nd AT ioniztion processes nd the genertion of the chrge t Si/SiO 2 interfce. Trps generted under the HEFS in the semiconductor ulk influence on the electricl chrcteristics of MOSFET in slightly different wy. DT nd AT ioniztion processes in the ulk of semiconductor re going on in similr wy nd under the sme conditions, ut in this cse the influence of electron concentrtion in the semiconductor ulk is more importnt thn the formed positive or negtive chrge (Fig. 2). When the ssocited energy of DT in foridden gp chnges from E V to E C, the proility of its ioniztion increses, it releses n electron nd ecomes positive chrged. The increse of the electron concentrtion in semiconductor ulk leds to the reduction of threshold voltge V TH, while t the sme time the sturtion current I SAT of the n-chnnel MOSFET increses. In the cse of AT, the ioniztion proility increses when their ssocited energy chnges from E C to E V. AT in semiconductor ulk cptures n electron nd ecomes neutrl. This recomintion process significntly reduces the sturtion current I SAT, which is prticulrly importnt in n-chnnel VDMOSFET, due to the fct tht its current fter the chnnel, flows verticlly through the epitxil lyer nd Si sustrte to drin contct. The impct of DT nd AT generted t the Si/SiO 2 interfce generted under HEFS is nlysed on typicl n- chnnel MOS trnsistor fricted in stndrd 0.35μm CMOS technology. The gte oxide thickness is d OX =10nm. The influences of interfce DT nd AT on V TH, I L =I D (V GS =0.1V) nd I SAT =I D (V GS =5.V), otined y nlysing the simultion results re summrized in T. I. TABLE I: The influence of interfce DT nd AT on the electricl chrcteristics of n-chnnel MOS trnsistor. N DT > cm -3 const E.L DT > 0.6eV E C const E.L DT > 0.6eV E V const const const N AT > cm -3 E.L AT > 0.8eV E C const const E.L AT > 0.8eV E V const const The distriution of potentil in poly-si, electric field in gte oxide, ionized DT density t Si/SiO 2 interfce, nd electron concentrtion in silicon, re shown on Fig. 3. The chnge of the threshold voltge V TH of n-chnnel MOS, depending on interfce DT prmeters (donor trp density N DT nd ssocited energy level E.L DT ) is given on Fig. 4. N DT =5.e15, E.L DT =0.5eV V TH =0.65V, N DT =1.e09 N DT =5.e15, E.L DT =0.78eV V TH =0.36V, N DT =3.e12 Fig. 2. The schemtic representtion of DT nd AT ioniztion nd genertion-recomintion processes in semiconductor ulk. Fig. 3. Interfce DT influence on n-chnnel MOS trnsistor: ) ionized donor trps density, ) electron concentrtion. III. SIMULATION RESULTS In this section the impcts of DT nd AT trps t Si/SiO 2 interfce nd in semiconductor ulk on the electricl chrcteristics of n-chnnel MOS trnsistor nd n-chnnel VDMOS power trnsistor re presented. The simultions hve een crried out y using the process simultor ATHENA [8] nd the device simultor ATLAS [9], which re the integrl prt of Silvco TCAD softwre pckge. Fig. 4. The chnge of the threshold voltge V TH of n-chnnel MOS, depending on interfce DT prmeters. 60

3 Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 The distriution of potentil in poly-si, electric field in gte oxide, ionized AT density t Si/SiO 2 interfce nd electron concentrtion in silicon, re shown on Fig. 5. The chnges of the threshold voltge V TH nd lekge current I L of n- chnnel MOS, depending on interfce AT prmeters (cceptor trp density N AT nd ssocited energy level E.L AT ) re given on Fig. 6 nd Fig. 7, respectively. Sets of AT prmeters for the given ionized cceptor trp density nd electron concentrtion on Fig. 5 re mrked on Fig. 6. N AT =1.e12, E.L AT =0.5eV V TH =1.16V, N AT =9.e11 N AT =1.e12, E.L AT =0.1eV V TH =0.75V, N AT =3.e011 Fig. 5. Interfce AT influence on n-chnnel MOS trnsistor: ) ionized cceptor trps density, ) electron concentrtion. B. n-chnnel MOS trnsistor ulk trps The influences of ulk DT nd AT on V TH, I L nd I SAT, otined y the nlysing of the simultion results re summrized in T. II. It is ovious tht the presence of DT nd AT in semiconductor ulk lso impct on the vlue of I SAT due to recomintion process. TABLE II: The influence of ulk DT nd AT on the electricl chrcteristics of n-chnnel MOS trnsistor. N DT > cm -3 E.L DT > E V E C N AT > cm -3 E.L AT > E C E V The distriution of potentil in poly-si, electric field in gte oxide, ionized DT density in semiconductor ulk, electron concentrtion nd totl current density, in silicon re given on Fig. 8, while the chnge of the threshold voltge V TH of n-chnnel MOS, depending on ulk DT prmeters (donor trp density N DT nd ssocited energy level E.L DT ) is given on Fig. 9. Sets of DT prmeters for the given ionized donor trp density, electron concentrtion nd totl current density on Fig. 8 re mrked on Fig. 9. The distriution of potentil in poly-si, electric field in gte oxide, ionized AT density in semiconductor ulk, electron concentrtion nd crrier recomintion velocity in silicon, re shown on Fig. 10, while the chnge of the threshold voltge V TH of n-chnnel MOS, depending on ulk AT prmeters (donor trp density N DT nd ssocited energy level E.L DT ) is given on Fig. 11. N DT =1.e17, E.L DT =0.1eV V TH =0.62V N DT =1.e17, E.L DT =0.7eV V TH =0.37V Fig. 6. The chnge of the threshold voltge V TH of n-chnnel MOS, depending on interfce AT prmeters. Fig. 7. The chnge of the lekge current I L of n-chnnel MOS, depending on interfce AT prmeters. c Fig. 8. Bulk DT influence on n-chnnel MOS trnsistor: ) ionized donor trps density, ) electron concentrtion nd c) totl current density. 61

4 Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 C. n-chnnel VDMOS trnsistor interfce trps The impct of DT nd AT generted t the Si/SiO 2 interfce generted under HEFS is nlysed on typicl n- chnnel VDMOS trnsistor. The chnnel length nd gte oxide thickness of the VDMOS trnsistor re l CH =1μm nd d OX =60nm, while the threshold voltge is V TH =3.7V. The influences of interfce DT nd AT on V TH, I L =I D (V GS =0.4V) nd I SAT =I D (V GS =10.V), otined y nlysis of the simultion results re given in T. III. TABLE III: The influence of interfce DT nd AT on the electricl chrcteristics of n-chnnel VDMOS trnsistor. Fig. 9. The chnge of the threshold voltge V TH of n-chnnel MOS, depending on ulk DT prmeters. N AT =8.e17, E.L AT =0.1eV V TH =0.66V c N AT =8.e17, E.L AT =0.7eV V TH =1.72V Fig. 10. Bulk AT influence on n-chnnel MOS trnsistor: ) ionized cceptor trps density, ) electron concentrtion nd c) recomintion velocity. N DT > cm -3 const E.L DT > 0.6eV E C const E.L DT > 0.6eV E V const const N AT > cm -3 const E.L AT > 0.8eV E C const E.L AT > E V 0.8eV const const As cn e seen, the interfce DT hs the identicl impct on the electricl chrcteristics of VDMOS trnsistor s in the cse of MOS trnsistor, while the impct of interfce AT is slightly different. Unlike MOS trnsistor, here, the interfce AT reduces the sturtion current nd does not ffect on the lekge current. The distriution of potentil in poly-si, electric field in gte oxide, ionized DT density t Si/SiO 2 interfce, nd electron concentrtion, re shown on Fig. 12, while the chnge of the threshold voltge V TH of n-chnnel VDMOS, depending on interfce DT prmeters (donor trp density N DT nd ssocited energy level E.L DT ) is given on Fig. 13. The vlues of threshold voltge V TH nd ionized interfce DT concentrtion N DT re given on Fig.12, while the sets of DT prmeters for the given ionized donor trp density nd electron concentrtion on Fig.12 re mrked on Fig.13. N DT =1.e14, E.L DT =0.5eV V TH =3.8V, N DT =4.e05 N DT =1.e14, E.L DT =0.8eV V TH =1.30V, N DT =5.e10 Fig. 11. The chnge of the threshold voltge V TH of n-chnnel MOS, depending on ulk AT prmeters. Fig. 12. Interfce DT influence on n-chnnel VDMOS trnsistor: ) ionized donor trps density, ) electron concentrtion. 62

5 Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 D. n-chnnel VDMOS trnsistor ulk trps The influences of ulk DT nd AT on V TH, I L nd I SAT, otined y the nlysing of the simultion results re summrized in T. IV. TABLE IV: The influence of ulk DT nd AT on the electricl chrcteristics of n-chnnel VDMOS trnsistor. Fig. 13. The influence of interfce DT prmeters: donor trp density N DT nd energy level E.L DT on threshold voltge V TH. The distriution of potentil in poly-si, electric field in gte oxide, ionized AT density t Si/SiO 2 interfce, nd totl current density, re shown on Fig. 14, while the chnge of the threshold voltge V TH of n-chnnel VDMOS, depending on interfce DT prmeters (donor trp density N DT nd ssocited energy level E.L DT ) is given on Fig. 15. N DT > cm -3 E.L DT > E V E C N AT > 10?? cm -3 no inf. E.L AT > E C 0.5eV no inf. const E.L AT > 0.5eV E V no inf. const The ulk DT hs the identicl impct on the electricl chrcteristics of VDMOS trnsistor s in the cse of MOS trnsistor. The ulk AT reduces the sturtion current due to ioniztion of trps nd recomintion of electrons. This is prticulrly evident when the ssocited energy of AT is pproching to the top of the vlence zone (Fig. 16). N AT =1.e12, E.L AT =0.1eV V TH =3.8V, N AT =2.e11 N AT =1.e12, E.L AT =0.5eV V TH =6.5V, N AT =1.e012 Fig. 14. Interfce AT influence on n-chnnel VDMOS trnsistor: ) ionized cceptor trps density, ) totl current density. Fig. 16. The influence of ulk AT ssocite energy level on the sturtion current of n-chnnel VDMOS trnsistor. N DT =5.e17, E.L DT =0.1eV V TH =3.7V N DT =5.e17, E.L DT =0.7eV V TH =2.70V Fig. 15. The influence of interfce AT prmeters: cceptor trp density N AT nd energy level E.L AT on threshold voltge V TH. Fig. 17. Bulk DT influence on n-chnnel VDMOS trnsistor: ) ionized donor trps density, ) recomintion velocity. 63

6 Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 The distriution of potentil in poly-si, electric field in gte oxide, ionized DT nd AT density in semiconductor ulk, electron concentrtion, recomintion velocity nd totl current density, in silicon re given on Figs. 17 nd 18, while the chnge of the threshold voltge V TH of n- chnnel VDMOS, depending on ulk DT prmeters is given on Fig. 19, where the sets of DT prmeters for the given distriutions re mrked. N AT =1.e15, E.L AT =0.1eV V TH =3.8V N AT =1.e15, E.L AT =0.7eV c Fig. 18. Interfce AT influence on n-chnnel VDMOS trnsistor: ) ionized cceptor trps density, ) recomintion velocity, c) totl current density. IV. CONCLUSION The impcts of defects, which re generted t the Si/SiO 2 interfce nd in the semiconductor ulk under HEFS, on the electricl chrcteristics of n-chnnel MOS nd n-chnnel VDMOS power trnsistors re nlysed nd simulted seprtely y using the progrm ATHENA for the complete technology process simultion nd the device simultor ATLAS which re n integrl prt of Silvco TCAD softwre pckge. ACKNOWLEDGEMENT This work hs een supported y the Ministry of Eduction nd Science of the Repulic of Seri, under the project TR Fig. 19. The influence of interfce DT prmeters: donor trp density N DT nd energy level E.L DT on threshold voltge V TH. REFERENCES [1] Wng, T., Ching, L., Zous, N., Chng, T., Hung, C., "Oxide Trps in MOSFET s y Using Suthreshold Trnsient Current Technique", IEEE Trnsction on Electron Devices, Vol. 45, No. 8, 1998, pp [2] Alwn, M., Beydoun, B., Kett, K., Zoeter, M., "Bis temperture instility from gte chrge chrcteristics investigtions in n-chnnel power MOSFET", Microelectronics Journl, Vol. 38, 2007, pp [3] Benltreche, M.S,, Rhmoune, F., Toumit, O., "Experimentl investigtion of Si-SiO2 interfce trps using equilirium voltge step technique", Informcije MIDEM, Vol. 41, No. 3, 2011, pp [4] Esseni, D., Bude, J-D., Selmi, L., "On Interfce nd Oxide Degrdtion in VLSI MOSFETs Prt II: Fowler Nordheim Stress Regime", IEEE Trnsction on Electron Devices, Vol. 49, No. 2, 2002, pp [5] Crtier, E., "Chrcteriztion of the hot-electroninduced degrdtion in thin SiO 2 gte oxide", Microelectronics Reliility, Vol. 38, No. 2, 1997, pp [6] Aleksić, S., Pešić, B., Pntić, D., "Simultion of Semiconductor Bulk Trp Influence on the Electricl Chrcteristics of the n-chnnel Power VDMOS Trnsistor", Informcije MIDEM, Vol. 43, No. 2, 2013, pp [7] Aleksić, S., Bjelopvlić, D., Pntić, D., "Simultion of Bulk Trps Influence on the Electricl Chrcteristics of VDMOS Trnsistor, Proc. of XLVI Interntionl Scientific Conference on Informtion, Communiction nd Energy Systems nd Technologies - ICEST 2011, pp , Niš, Seri, June [8] ATHENA User s Mnul, SILVACO, Inc., CA, USA, [9] ATLAS User s Mnul, SILVACO, Inc., CA, USA,