Solid-State Electronics

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Solid-Stte Electronics 52 (2008) 1182 1187 Contents lists ville t ScienceDirect Solid-Stte Electronics journl homepge: www.elsevier.

1 Solid-Stte Electronics 52 (2008) Contents lists ville t ScienceDirect Solid-Stte Electronics journl homepge: STI-to-gte distnce effects on flicker noise chrcteristics in 0.13 lm CMOS Chih-Yun Chn, Yen-Chun Hung, Jun-Wei Chen, Shwn S.H. Hsu, *, Ying-Zong Jung Institute of Electronics Engineering, Ntionl Tsing Hu University, EECS 509, 101, Sector 2, Kung-Fu Rod, Hsinchu 300, Tiwn Ntionl Chip Implementtion Center, Hsinchu, Tiwn rticle info strct Article history: Received 2 Ferury 2008 Received in revised form 15 April 2008 Accepted 2 My 2008 Aville online 11 June 2008 The review of this pper ws rrnged y Prof. S. Cristolovenu Keywords: Flicker noise CMOS Shllow-trench-isoltion (STI) Stress The geometry effect on the flicker noise chrcteristics nd the vritions in 0.13 lm CMOS trnsistors were studied. By symmetriclly extending the distnce etween the shllow-trench-isoltion (STI) to the gte, oth NMOS nd PMOS presented ovious improvement on the noise chrcteristics. As the distnce incresed from 0.6 lm to 10lm, the verge noise level reduced y more thn one order of mgnitude (NMOS) nd the stndrd devitions r db improved from 5.95 db to 1.79 db for NMOS nd from 3.93 db to 2.17 db for PMOS, respectively. To further identify the noise mechnism, the devices with symmetricl STI-to-gte distnces were lso investigted. It ws found tht the distnce in the source side (SA) hs much higher impct on the oserved noise chrcteristics. The results suggested tht the noise chrcteristics were dominted y the STI stress induced trps for oth NMOS nd PMOS studied here. In ddition, the crrier numer fluctution model with the correlted moility scttering could e more suitle to descrie the noise chrcteristics in these devices. Ó 2008 Elsevier Ltd. All rights reserved. 1. Introduction 2. Devices lyout design In recent yers, the shllow-trench-isoltion (STI) is eing extensively employed in the CMOS process to improve the isoltion etween the devices. As the device technology keeps dvncing, the MOSFET chrcteristics hve ecome very sensitive to the compressive stress introduced y the STI. It hs een found tht the device DC chrcteristics, e.g., threshold voltge (Vth), trnsconductnce (g m ), lekge current nd drin current (I DS ) re ll ffected y the STI [1 4]. The compressive stress resulted from STI nd the stress-control lyers on flicker noise in CMOS hve lso een studied previously [5 6]. In ddition, the device geometries cn e crucil to the low-frequency noise chrcteristics under the impct of STI [7 8]. In this work, we study the 0.13 lm RF CMOS trnsistors with oth symmetricl nd symmetricl lyouts regrding vrious STI spces. By extending the STI-to-gte spce, the flicker noise level nd the corresponding vrition reduce significntly. To further investigte the impct of STI stress on the devices, the devices with symmetricl lyouts re designed to identify the flicker noise mechnisms. Ech device type from mny different chips is mesured to otin sttisticl conclusion. This pper is orgnized s follows. Section 2 descries the device lyouts nd the test structure. Section 3 presents the experimentl results nd discussion, including the Vth, g m, I DS, flicker noise chrcteristics, nd the noise vrition model. Section 4 concludes this work. * Corresponding uthor. Tel.: ; fx: E-mil ddress: shhsu@ee.nthu.edu.tw (S.S.H. Hsu). Fig. 1 shows the typicl lyout of MOSFET nd the ctive region is surrounded y the STI structure, where SA nd SB re defined s the distnces from the gte edge to the STI for the source nd drin sides, respectively. By chnging the SA(SB) distnce, the ssocited compressive stress introduced y STI in the ctive region cn e different. Three STI-to-gte distnces for symmetricl lyout (SA = SB) of 0.6 lm (minimum rule), 1.2 lm, nd 10 lm, nd the symmetricl structures (SA 6¼ SB) of 0.6 lm/10 lm were designed. Both NMOS nd PMOS used in this study were fricted y stndrd 0.13 lm CMOS process, with gte oxide thickness of 26 Å, nd the Vth of 0.4 V. Tle 1 lists ll the device sizes under test nd fixed W/L = 10/0.13 (N finger = 1) is employed for fir comprison. The test structure used in this study is GSG (ground-signlground) RF pds. Since the nnometer-scle devices often hve very high low-frequency gin, the low-impednce RF terminls (50 ohm) cn prevent the oscilltion prolems to otin more relile dt. The flicker noise mesurement setup in this work is depicted s descried in [7]. The mesurements re performed in rnge of 10 Hz 100 KHz, nd the noise floor of the system is well elow the tested devices in the mesured frequency rnge. 3. Results nd discussion 3.1. DC chrcteristics Fig. 2 shows the threshold voltges for the three designs of symmetricl devices (SA = SB). The results indicte tht the verge /$ - see front mtter Ó 2008 Elsevier Ltd. All rights reserved. doi: /j.sse

2 C.-Y. Chn et l. / Solid-Stte Electronics 52 (2008) Poly Gte SA(SB) = 0.6 μm Source Drin V th (V) SA(SB) = 1.2 μm STI SA SB STI SA(SB) = 10 μm μm NMOS Averge SA(SB) Distnce (μm) Fig. 1. Typicl lyout of MOSFET surrounded y the STI structure nd the corresponding cross section, where SA(SB) is the gte-to-sti distnce. Tle 1 Different devices under test in this study W/L = 10/0.13 (N finger = 1) Symmetricl devices Asymmetricl devices SA (lm) SB (lm) SA (lm) SB (lm) NMOS PMOS V th (V) SA(SB) = 0.6 μm SA(SB) = 1.2 μm SA(SB) = 10 μm μm PMOS Averge SA(SB) Distnce (μm) Fig. 2. Experimentl results of Vth s function of the STI-to-gte distnce SA(SB) for 0.13 lm () NMOS, nd () PMOS. Vth (five devices) shifts 18 mv for NMOS nd 6.5 mv for PMOS, s SA(SB) reduces from 10 lm to 0.6 lm. The min reson cn e ttriuted to the STI stress induced sustrte doping modultion. As the STI edge ecomes closer to the chnnel, the pocket implnt (or hlo implnt) is ffected y the stress leding to higher effective sustrte doping concentrtion [9 10] nd therefore incresed Vth for oth NMOS nd PMOS. Fig. 3 presents the trnsconductnce (g m ) chnges s function of V GS in the triode region, nd n opposite trend cn e oserved for NMOS nd PMOS. The mximum g m of NMOS degrdes y 10%, while tht of PMOS improves y 12%, which cn e explined y the following eqution g m ¼ oi DS W triode region ¼ l eff C ox L / l eff ð1þ ov GS where l eff is the effective crrier moility. For fixed, the chnge of g m cn e minly ttriuted from the ffected moility due to the STI stress [11]. For NMOS devices, the compressive stress degrdes the crrier moility, while tht improves the moility for PMOS. Similr trends re lso oserved in the DC I V chrcteristics. With the compressive stress, the split vlnce nd results in lighthole-like energy levels leding to reduced hole effective mss nd enhnced moility in PMOS. Oppositely, the stress induced phonon scttering increses electron effective mss nd thus the reduced moility in NMOS [11]. Aove discussions indicte tht the devices with different STI-to-gte distnces present different DC chrcteristics. Detiled investigtions on flicker noise chrcteristics for different device geometries will e crried out in the following sections. Gm (ms/mm) NMOS nd PMOS = 50 mv SA = SB = d NMOS d = 10 μm 3.2. Flicker noise chrcteristics PMOS d = 0.6 μm PMOS d = 10 μm NMOS d = 0.6 μm Gte Voltge (V) Fig. 3. Dependence of the trnsconductnce g m on the STI-to-gte distnce SA(SB) for oth 0.13 lm NMOS nd PMOS Symmetricl devices Both crrier numer fluctution nd moility fluctution models were employed to explin the flicker noise mechnisms in MOSFETs [12 19]. For NMOS trnsistors, the origin of the flicker noise ws minly ttriuted to the crrier numer fluctution [18 19]. However, some of the studies suggested tht the moility fluctution model my e more suitle for PMOS [17,20]. Compred with the previous studies, it is even more interesting to clrify this point here since the STI effect hs n impct on the crrier

3 1184 C.-Y. Chn et l. / Solid-Stte Electronics 52 (2008) RF NMOS SA = SB = 10μm = 50 mv, V GS = 0.45 V~ 0.8 V / I 2 t f = 10 Hz RF PMOS SA = SB = 10 μm = -50 mv, V GS = V ~ -0.8 V / I 2 t f = 10 Hz RF NMOS SA = SB = 0.6μm = 50 mv, V GS = 0.45 V ~ 0.8 V / I 2 t f = 10 Hz RF PMOS SA = SB = 0.6μm = -50 mv, V GS = V ~ -0.8 V / I 2 t f = 10 Hz Fig. 4. Noise current spectrl density /I 2 t 10 Hz nd (g m /I D ) 2 s function of the drin current for 0.13 lm () NMOS, nd () PMOS with SA(SB)=10lm. Both devices re ised under of 50 mv nd V GS from 0.45 V to 0.8 V (50 mv/step). Fig. 5. Noise current spectrl density /I 2 t 10 Hz nd (g m /I D ) 2 s function of the drin current for 0.13 lm () NMOS, nd () PMOS with SA(SB) = 0.6 lm. Both devices re ised under of 50 mv nd V GS from 0.45 V to 0.8 V (50 mv/step). moility nd lso introduces trps simultneously. Both types of devices were mesured in the triode region ( = 50 mv) to identify the flicker noise mechnisms. Fig. 4() nd () plots the /I 2 curves versus (g m /I) 2 for NMOS nd PMOS (SA = SB =10lm), respectively. As cn e seen, these two curves follow the sme trend when the drin current increses, which indictes tht the crrier numer fluctution model is more suitle in oth cses [21]. The results suggest tht lthough the STI stress ffects the crrier moility, the min flicker noise mechnism is still the crrier numer fluctution. Fig. 5() nd () shows the results for NMOS nd PMOS of SA = SB = 0.6 lm, respectively. Notice tht discrepncy etween the /I 2 nd the (g m /I) 2 curves in oth figures cn e oserved s the devices enter the high-current region, which cn e explined y the following eqution [21] 2 g 2 m ¼ S vf ðf Þ ð2þ I 2 D 1 l eff C ox I D g m I 2 D where is the scttering prmeter, l eff is the effective crrier moility, nd the S vf is fltnd voltge spectrl density [17]. As indicted in (2), the numer fluctution could induce correlted moility scttering. As result, when SA(SB) ecomes very smll nd with more effective trps, this effect is more significnt leding to the devition of the two curves s oserved in Fig. 5. Fig. 6 8, present the normlized drin noise current spectrl densities for symmetricl NMOS devices (SA(SB) = 0.6 lm, 1.2 lm, nd 10 lm) ised in the sturtion region ( of 0.7 V nd V GS of 0.7 V). As shown in Fig. 6 with SA(SB) = 0.6 lm, the noise level presents wide vrition up to lmost two orders of mgnitude / I 2 (Hz -1 ) Symmetricl NMOS SA = SB = 0.6 μm Fig. 6. Normlized noise current spectrl density /I 2 for 0.13 lm NMOS with SA(SB) = 0.6 lm under of 0.7 V nd V GS. The different trces re for different devices with the sme W/L = 10/0.13 (N finger = 1). nd ovious G R components from different devices even under the sme is condition. On the other hnd, the noise vrition cn e effectively reduced when SA(SB) extended to 1.2 lm nd eyond (10 lm) s shown in Fig. 7 nd Fig. 8, in which the noise level vrition is round one order of mgnitude for the worst cses, nd the G R noise plteus re not s ovious s those oserved in Fig. 6 for the devices with SA(SB) = 0.6 lm.

4 C.-Y. Chn et l. / Solid-Stte Electronics 52 (2008) / I 2 (Hz -1 ) Symmetricl NMOS SA = SB = 1.2 μm Fig. 7. Normlized noise current spectrl density /I 2 for 0.13 lm NMOS with SA(SB) = 1.2 lm under of 0.7 V nd V GS. The different trces re for different devices with the sme W/L = 10/0.13 (N finger = 1). / I 2 (Hz -1 ) Symmetricl NMOS SA = SB = 10 μm Fig. 8. Normlized noise current spectrl density /I 2 for 0.13 lm NMOS with SA(SB)=10lm under of 0.7 V nd V GS. The different trces re for different devices with the sme W/L = 10/0.13 (N finger = 1). / I 2 (Hz -1 ) Symmetricl NMOS / I 2 t 100Hz, V GS / I 2 for different devices Averge Vlue SA=SB (μm) Fig. 9. The normlized noise current spectrl density /I 2 t f = 100 Hz for NMOS s function of the STI-to-gte distnce SA(SB). The devices were ised in the sturtion region under fixed of 0.7 V nd V GS. The different points re for different devices with the sme W/L = 10/0.13 (N finger = 1). Fig. 9 plots the noise current spectrl density /I 2 t 100 Hz for the three types of NMOS devices together, which indictes tht the verged noise level nd noise vrition reduce significntly when SA(SB) increses from 0.6 lm to 1.2 lm, while the chnges re not tht ovious s the SA(SB) further extends to 10 lm. The results suggest tht the noise vrition nd the noise level hve strong dependence on the STI round the ctive region. With the high compressive stress induced round the STI nd the ctive re oundry, mny defects cn e generted during the process. The closer distnce of STI to the device chnnel, the more severe effect on the device flicker noise chrcteristics cn e oserved. As oserved from the experimentl results, the SA(SB) distnce of 1.2 lm selected in this study seems trnsition vlue for the lowered STI effect, which is consistent with those reported previously [2 3]. According to Miymoto et l. [2], the simultion results indicted tht the compressive stress in the x direction incresed rpidly from 450 MP to 750 MP when the STI uffer spce ecomes less thn 1 lm. Also, Gllon et l. [3] showed tht the criticl distnce for the STI hving n impct on trnsistor chrcteristics onsets lso from 1 lm. The results suggest tht the distnce of 1.2 lm oserved here is most likely generl cse. However, this STI stress relx distnce my depend on different technologies nd etter e determined y experiments. Vrious processes hve een proposed to llevite the STI induced stress in CMOS process [2,5]. The PMOS trnsistors presented similr trend with tht of NMOS s shown in Fig. 10. As mentioned, some previous studies suggested tht the moility fluctution my e the dominnt fctor for PMOS trnsistors in the strong inversion [16 17]. However, sed on the results of Fig. 4(), Fig. 5(), nd the dependence of SA(SB) on the noise spectrl densities in Fig. 10, the noise chrcteristics of the PMOS trnsistors re similr with the NMOS devices. In other words, the noise mechnism is etter descried y the numer fluctution model nd the noise chrcteristics re minly determined y the STI effect in oth types of trnsistors studied here Asymmetricl devices Fig. 11 shows the normlized drin noise current spectrl densities for the symmetricl NMOS devices with SA = 0.6 lm (source side) nd SB =10lm (drin side) in the sturtion region, nd Fig. 12 shows the results for the devices with SA =10lm nd SB = 0.6 lm. As cn e seen, n ovious improvement of noise vrition nd the reduced G R noise ulges cn e otined when lrge source side extension (SA) ws used. Fig. 13 plots the noise current spectrl densities t 100 Hz for oth cses together. The results clerly indicted tht the trps locted in the source region hve more impcts on the flicker noise chrcteristics thn those / I 2 (Hz -1 ) Symmetricl PMOS / I 2 t 100Hz, V GS = -0.7 V / I 2 for different devices Averge Vlue SA=SB (μm) Fig. 10. The normlized noise current spectrl density /I 2 t f = 100 Hz for PMOS s function of the STI-to-gte distnce SA(SB). The devices were ised in the sturtion region under fixed of 0.7 V nd V GS = 0.7 V. The different points re for different devices with the sme W/L = 10/0.13 (N finger = 1).

5 1186 C.-Y. Chn et l. / Solid-Stte Electronics 52 (2008) / I 2 (Hz -1 ) Asymmetricl NMOS SA = 0.6μm, SB = 10μm Fig. 11. Normlized noise current spectrl density /I 2 for symmetricl 0.13 lm NMOS with SA = 0.6 lm (source side), SB =10lm (drin side) under of 0.7 V nd V GS. The different trces re for different devices with the sme W/ L = 10/0.13 (N finger = 1). shows tht the difference in these two cses (SA =10lm/ SB = 0.6 lm nd SA = SB = 10 lm) is not significnt. The oserved trend cn e explined s follows. Between the drin nd the pinch-off point in the chnnel, the crriers trvel with the sturtion velocity nd lso the verticl electric field is reltively smll. Therefore, the trpping detrpping process is not s pronounced nd the trps round the drin side re not s criticl s those locted in the source side. A similr explntion hs een given, while there were no corresponding experiments to verify this point [18,22]. In this study, the experimentl dt from the symmetricl lyouts provide direct proof on this point Sttistic model for the Flicker noise vrition To quntittively study the noise level vrition in different SA/SB spces, the following formuls re employed to nlyze the mesured dt. The reltive stndrd devition r db cn e clculted y [23 25] Tle 2 Noise vrition S + s function of the STI-to-gte distnces / I 2 (Hz -1 ) Asymmetricl NMOS SA = 10μm, SB = 0.6μm NMOS PMOS SA(SB) (lm) r db (db) S Mesured dt Error r Fig. 12. Normlized noise current spectrl density /I 2 for symmetricl 0.13 lm NMOS with SA =10lm (source side), SB = 0.6 lm (drin side) under of 0.7 V nd V GS. The different trces re for different devices with the sme W/L = 10/0.13 (N finger = 1). / I 2 (Hz -1 ) Asymmetricl NMOS / I 2 t 100Hz, V GS =0.7 V SA= 0.6 μm / SB = 10 μm / I 2 for different devices Averge Vlue SA= 10 μm / SB = 0.6 μm SA (μm) Fig. 13. Normlized noise current spectrl density /I 2 t f = 100 Hz for NMOS s function of the STI-to-gte distnces for symmetricl devices under of 0.7 V nd V GS. The different trces re for different devices with the sme W/L = 10/0.13 (N finger = 1). in the drin region. This cn e further identified y compring the results for devices with SA = SB =10lm s shown in Fig. 9, which (A 2 / Hz) (A 2 / Hz) Symmetricl NMOS SA = SB = 0.6 μm Mesurement dt Error r Symmetricl NMOS SA = SB = 10 μm Fig. 14. The noise current spectrl densities (solid line) nd the error rs (dotted line) for 0.13 lm NMOS with () SA(SB) = 0.6 lm, nd () SA(SB) =10 lm, using k = 2. The different trces re for different devices with the sme W/L = 10/0.13 (N finger = 1).

6 vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u 1 X r N db ¼ t ð;j db h idbþ 2 N 1 j¼1 where the,j db =10 log(,j ), j is the jth spectrum nd h i is the verge noise. The stndrd devition is n index of the noise diversion t ech frequency point (from 10 Hz to 10 KHz, totl 1081 frequency points in this cse). For NMOS devices with SA(SB) = 0.6 lm, 1.2 lm, nd 10 lm, the clculted r db were 5.95 db, 1.79 db, nd 1.83 db, respectively. For PMOS devices with SA(SB) = 0.6 lm, 1.2 lm, nd 10 lm, the clculted r db were 3.93 db, 2.24 db, nd 2.17 db, respectively. For simplified nlysis, the reltive noise level nd noise model cn e descried s follows ¼ K FI AF D f ð1 þ S Þ where S + nd S re the reltive noise vrition ove nd elow the verge noise h i, nd the noise vrition cn e expressed s [24] S ¼ 10 kr db =10 1 where the prmeter k is the selected confidence proility. In this work, the reltive vrition S + for different ises were clculted y using k = 2. The noise vrition S + is clculted with different SA(SB) vlues for NMOS nd PMOS s summrized in Tle 2. As cn e seen, significnt improvement of S + cn e oserved s SA(SB) incresed from 0.6 lm to 1.2 lm. Fig. 14 shows oth the mesured results (solid lines) nd the error rs (dotted line) for the three types of symmetricl NMOS devices under V GS of 0.7 V. As the technology keep scling down, n incresed discrepncy due to the impct of STI effect cn e expected in oth DC nd flicker noise chrcteristics. 4. Conclusion The geometry effect on DC nd flicker noise chrcteristics hve een studied for 0.13 lm CMOS trnsistors using oth symmetricl nd symmetricl lyouts with different SA(SB) distnces. A more pronounced G R noise nd higher noise level were oserved with decresed SA/SB distnces, which cn e ttriuted to the STI induced trps nd descried y the crrier numer fluctution model. The results from the symmetricl devices proved tht the trps round the source side hve more significnt impct on flicker noise chrcteristics compred with those in the drin side. In ddition, this study provides simple pproch to improve the device flicker noise. By properly extending the STI-to-gte distnce in the source side (SA > 1.2 lm), the noise level nd their vrition C.-Y. Chn et l. / Solid-Stte Electronics 52 (2008) ð3þ ð4þ ð5þ cn e reduced, which cn e very useful to design noise sensitive circuits nd locks such s oscilltors nd mixers. Finlly, the noise level vrition model provided quntittive nlysis of these devices, nd cn e employed in SPICE model for circuit design pplictions. Acknowledgements This work is supported y the Ntionl Science Council in Tiwn under contrct NSC E The uthors would lso like to express their grtitude towrds Professor J. Gong for helpful discussions nd the Ntionl Nno Device Lortories (NDL) for mesurement support. References [1] Sheu YM, Chng CS, Lin HC, Lin SS, Lee CH, Wu CC, et l. VLSI Tech Dig 2003:76 9. [2] Miymoto M, Oht H, Kumgi Y, Sonoe Y, Ishishi K, Tink Y. IEEE Trns Electron Devices 2004;51:440. [3] Gllon C, Reimold G, Ghiudo G, Binchi RA, Gwoziecki R, Rynud C. In: Proceeding of the ESSDERC; p [4] Scott G, Lutze J, Ruin M, Nouri F, Mnley M. IEDM Tech Dig 1999: [5] Ohguro T, Okym, Mtsuzw YK, Mtsung K, Aoki N, Kojim K, et l. In: Symposium on VLSI technology; p [6] Med S, Jin YS, Choi JA, Oh SY, Lee HW, Woo JY, et l. In: Symposium on VLSI technology; p [7] Chn CY, Jin JD, Lin YS, Hsu SH, Jung YZ. IEEE Trns Electron Devices 2007;54:3383. [8] Chn CY, Lin YS, Hung YC, Hsu SSH, Jung YZ. IEEE MTT-S Int. Sympos. Dig. 2007: [9] Prk H, Jones KS, Slinkmn JA, Lw ME. IEDM Tech Dig 1993: [10] Su KW, Sheu YM, Lin CK, Yng SJ, Ling WJ, Xi X, et l. In: Proceedings of the custom integrted circuits conference; p [11] Rim K, Hoyt JL, Gions FG. IEEE Trns Electron Devices 2000;47:1406. [12] McWorther AL. Semiconductor surfce physics. University of Pennsylvni Press; [13] Simoen E, Cleys C. Solid-Stte Electron 1999;43:865. [14] Ghiudo G, Boutchch T. Microelectron Reli 2002;42:573. [15] Vndmme LKJ, Li X, Rigud D. IEEE Trns Electron Devices 1994;41:1936. [16] Vndmme EP, Vndmme LKJ. IEEE Trns Electron Devices 2000;47:2146. [17] Vlenz M, Hoffmnn A, Sodini D, Ligle A, Mrtinez F, Rigud D. IEE Proc-Circ Dev Syst 2004;151:102. [18] Wirth GI, Koh J, Silv RD, Thewes R, Brederlow R. IEEE Trns Electron Devices 2005;52:1576. [19] Hung KK, Ko PK, Hu C, Cheng YC. IEEE Trns Electron Devices 1990;37:654. [20] Hooge FN. Phys Lett 1969;29A:139. [21] Ghiudo G, Roux-dit-Buisson O, Blestr F, Brini J. Phys Stt Sol () 1991;124:571. [22] Asgrn S, Deen MJ, Chen CH. IEEE Trns Electron Devices 2004;51:2109. [23] Deen MJ, Mrinov O, Onsongo D, Dey S, Bnerjee S. Proc SPIE 2004;5470:251. [24] Snden M, Mrinov O, Deen MJ, Ostling M. IEEE Trns Electron Devices 2002;49:514. [25] Snden M, Mrinov O, Deen MJ, Ostling M. IEEE Electron Devices Lett 2001;22:242.

The Influence of Interface and Semiconductor Bulk Traps Generated Under HEFS on MOSFET`s Electrical Characteristics

The Influence of Interface and Semiconductor Bulk Traps Generated Under HEFS on MOSFET`s Electrical Characteristics Proceedings of the 5th Smll Systems Simultion Symposium 2014, Niš, Seri, 12th-14th Ferury 2014 The Influence of Interfce nd Semiconductor Bulk Trps Generted Under HEFS on MOSFET`s Electricl Chrcteristics