EE194-EE290C. 28 nm SoC for IoT
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1 EE194-EE290C 28 nm SoC for IoT Ref: Communica:on Systems by A. Bruce Carlson, Paul B. Crilly and Janet C. Rutledge CMOS VLSI Design by Neil H. Weste and David Money Harris Timing Library Format Reference, Cadence Design System hsps:// Synopsys Design Compiler User Guide
2 Bit Synchroniza:on Carrier Frequency and Phase Frame Synchroniza:on Synchroniza:on
3 Synchroniza:on PN sequence generator. m 1 m 2 m 3 m 4 m Output sequence
4 Synchroniza:on Autocorrela:on of a PN sequence. R s (τ) 1 -T c T c (N-1)T c (N+1)T c 1/N NT c τ
5 Synchroniza:on Frame Synchroniza:on Preamble Start of message Message bits t
6 Synchroniza:on Frame Synchroniza:on/Preamble Detec:on... a K a K-1 a K-2 a K-N... c 1 c 2 c n Σ V K N v k = c i a k i i=1
7 Matlab Example openexample('comm/msksignalrecoveryexample') MSKSignalRecoveryExample
8 Transmission Gate Mux q Nonrestoring mux uses two transmission gates - Only 4 transistors S D0 D1 S Y S
9 D Latch q When CLK = 1, latch is transparent - D flows through to Q like a buffer q When CLK = 0, the latch is opaque - Q holds its old value independent of D q a.k.a. transparent latch or level-sensitive latch CLK CLK D Latch Q D Q
10 D Latch Design q Multiplexer chooses D or old Q D CLK 1 0 Q Q D CLK CLK CLK Q Q CLK
11 D Latch Opera:on Q Q D Q D Q CLK = 1 CLK = 0 CLK D Q
12 D Flip-flop q When CLK rises, D is copied to Q q At all other times, Q holds its value q a.k.a. positive edge-triggered flip-flop, master-slave flip-flop CLK CLK D D Flop Q Q
13 D Flip-flop Design q Built from master and slave D latches CLK D CLK QM CLK Q CLK CLK CLK CLK CLK D Latch QM Latch Q CLK CLK
14 D Flip-flop Opera:on D QM Q CLK = 0 D QM Q CLK = 1 CLK D Q
15 Race Condi:on q Back-to-back flops can malfunction from clock skew - Second flip-flop fires late - Sees first flip-flop change and captures its result - Called hold-time failure or race condition CLK1 CLK1 CLK2 CLK2 D Flop Q1 Flop Q2 Q1 Q2
16 Setup and Hold Time Voltage Clock Setup Time Hold Time Time
17 Non-overlapping Clocks q Non-overlapping clocks can prevent races - As long as non-overlap exceeds clock skew q We will use them in this class for safe design - Industry manages skew more carefully instead φ 2 φ 1 D QM Q φ 2 φ 2 φ 1 φ 1 φ 2 φ 1 φ 1 φ 2
18 Scan In Cell scan_in chip_in _int phi phib scan_i0o1 0 1 scan_i0o1 load phi phi_out phib_out D Q D Q phib scan_i0o1_out load_out scan_out _int scan_out scan_out_int load D Q chip_in_int chip_in
19 Scan Out Cell phi phib scan_i0o1 load phi_out phib_out scan_i0o1_out load_out scan_in 0 chip_out 1 phi scan_i0o1 D Q D Q phib scan_out
20 Scan In-Out Cell phi phib scan_i0o1 load scan_in 0 chip_out 1 phi scan_i0o1 phi_out phib_out D Q D Q phib scan_i0o1_out load_out scan_out _int scan_out scan_out_int load D Q chip_in_int chip_in
21 Gate Layout q Layout can be very time consuming - Design gates to fit together nicely - Build a library of standard cells q Standard cell design methodology - V DD and GND should abut (standard height) - Adjacent gates should satisfy design rules - nmos at bottom and pmos at top - All gates include well and substrate contacts
22 q Uniform cell height q Uniform well height q M1 V DD and GND rails q M2 Access to I/Os q Well / substrate taps q Exploits regularity Standard Cells
23 Coping With Complexity q How to design System-on-Chip? - Many millions (even billions!) of transistors - Tens to hundreds of engineers q Structured Design q Design Partitioning
24 Structured Design q Hierarchy: Divide and Conquer - Recursively system into modules q Regularity - Reuse modules wherever possible - Ex: Standard cell library q Modularity: well-formed interfaces - Allows modules to be treated as black boxes q Locality - Physical and temporal
25 Design Par::oning q Architecture: User s perspective, what does it do? - Instruction set, registers - MIPS, x86, Alpha, PIC, ARM, q Microarchitecture - Single cycle, multi-cycle, pipelined, superscalar? q Logic: how are functional blocks constructed - Ripple carry, carry look-ahead, carry select adders q Circuit: how are transistors used - Complementary CMOS, pass transistors, domino q Physical: chip layout - Datapaths, memories, random logic
26 HDL q Hardware Description Languages - Widely used in logic design - Verilog and VHDL q Describe hardware using code - Document logic functions - Simulate logic before building - Synthesize code into gates and layout Requires a library of standard cells
27 Verilog Example module fulladder(input a, b, c, output s, cout); a b a b c sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule cout s c fulladder carry sum module carry(input a, b, c, output cout) cout s assign cout = (a&b) (a&c) (b&c); endmodule
28 Circuit Design q How should logic be implemented? - NANDs and NORs vs. ANDs and ORs? - Fan-in and fan-out? - How wide should transistors be? q These choices affect speed, area, power q Logic synthesis makes these choices for you - Good enough for many applications - Hand-crafted circuits are still better
29 Example: Carry Logic q assign cout = (a&b) (a&c) (b&c); a b a c b c g1 g2 g3 x y z g4 cout a a p1 c c n1 b p3 n3 b p2 i3 i1 n2 b a a b p4 i4 p5 cn n5 i2 n4 p6 n6 cout Transistors? Gate Delays?
30 Gate Level Netlist module carry(input a, b, c, output cout) wire x, y, z; and g1(x, a, b); and g2(y, a, c); and g3(z, b, c); or g4(cout, x, y, z); endmodule a b a c b c g1 g2 g3 x y z g4 cout
31 Transistor Level Netlist module carry(input a, b, c, output cout) wire i1, i2, i3, i4, cn; tranif1 n1(i1, 0, a); tranif1 n2(i1, 0, b); tranif1 n3(cn, i1, c); tranif1 n4(i2, 0, b); tranif1 n5(cn, i2, a); tranif0 p1(i3, 1, a); tranif0 p2(i3, 1, b); tranif0 p3(cn, i3, c); tranif0 p4(i4, 1, b); tranif0 p5(cn, i4, a); tranif1 n6(cout, 0, cn); tranif0 p6(cout, 1, cn); endmodule a a p1 c c n1 b p3 n3 b p2 i3 i1 n2 b a a b p4 i4 p5 cn n5 i2 n4 p6 n6 cout
32 SPICE Netlist.SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF.ENDS
33 q Floorplan q Standard cells - Place & route q Datapaths - Slice planning q Area estimation Physical Design
34 MIPS Floorplan
35 MIPS Layout
36 Synthesized Controller q Synthesize HDL into gate-level netlist q Place & Route using standard cell library
37 Design Verifica:on q Fabrication is slow & expensive q Debugging chips is very hard - Limited visibility into operation q Prove design is right before building! - Logic simulation - Ckt. simulation / formal verification - Layout vs. schematic comparison - Design & electrical rule checks q Verification is > 50% of effort on most chips! Specification Architecture Design Logic Design = = Function Function = Function Circuit Design = Function Timing Power Physical Design
38 VLSI Flow q Design Compiler (DC) Synopsys tool Design Compiler op:mizes designs to provide the smallest and fastest logical representa:on of a given func:on. It comprises tools that synthesize your HDL descrip:ons into op:mized, technology-dependent, gate-level designs.
39 DC Converts a design descrip:on wrisen in a HDL, into an op:mized gate-level netlist mapped to a specific logic library. When the synthesized design meets func:onality, :ming, power, and other design goals, you can pass the design to IC Compiler for physical implementa:on.
40 Liberty Timing File(LIB) The.lib file is an ASCII representa:on of the :ming and power parameters associated with any cell in a par:cular semiconductor technology. The :ming and power parameters are obtained by simula:ng the cells under a variety of condi:ons and the data is represented in the.lib format. The.lib file contains :ming models and data to calculate: I/O delay paths Timing check values Interconnect delays I/O path delays and :ming check values are computed on a per-instance basis. Path delays in a circuit depend upon the electrical behavior of interconnects between cells. This parasi:c informa:on can be based on the layout of the design, but must be es:mated when no layout informa:on is available. Also it is not possible to predict the process, voltage and temperature varia:ons and dera:ng factors can be included to compensate for these varia:ons.
41 Liberty Timing File(LIB) Cell-based delay calcula:on is modeled by characterizing cell delay and output transi:on :me (output slew) as a func:on of input transi:on :me (input slew) and the capaci:ve load on the output of the cell. Timing checks are also func:ons of input slew and output capaci:ve load. Each cell has a specific number of input-to-output paths A B C Z Path delays can be described for each input signal transi:on that affects an output signal The path delay can also depend on signals at other inputs (state dependencies) In many sequen:al cells, the path delay from an input pin to an output pin can depend on the path delay from another output pin to this output pin
42 Liberty Timing File(LIB) Cell-based delay calcula:on is modeled by characterizing cell delay and output transi:on :me (output slew) as a func:on of input transi:on :me (input slew) and the capaci:ve load on the output of the cell. Timing checks are also func:ons of input slew and output capaci:ve load. Each cell has a specific number of input-to-output paths A B C Z Path delays can be described for each input signal transi:on that affects an output signal The path delay can also depend on signals at other inputs (state dependencies) In many sequen:al cells, the path delay from an input pin to an output pin can depend on the path delay from another output pin to this output pin
43 Liberty Timing File(LIB) Delay,Power, Timing Checks Input Slew Output Capacitance Lookup-table (non-linear delay) model.
44 Liberty Timing File(LIB) Delay,Power, Timing Checks Input Slew Output Capacitance Lookup-table (non-linear delay) model.
45 Parameter Varia:on q Transistors have uncertainty in parameters Process: L eff, V t, t ox of nmos and pmos Vary around typical (T) values q Fast (F) L eff : short V t : low t ox : thin q Slow (S): opposite q Not all parameters are independent for nmos and pmos slow fast pmos SF SS TT FF FS slow nmos fast
46 Environmental Varia:on q V DD and T also vary in time and space q Fast: V DD : high T: low Corner Voltage Temperature F C T C S C
47 Process Corners q Process corners describe worst case variations - If a design works in all corners, it will probably work for any variation. q Describe corner with four letters (T, F, S) - nmos speed - pmos speed - Voltage - Temperature
48 Important Corners q Some critical simulation corners include Purpose nmos pmos V DD Temp Cycle time S S S S Power F F F F Subthreshold leakage F F F S
49 Design Objects
50 Top Level Par::oning
51 Design Environment Before a design can be op:mized, you must define the environment in which the design is expected to operate. You define the environment by specifying opera:ng condi:ons, system interface characteris:cs, and wire load models. Opera:ng condi:ons include temperature, voltage, and process varia:ons. System interface characteris:cs include input drivers, input and output loads, and fanout loads. The environment model directly affects design synthesis results.
52 Drive Characteris:cs To determine the delay and transi:on :me characteris:cs of incoming signals, Design Compiler needs informa:on about the external drive strength and the loading at each input port. Drive strength is the reciprocal of the output drive resistance, and the transi:on delay at an input port is the product of the drive resistance and the capacitance load of the input port. Design Compiler uses drive strength informa:on to buffer nets appropriately in the case of a weak driver. By default, Design Compiler assumes zero drive resistance on input ports, meaning infinite drive strength.
53 Drive Characteris:cs By default, Design Compiler assumes zero capaci:ve load on input and output ports.
54 Wire Load Models Wire load models es:mate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Design Compiler uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on sta:s:cal informa:on specific to the vendors process. The models include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for es:ma:ng net lengths (the number of fanouts determines a nominal length).
55 Design Rule Constraints
56 Design Rule Constraints
57 Fabrica:on & Packaging q Tapeout final layout q Fabrication - 6, 8, 12 wafers - Optimized for throughput, - not latency (10 weeks!) - Cut into individual dice q Packaging - Bond gold wires from die I/O pads to package
58 Tes:ng q Test that chip operates - Design errors - Manufacturing errors q A single dust particle or wafer defect kills a die - Yields from 90% to < 10% - Depends on die size, maturity of process - Test each part before shipping to customer
59 MIPS R3000 Processor q 32-bit 2 nd generation commercial processor (1988) q Led by John Hennessy (Stanford, MIPS Founder) q KB Caches q 1.2 µm process q 111K Transistors q Up to MHz q 66 mm 2 die q 145 I/O Pins q V DD = 5 V q 4 Watts q SGI Workstations
60 Transistor as Switches q We can view MOS transistors as electrically controlled switches q Voltage at gate controls path from source to drain g = 0 g = 1 nmos g d s d s OFF d s ON pmos g d s d s ON d s OFF
61 CMOS Inverter A Y 0 1 V DD 1 0 A Y A Y GND
62 CMOS NAND Gate A B Y Y A B
63 CMOS NOR Gate A B Y A B Y
64 Complementary CMOS q Complementary CMOS logic gates - nmos pull-down network - pmos pull-up network - a.k.a. static CMOS pmos pull-up network inputs output Pull-up OFF Pull-down OFF Z (float) 1 Pull-up ON nmos pull-down network Pull-down ON 0 X (crowbar)
65 Series and Parallel q nmos: 1 = ON q pmos: 0 = ON q Series: both must be ON q Parallel: either can be ON (a) g1 g2 a b a a a a b b b b OFF OFF OFF ON a a a a a g g2 b 0 b 1 b 0 b 1 b (b) ON OFF OFF OFF a a a a a g1 g b b b b b (c) OFF ON ON ON a a a a a g1 g b b b b b (d) ON ON ON OFF
66 Conduc:on Complement q Complementary CMOS gates always produce 0 or 1 q Ex: NAND gate - Series nmos: Y=0 when both inputs are 1 - Thus Y=1 when either input is 0 - Requires parallel pmos q Rule of Conduction Complements - Pull-up network is complement of pull-down - Parallel -> series, series -> parallel A B Y
67 Signal Strength q Strength of signal - How close it approximates ideal voltage source q V DD and GND rails are strongest 1 and 0 q nmos pass strong 0 - But degraded or weak 1 q pmos pass strong 1 - But degraded or weak 0 q Thus nmos are best for pull-down network
68 Pass Transistors q Transistors can be used as switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degraded 1 g s g = 0 d Input g = 0 Output 0 degraded 0 s d s g = 1 d 1 g = 0 strong 1
69 Transmission Gates q Pass transistors produce degraded outputs q Transmission gates pass both 0 and 1 well a g gb b g = 0, gb = 1 a b g = 1, gb = 0 a b Input Output g = 1, gb = 0 0 strong 0 g = 1, gb = 0 1 strong 1 a g b a g b a g b gb gb gb
70 Tristates q Tristate buffer produces Z when not enabled EN A Y 0 0 Z 0 1 Z A EN Y A EN Y EN
71 Non-restoring Tristate q Transmission gate acts as tristate buffer - Only two transistors - But non-restoring Noise on A is passed on to Y EN A Y EN
72 Tristate Inverter q Tristate inverter produces restored output - Violates conduction complement rule - Because we want a Z output A A A EN EN Y Y Y EN = 0 Y = 'Z' EN = 1 Y = A
73 Mul:plexers q 2:1 multiplexer chooses between two inputs S D1 D0 Y S 0 X X X 0 D0 D1 0 1 Y 1 1 X 1
74 Gate-Level Mux Design q How many transistors are needed? 20 Y = SD + SD 1 0 (too many transistors)
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