Clocking Strategies and Scannable Latches for Low Power Applications

Transcription

1 locking trtegies nd cnnle Ltches for Low Power pplictions V. Zyun nd. eltzer eserch ivision, T.J. Wtson eserch enter, Yorktown Heights, NY 598 (. eltzer is now with Epson eserch nd evelopment, NY) strct This pper covers rnge of issues in the design of clocking schemes for low-power pplictions. First we revisit, extend nd improve the power-performnce optimiztion methodology for ltches, ttempting to mke it more forml nd comprehensive. t switching fctor nd the glitching ctivity re tken into considertion, using forml nlyticl pproch, then notion of energy-efficient fmily of configurtions is introduced to mke the comprison of different ltch styles in the power-performnce spce more fir, lso the power of the clock distriution is tken into ccount. Prcticl issues of uilding low overhed scn mechnism re considered, nd the power overhed of the scnnle design is nlyzed. low-power L extension to single-phse ltches is proposed, nd results of comprtive study of Lscnnle ltches re shown, supported y experimentl dt mesured on 0:8 test chip. ntroduction ince the importnce of designing low-power high performnce clocking schemes hs een recognized, numer of low-power ltch studies hve een pulished [9,, 8,, 6,,, 5, 4]. Vrious ltch styles hve een compred in the power-performnce design spce, numer of useful criteri hve een introduced, nd severl new low-power ltches hve een suggested. This pper improves the existing power-performnce optimiztion methodology in severl spects. First the methodology is formlized y using nlyticl formuls to tke into ccount oth dt switching ctivity nd the glitching fctor, sed on []. forml optimiztion of every ltch style in the power-performnce spce is performed efore compring different ltch styles through constructing energy-efficient fmilies of configurtions for every ltch. The importnce of the ltch sclility with respect to lowering supply voltge is emphsized y treting s prmeter, rther thn constnt. Power of the clock distriution network is nlyzed, nd the single-phse clocking scheme is compred with twophse clocking. numer of prcticl issues of uilding ltches hve een missing in mny cdemic studies. One of them is the testility issue, prticulrly, the scn mechnism. t the sme time the power overhed of the scnnle design cn e very significnt, nd the complexity of modern designs hs reched the point where sving power y implementing non-scnnle design is not vile. n this work we propose low power overhed scn mechnism for single phse ltches, nd compre it with other pproches in terms of power. Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distriuted for profit or commercil dvntge nd tht copies er this notice nd the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior specific permission nd/or fee. LPE 0, ugust 6-7, 00, Huntington ech, liforni, U. opyright /0/ $5.00 Experimentl verifiction of the ides is ecoming incresingly importnt s the technology moves to the deep su-micrometer region, ecuse it is getting more nd more difficult to tke into ccount in simultions ll second order effects of the technology. n this pper we present experimentl results for low-power ltches uilt on stte-of-the rt technology. Optimiztion nd comprison methodology. Performnce esurement The stte of the rt methodology for compring the performnce of different ltches consists in evluting the following metric [8], sed on simultion of the switching of the ltch for vrying vlues of the dt setup time: T setup +! = min[t ;to; +mx( 0!!0)] where T setup is the setup time, nd! is dely through the ltch, mesured from the pproprite trnsition t the clock input nd the corresponding trnsition t the ltch output. n the formul the mx chooses the mximum dely etween the positive nd negtive trnsitions, nd the min chooses the smllest vlue of the sum for ll vlues of the dely etween the trnsitions t the dt nd clock inputs, T ;to;, s shown in Fig.. For this ltch the minimum vlue for the sum is reched when the dely etween the dt nd clock trnsitions is T ;to; =30ps, nd the dely through the ltch t this point is mx( 0!!0) = 80ps. Thus, we put for this ltch T setup +! = 30ps + 80ps =4ps. ll delys re mesured ssuming lod of four minimum size inverters. dely, ns > 0. >0 + to T, ns to Figure : Evlution of the performnce metric.. Power esurement significnt ostcle in clculting power directly y simultion is tht power dissiption is strongly pttern dependent. For exmple, in ltch the power depends on the verge numer of trnsitions t the dt input, s well s their time positions. The stte of the rt 346

2 methodology used y other uthors typiclly estimtes the power of ltch for two vlues of the switching ctivity t the dt input: = 0 nd =, nd then estimtes the verge power s liner comintion of the power under these extreme cses, with the weights depending on the dt switching fctor. The spurious switching ctivity, or glitching t the dt input is typiclly either neglected or dded in n d hoc mnner. n our study we used more forml pproch developed in [] which models the circuit s directed grph, clled the stte trnsition digrm, T [3, 7], such tht there is one-to-one correspondence etween edges in the grph nd power-dissipting events in circuit Tle : echle sttes in the T of the modified ltch. nd 0 designte voltge levels t the nodes of the circuit. node stte nme ,, G H To construct T for ltch we uild stte tree using the stte tree lgorithm []. n the first row we drw one circle for ech comintion of voltge vlues t the input nodes. n the second row we specify ll nodes whose voltges re uniquely specified given the voltge vlues t the nodes in the first row. Then the tree rnches, ech rnch corresponding to the stte of some node whose voltge vlue is so fr independent of those t ll nodes in this rnch ove it. n the next row, gin, we write ll nodes whose sttes re uniquely specified given the voltges t the nodes in the rnch ove them. This repets until ll nodes re specified. s n exmple, Tle shows ll rechle sttes for the modified sense mplifier ltch, shown in Fig. 3. The modifiction of the ltch consists in interchnging input to the NNs in the second stge, so tht the signl is connected to the lower input nd the signl to the upper input of the corresponding NN gtes. The result of this modifiction is tht the cpcitnce chrged/dischrged on the slower :! 0 trnsition is minimized t the expense of somewht higher cpcitnce chrged/dischrged on the other trnsition. Though simple modifiction, it results in 5% dely reduction, compred to the configurtion where oth nd signls re connected to the lower inputs of the NN gtes, nd in 3% dely reduction compred to the configurtion where oth nd signls re connected to the upper inputs of the NN gtes. The ility to do this sort of nlysis esily is nother reson for using the T nlysis. fter ll sttes hve een specified, we uild T y strting with one stte tht is oviously rechle. For every stte in the grph we find two other sttes rechle from it vi edges corresponding to trnsitions t the clock nd dt inputs. This process is repeted until oth edges leving every node enter sttes tht hve lredy een counted. The T for the modified ltch is shown in Fig., with the sttes designted in Tle. To simplify the explntion in this section, we will merge the sttes in Fig. tht differ only y the voltge levels t nodes G nd H. Then sttes with n index in Fig. merge with those tht hve index, reducing the T to simpler one, shown in Fig.. For our lyout of the ltch the cpcitnces t nodes H nd G re out 8 times smller thn those t nodes nd, mking the simplifiction quite resonle. till, the methodology cn e crried out Figure : tte trnsition digrm of the modified sense mplifier ltch (); simplified T (). without ny simplifying ssumptions, nd ll results presented in this pper re sed on the full nlysis of the T for every ltch. t is importnt to emphsize tht we ttriute the power dissipted for chrging/dischrging cpcitnces t the clock nd dt inputs to the ltch itself, rther thn to fn-in gte or the clock distriution tree. t is importnt tht the input cpcitnce of the wiring within the ltch lyout e included. imilrly, we do not include the power dissipted for chrging/dischrging the lod driven y ltch into ltch power. However, the output cpcitnce of the wiring within the ltch lyout must e included. uch convention mkes the power comprison etween different ltches more fir, however this lso mkes the T more complicted compred to those pulished in other works. Energy weights for every edge in the T re clculted using n nlog simultor or, for rough estimtes, mnully, using the formul P iv dd4v, where P i is the sum of cpcitnces t ll nodes tht hve different voltge levels in the sttes connected y the edge. Then, sed on the proilistic nlysis of the T, presented in [], nlyticl formuls re derived for the power of ltch tht express ltch power in terms of true nd spurious switching ctivities t the dt input. where P true = f( 0 + P + ) () 0 = E 00 = E ; E 00 = (E0 + E ; E00 ; E) n these formuls is the switching ctivity s defined in [], P is the proility of ltching, E mn re energy weights of pths p mn m n = f0 g in the grph tht re trversed when m ws ltched in the previous clock cycle nd the dt hs chnged to n (or hs not chnged if m = n). For the simplified T in Fig. some of the pths re p 0 = fs 3! s 6! s 5! s g, p = fs! s 8! s 7! s 3g, p 00 = fs 3! s 6! s 3g, nd p = fs! s 8! s g. The pth energy weight is otined y summing energy weights of ll edges long it. For ccurte estimtes, we simulte the ltch, using n input pttern tht cuses the ltch to go through every single edge in the T, nd energy weights re mesured y the simultor. t turns out tht every term in power formuls includes only energies dissipted on complete cycles in the T, which llows us to mesure these energies y integrting the current of the power supply, in cse the simultor does not support the mesurements of the instntneous power. n the presence of the spurious ctivity t the dt input formul similr to () is derived in [] tht is vlid for ll resonle 347

3 G H Figure 3: Trnsistor digrms: modified sense mplifier ltch, true single phse ltch. ltches known to the uthors: P totl = 0P true + f h E cycle + E cycle + ( ; 0)( P ) i ().3 Tuning Trnsistor izes efore compring it with other ltches, every ltch must e optimized for power-performnce metric, in order to mke sure tht the est configurtions of every ltch re compred. However, it turns out tht it is virtully impossile to come up with single metric tht would e fir for every ltch some ltches re more suitle for high-speed designs, others for low-power, ut slower designs. To void this uncertinty, we uilt for every ltch n energyefficient fmily of configurtions, which is fmily of configurtions, otined y optimizing ltch to minimize the cost function (E=E 0) +(;)(= 0) for ll vlues of the optimiztion prmeter in the rnge 0. Here, is the sum of the setup time nd the dely through the ltch, s defined in section., nd E is the verge energy dissipted y the ltch in one clock cycle, determined ccording to section.. This cost function ws used ecuse it resulted in consistent convergence of the circuit tuner. Thus, every configurtion in the energy-efficient fmily is the one tht results in the highest performnce mong ll configurtions dissipting the sme power, or the one tht dissipted the lest power mong ll configurtions tht deliver the sme performnce. f plotted in the power-versus-performnce coordintes, energy-efficient configurtions form convex hull of ll possile configurtions of given ltch, Fig.4. 0 enery efficient fmily ll configurtions where 0 P 0 = p E ij ;E cycle, 0 P = 00 p E ij ; P p E ij, P 00 0 P = p E ij + 0 p E ij ; P p E ij ; P 00 p E ij. Here P true is the verge power in the sence of glitches, clculted y (), the verge numer of spurious pulses during one clock cycle clculted s P = k k, where k is the proility tht k spurious pulses occur during one clock cycle. n mny ltches spurious pulses occurring when clock is high dissipte more (or less) energy thn those occurring when clock is low. This is ccounted y the term Ecycle, where is the verge numer of spurious pulses per cycle occurring while clock is high. n the ove formuls p k ij denote pth in T trversed when i ws ltched in the previous clock cycle nd the true dt vlue hs chnged to j (or hs not chnged if i = j) nd when k spurious pulses occurred in this clock cycle. n the ove formul the summtion of the energy weights is tken long such pths. For exmple, in Fig., p 00 = fs 3! s 6! s 5! s 6! s 3g, nd p 0 = fs 3! s 6! s 5! s 6! s 5! s g. E cycle is the energy dissipted y one spurious pulse, provided tht t lest one spurious pulse hs occurred efore it. For the T in Fig., E cycle is the energy dissipted on the cycle p cycle = fs 6! s 5! s 6g, or p cycle = fs 8! s 7! s 8g, nd E cycle is the energy dissipted on the cycle p cycle = fs 3! s! s 3g, orp cycle = fs! s 4! s g. There is one more cycle in the T in Fig., p cycle = fs 3! s! s 3 g,orp cycle = fs! s 4! s g, ut it hs the sme energy. Thus, the verge totl ltch power in () is sum of the true portion multiplied y the proility tht no spurious pulses occur during one clock cycle, 0, nd the spurious portion which depends on three prmeters: nd the verge numer of spurious pulses per cycle, when clock is low nd high, respectively, nd 0. The term f( ; 0)( P ) ccounts for the the difference etween the energies dissipted y the first nd susequent spurious pulses. For mny ltches (which is the cse for the T in Fig. ), it cncels h with 0P true, ndithe expression reduces to P 0 totl = P true + f E cycle + E cycle. POWE, uw/ghz T + T, ps ETUP Figure 4: uilding energy-efficient fmily for ltch. Hving uilt energy-efficient fmilies for every ltch llows us to compre different ltches over the whole energy-performnce design trdeoff spce, rther thn compring prticulr configurtions of every ltch. lock istriution Power When compring different ltches for energy efficiency it is essentil tht the power dissipted in the clocking tree e tken into ccount, ecuse different ltches present different requirements s well s different mounts of cpcitive lod on the clock distriution network. oreover, some ltch styles require two clock phses, while others use only one phse. To evlute the effect of the power of the clock distriution tree on the ltch energy efficiency, we simulted clock distriution tree for 3-it dtpth ltch, with trck it step, using 0:8 technology with set to V. When clculting the cpcitive lod presented y ltch to the clock distriution network, it is importnt to include the cpcitnce of the clock wiring inside the ltch cell. We found tht for ltch design using very smll trnsistor sizes, the internl wiring my represent from 5% to 0% of the totl cpcitive lod on the clock. 348

4 The simulted circuitry included clock splitter tht genertes two non-overlpping clock phses nd distriution network feeding every ltch. Trnsistor sizes in the clock drivers were set to the miniml sizes tht re needed to gurntee tht the slope t every node in the clock distriution network is no more thn 0ps. The simultion results showed tht the whole simulted clock distriution network dissiptes 40fJ per clock cycle, of which 0fJ is dissipted for driving the wire cpcitnce nd ltch input cpcitnce, nd 40fJ is dissipted in clock drivers. ivided y 3 ltches in the simulted structure, this yields 7.5fJ per ltch per clock cycle. Note tht the power dissipted for driving the cpcitnce t the clock input of the ltch is counted s power dissipted in the ltch, rther thn in the distriution tree. Tking this into ccount yields n estimte of 6.5fJ per ltch per clock cycle overhed for distriuting one clock phse. The overhed for distriuting two clock phses is 3fJ per ltch per clock cycle, which is comprle to the energy dissipted within the ltch itself, if the ltter is uilt using very smll trnsistor sizes. This nlysis indictes tht in low power design which uses very smll trnsistors, ltch tht cn work with single phse of the clock hs 30% power dvntge over ltch tht requires two phses for roust opertion. 3 cnnle ltches The integrtion nd complexity of modern systems hs grown to the point where sving power y uilding non-scnnle design is no longer n option. The power overhed of the scnnle design my e very significnt. For exmple, the study in [] hs reported 54% increse in power of n L stndrd cell design over the identicl non-scnnle design. However, the effect of scnnle design on power hs not received sufficient ttention in recent works on low-power ltches. n this work we try to fill this gp y nlyzing the power overhed of existing pproches to uilding scnnle ltches nd proposing new, low power overhed L comptile extension to edge-triggered ltches. There exist two mjor pproches to uilding scnnle designs: edge-triggered nd level sensitive, L scn. ecuse the L scn is rce free, it is more roust thn the edge-triggered scn, nd it preserves the integrity of the scn chin even in the presence of significnt clock skews []. For this reson L is the scn mechnism of our choice. P P Figure 5: L trnsmission gte ltch (ove) nd NO ltch (elow). The stndrd wy of implementing n L mster-slve ltch is shown in Fig. 5 for the trnsmission-gte ltch (clled PowerP ltch in [8]), nd NO ltch (clled O ltch in [8]). n these ltches the power overhed of the scn is quite smll only drin cpcitnces of trnsistors nd P (which re cut off) re chrged/dischrged during the norml opertion mode. However, these ltches require two phses of clock, nd, in the norml opertion mode, which, ccording to ection, increses the totl power of the clocking system y 30%. n order to void the power penlty of the second clock phse, the ltch should operte with single clock phse during the norml mode, nd during the scn mode it should operte s mster-slve ltch with two non-overlpping clock phses, s required y the L stndrd. Fig. 6 shows the proposed L extension to the sense mplifier ltch tht hs this property. O O N scn ltch N3 N4 cn N3 E N5 Figure 6: cnnle sense mplifier ltch: proposed L scnnle ltch, prior rt [6] edge-triggered scnnle ltch. The result is chieved y mixing in the scn-in dt t the second stge of the ltch, - stge. The scn-in dt signl, is written to the - stge of the ltch through trnsistors nd N, or N nd N4. High level of clock enles the scn-in write opertion. The scn ltch in Fig. 6 is level sensitive ltch controlled y clock. uring the scn mode the clock is kept t the low level, nd the - stge of the ltch nd the scn ltch work s mster-slve ltch, controlled y clocks nd, s required y L. uring the norml opertion mode clocks nd re kept t the low level, nd the ltch opertes s the conventionl ltch. The power overhed of the proposed scn extension is reduced to the drin cpcitnce of two minimum-sized trnsistors nd N3, connected to the output nodes nd. This extr cpcitnce is chrged or dischrged t most once per clock cycle, nd is not ffected y spurious trnsitions t the dt input. Thus, the power overhed of the scn extension is 4P = f where is the drin cpcitnce of trnsistors nd N3 in Fig. 6, nd is the true switching ctivity t the dt input. prior rt edge-triggered scnnle version of the ltch [6] is shown in Fig. 6. uring the norml mode of opertion the input N4 N F N6 349

5 Tle : Power overhed of dding scn the ltch. pproch energy overhed vlue vlue for V dd =v formul =0:3 =0:3 prior rt V dd (V dd ; V T )4 4.7 ff.0 fj mux-sed ( + )V dd mux 5. ff 4.6 fj proposed V dd. ff 0.3 fj signl cn is low, nd the current flows through trnsistors or N, controlled y the input dt signls nd. uring the scn mode the signl cn is high, nd the current flows through trnsistors N3 or N4, controlled y the scn-in signls nd. This implementtion of the scn-in cpility hs very high power overhed, ecuse it significntly increses cpcitnce t the ottom prt of the ltch (nodes,, E, F nd ). ince these nodes re chrged nd dischrged every clock cycle, independent of the switching ctivity, the increse in power dissiption equls 4P = f (; V T ) 4 where 4 is the increse of the cpcitnce t nodes,, E, F nd in Fig. 6. n lterntive implementtion of the scn cpility y mens of multiplexing the input nd scn-in dt degrdes the performnce of the ltch y incresing the setup time, moreover, it leds to n increse of the the power dissiption which is proportionl to the sum of the input dt switching ctivity nd glitching fctor, 4P 3 = f mux ( + ) where mux is the cpcitnce of the multiplexor t the input, is the input dt switching ctivity, nd is the glitching fctor t the dt input. sed on cpcitnce vlues for 0:3 technology, Tle estimtes the power overhed of dding the scn feture to the ltch using the two prior rt pproches nd the proposed pproch. The fourth column gives the energy overhed estimtes for typicl vlues of the dt switching ctivity nd the glitching fctor. The Tle shows tht the proposed L extension reduces the energy overhed of the scnnle ltch times (which could e even more in high glitching nodes), compred to the input multiplexed design, nd 37 times, compred to the prior rt design in Fig. 6. Under the sme conditions the full sense mplifier ltch in Fig. 6 dissiptes out 8.5fJ per clock cycle. Thus, using the proposed pproch results in more thn 50% power svings in the scnnle ltch, nd out 30% svings in the totl ltch power, including the clock distriution tree. n terms of the effect on the ltch performnce, the proposed scn extension hs pproximtely the sme decrese in performnce s the prior rt pproch in Fig. 6, nd significntly smller decrese in performnce thn the multiplexor-sed pproch. The proposed L extension cn e used with mny other single phse ltches, including those descried in []. 4 omprtive study We hve done comprtive study of lrge numer of different ltch styles to identify the ones tht re most suitle for low power design. ince the power supply reduction is essentil for reducing power, we primrily focused on sttic nd semi-sttic ltches ecuse of their higher noise mrgin. lso, since reduction plys such n importnt role, we were prticulrly interested in those ltches whose performnce degrdes the lest s is reduced. n this pper we show results only for four ltch styles: L scnnle NO nd trnsmission gte ltches, Fig. 5, proposed L sense mplifier ltch, Fig 6 nd semi-sttic true single phse ltch, Fig 3, derived from []. The optimiztion descried in ection ws pplied to every ltch. The optimiztion prmeter ws chnged in the rnge from 0. to 0.9 to generte the energy efficient curve for ech ltch for =0.9V. ulk technology ws used with 0:3 feture size. The power nd performnce of the tuned ltch were mesured s descried in ection. Then ll energy efficient configurtions of every ltch were simulted for lower vlues of, =0.8V nd =0.7V. No dditionl tuning ws done, however. The results re shown in Fig. 7, for the ctivity fctor of 0.3 trnsitions per cycle, nd the spurious ctivity of 0.5 glitches per cycle. ENEGY PE YLE, fj NO 09V TG 09V TG 08V TG 07V 09V 08V 07V 0.9V 0.8V 0.7V T ETUP + T, ps Figure 7: verge energy per cycle versus performnce. witching fctor = 0:3, glitching ctivity = 0:5 ( = 0: = 0:0 3 = 0:005). olid lines connect points of energy efficient configurtions for every vlue of. Extensive use of clock gting effectively increses the switching fctor nd the glitching ctivity. Fig. 8 plots the verge energy per cycle of the sme ltches for higher vlue of the switching nd glitching ctivities. Low power consumption of the L sense mplifier ltch even in the presence of significnt glitching ctivity, s well s its ility to operte with reduced swing signls mke it very good cndidte for low power designs. 5 Experimentl dt test site ws constructed in n experimentl 0.8 micron O process to investigte the ility of single clock sense mplifier style ltches uilt of very smll width devices to cpture dt with poor slew rtes nd low. The true/complement input sense mplifier style ltch ws modified for single ended input in two versions s shown in Fig. 9. The first version used gte input with n dded inverter of minimum size devices to drive the opposite gte. The second version used mixed gte plus source input. The input ws connected to four.6mm wires with 6 tristte drivers distriuted long ech wire. The driver dt nd selects re controlled y scn ltch chin nd the output of the sense mplifier ltch is oserved t the pds. The experiment mesured the mximum frequency t which the ltch could cpture lternting ones nd zeroes inserted t the end of the long wire versus. ecuse the solute frequency is proportionl to oth the lrge wire dely nd the setup+hold time of the ltch, the results of the experiment re presented in reltive terms. Figure shows the results over the voltge rnge equl to 0.55V to.5v. oth circuits operted 350

6 ENEGY PE YLE, fj NO 09V TG 09V TG 08V TG 07V 09V 08V 07V 0.9V 0.8V 0.7V rtio: gte input design / mixed input design mx frequency rtio energy rtio T ETUP + T, ps (volts) Figure : Ltch comprison experiment: gte-input (Fig. 9) versus mixed-input designs (Fig. 9). Figure 8: verge energy per cycle versus performnce. witching fctor =0:5, glitching ctivity =0:55 ( =0: = 0: 3 =0:05). olid lines connect points of energy efficient configurtions for every vlue of. Figure 9: Ltches on the test chip: gte input ltch, mixed input ltch. over the full voltge rnge, including the extreme low voltge corresponding to V TP +V TN. The conventionl gte input showed etter setup+hold time s well s lower energy. 6 onclusions Power-performnce optimiztion methodology for ltches ws extended to formlly prmeterize ltch power in terms of switching fctor nd glitching ctivity. The concept of energy efficient fmily of configurtions ws introduced nd used for forml comprison of different ltch styles in the power-performnce spce. lock distriution power ws found to e significnt component of the totl power of the clocking system in low-power designs, nd ltches using single clock phse were found to dissipte 30% less power thn those requiring two phses of clock. Prcticl issues of uilding low power overhed scn mechnism were considered, nd low-power L extension to single-phse ltches ws proposed nd demonstrted to significntly reduce the power overhed of L design. esults of comprtive study of L ltches re shown, nd the modified sense mplifier ltch with the proposed L extension ws found to e very strong cndidte for low-power designs. esults re supported y experimentl dt mesured on 0:8 test chip which showed roust opertion of the sense mplifier ltch uilt of very smll width devices over the full voltge rnge. Gte-input version of the sense mplifier ltch ws found to e oth fster nd lower-power thn the mixed-input vrition. cknowledgment The uthors would like to thnk. Kosonocky, K. hin,. Hen,. Kneel nd W. Hwng for useful discussions;. mmedito for mesuring experimentl dt; G. Gristede for tool support; nd K. Wrren nd J. oreno for mngement support. eferences []. Fris. ircuit design for full scn TPG. n Forth nnul EEE nterntionl onference, pges , 99. [] T. Lng, E. usoll, nd J. ortdell. ndividul flip-flops with gted clocks for low power dtpths. EEE Trnsctions on ircuits nd ystems : nlog nd igitl ignl Processing, 44(6):507 56, June 997. [3] J.Y. Lin, T.. Liu, nd W.Z. hen. cell-sed power estimtion in O comintionl circuits., pges , 994. [4] N. Nedovic nd V. Oklodzij. ynmic flip-flop with improved power. n Proceedings of the nterntionl onference on omputer esign, 000. [5] N. Nedovic nd V. Oklodzij. Hyrid ltch flip-flop with improved power efficiency. n Proceedings of the ymposium on ntegrted ircuits nd ystems esign, 000. [6]. Nikolic et l. mproved sense-mplifier-sed flip-flop: esign nd mesurements. EEE Journl of olid-tte ircuits, 35(6): , June 000. [7] J. H. tynryn nd K. K. Prhi. Het: Hierrchicl energy nlysis tool. Proceedings of the 33rd esign utomtion onference, pges 9 4, June 996. [8] V. tojnovic nd V. Oklodzij. omprtive nlysis of msterslve ltches nd flip-flops for high-performnce nd low-power systems. EEE Journl of olid-tte ircuits, 34(4): , pril 999. [9] V. tojnovic, V. Oklodzij, nd. jw. unified pproch in the nlysis of ltches nd flip-flops for low-power systems. n Proceedings of the nterntionl ymposium on Low Power Electronics nd esign, pges 7 3, ugust 998. []. vensson nd J. Yun. Ltches nd flip-flops for low power systems. n. hndrksn nd. rodersen, editors, Low Power O esign, pges EEE Press, 998. [] J. Yun nd. vensson. New single-clock O ltches nd flipflops with improved speed nd power svings. EEE Journl of olid-tte ircuits, 3():6 69, Jnury 997. [] V. Zyun nd P. Kogge. ppliction of T to ltch-power estimtion. EEE Trnsctions on VL ystems, 7(), rch