The Digital Logic Level
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1 The Digital Logic Level Wolfgang Schreiner Research Institute for Symbolic Computation (RISC-Linz) Johannes Kepler University Wolfgang Schreiner RISC-Linz
2 The Digital Logic Level The computer s real hardware. asic elements: gates. asic logic: oolean algebra. Combinatorial Circuits. rithmetic Circuits. Memory. CPUs and buses. oundary between computer science and electrical engineering. Wolfgang Schreiner 1
3 Gates gate is a device that computes a function on a two-valued signal. Fundament: transistor can operate as a binary switch. Three connections to the outside: collector, base, emitter. Input voltage V in < critical value: transistor becomes infinite resistance. Output voltage V out becomes externally regultated voltage V cc (5V). Input voltage V in > critical value: transistor becomes a wire. Output voltage V out is pulled to ground (0V). Interpret voltages as logical values. High voltage (V cc ) is a logical 1. Low voltage (ground) is a logical 0. Transistor acts like a logical inverter (NOT). Wolfgang Schreiner 2
4 asic Gates: Construction +V CC +V CC +V CC V out Collector V 1 V out V out V in V 2 V 1 V 2 ase Emitter (a) (b) (c) NND and NOR gates can be constructed by wiring two transistors in parallel respectively in series. Wolfgang Schreiner 3
5 asic Gates: Logic NOT X NND X NOR X ND X OR X X X X X X (a) (b) (c) (d) (e) Most computers are based on NND and NOR gates. Wolfgang Schreiner 4
6 oolean lgebra C C lgebra of boolean functions. 1 Inputs and results are logical values. 4 C oolean function of n variables has 2 n input combinations. Representation by truth table with 2 n rows. 2 2n oolean functions with n variables exist. 5 C C M 2 8 M C C 3 C 7 C (a) (b) Wolfgang Schreiner 5
7 Other Notation Truth tables are too clumsy too handle. Suffices to specify which combinations of inputs gives output 1. Let Ā denote negation, denote conjunction, + denote disjunction. M = ĀC + C + C + C. function of n variables can be descried by a sum of at most 2 n product terms of n variables. Linear representation of oolean functions. Wolfgang Schreiner 6
8 Implementation of oolean Functions Construct circuit for a given oolean function. Systematic process: 1. Write down the truth table for the function. 2. Provide inverters to generate the complement of each input. 3. Draw and ND gate for each term with a 1 in the result column. 4. Wire the ND gates to the appropriate inputs. 5. Feed the output of all ND gates into an OR gate. Further transformations possible: 1. Replace multi-input gates by two-input gates ( + + C + D = ( + ) + (C + D)). 2. Replace NOT, ND, OR gates by NND gates (or by NOR gates). Circuit is not necessarily the simplest one. Wolfgang Schreiner 7
9 Construction of NOT, ND, OR ny oolean function can be constructed from NND or NOR only. (a) + + (b) (c) NND gates and NOR gates are complete. Wolfgang Schreiner 8
10 Circuit Equivalence Try to reduce the number of gates in a circuit. + C ( + C) C C C + C C C + C (a) C + C ( + C) (b) Wolfgang Schreiner 9
11 Integrated Circuits Gates are manufactured in units called Integrated Circuits (ICs). Square piece of silicon (5 mm 5 mm). Gates are deposited on these chips. Multiple chips are mounted in packages of e.g. 15 mm 50mm. Two parallel rows of pins are placed on long edges. Various integration scales. V CC Pin 8 SSI (Small Scale Integrated): MSI (Medium Scale Integrated): Notch LSI (Large Scale Integrated): VLSI (Very Large Scale Integrated): > Today: up to 10 million transistors per chip. GND Wolfgang Schreiner 10
12 Combinatorial Circuits Wolfgang Schreiner 11
13 Multiplexers 2 n data inputs, one data outputs, 1 control input. Control input selects one of the data inputs. Selected input is routed to the output. Inverse is demultiplexer. 1 data inputs, 2 n outputs, 1 control input. Input is routed to the selected output. D 0 D 1 D 2 D 3 D 4 F Fundamental routing operations. D 5 D 6 D 7 C C C Wolfgang Schreiner 12
14 Decoders n-bit number as input, 2 n output lines. Input selects output line which is set to 1. Example application: Memory of eight 1M chips. 0 1M, 1-2M,... ddress is presented to memory. High-order 3 bits are used to select one chip. Fundamental control operations. C C C D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Wolfgang Schreiner 13
15 rithmetic Circuits Wolfgang Schreiner 14
16 dders Half adder. Two inputs, two outputs. Sum of inputs in one output. Carry in other output. Sum Carry Exclusive OR gate Sum Carry in Full adder. Three inputs, two outputs. Sum of inputs in one output. Carry but in other output Carry in Sum Carry out Carry Sum asis of 1 bit LU Carry out Wolfgang Schreiner 15 (a) (b)
17 rithmetic Logic Units 1 bit LU. Inputs enabled or not (set to 0). Control input selects operation. ND, OR, NOT, ddition. asis of n bit LU. INV EN EN Logical unit + Carry in Sum Output Enable lines F 0 Full adder F 1 Decoder Carry out Wolfgang Schreiner 16
18 rithmetic Logic Units 8 bit LU. Connection of 1-bit LU slices. F1 F bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU 1-bit LU INC O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 Carry in Carry out n-bit LUs can be constructed from 1-bit slices. Wolfgang Schreiner 17
19 Memory Wolfgang Schreiner 18
20 Clocks In digital circuits, timing relations must be controlled. Clock: circuit that emits sequence of pulses (crystal oscillator). Precise pulse width; precise interval between pulses (clock cycle time). Derived clock signals can be constructed by delays. y combination, clock cycle can be divided in subcycles. C1 Delay C2 (a) (b) C (c) Wolfgang Schreiner 19
21 Latches Circuits that remember previous input values. SR latch. S input: sets the latch; R input: resets the latch. If S is 1 and R is 0, Q gets 1. If R is 1 and S is 0, Q gets 0. If R and S are 0, Q remains unchanged. Q is inverse of Q. S Q S Q NOR R Q Q 0 R 1 0 (a) (b) (c) Wolfgang Schreiner 20
22 Pulse Generators Circuits which generates very short pulses. signal a and its negation b are fed into an ND gate. When signal a is set, negation b is slightly delayed. For a short period, there is a signal on output d. d a b d b ND c c c (a) b a Time (b) Wolfgang Schreiner 21
23 Flip-Flops Circuit which stores a data value at a precise time. Combination of a pulse generator and a latch. Inputs of latch are D ND D (no inconsistency may occur between R and S). Inputs are conjoined with output of pulse generator (input is read at well-defined time). D Q Q Current value of D is read and stored a fixed time after clock signal. Wolfgang Schreiner 22
24 Memory Organization Individual words must be addressed. Data in I 2 I 1 I 0 Write gate D Q CK D Q CK D Q CK Word memory. Input lines I i. ddress lines j. Chip select signal CS. RD signal for read/write. OE signal for output enable. Simple regular structure. 1 0 Word 0 select line Word 1 select line Word 2 select line CS RD D Q CK D Q CK D Q CK D Q CK D Q CK D Q CK D Q CK D Q CK D Q CK Word 1 Word 2 Word 3 CS RD O 1 O 2 O 3 OE Output enable = CS RD OE Wolfgang Schreiner 23
25 RMs: Random ccess Memories SRM: Static RM. Constructed from flip-flops. Content is retained as long as power is kept on. Very fast (few nanoseconds access time), used for caches. DRM: Dynamic RM. Each cell consists of transistor and capacitor only. Capacitor can be charged or discharged (0 or 1). Charge leaks out, bit needs to be refreshed every few milliseconds. Rather slow (tens of nanoseconds access time), used for main memory. SDRM: Synchronous DRM. Hybrid of SRM and DRM. ccess driven by synchronous clock. Used for main memory today. Wolfgang Schreiner 24
26 ROMs: Read Only Memories Content is inserted during manufacture. Content cannot be changed or erased, is retained even if power is switched off. Data are etched via mask into silicon surface. PROM: Programmable ROM. Content can be written once. Contains array of tiny fuses that can be blown out by high voltage. EPROM: Erasable PROM. Data can be erased by exposure to ultraviolet light. EEPROM: Electric EPROM. Data can be erased by electric pulses. Flash Memory: memory is block erasable and rewritable. Compact Flash card, Smartmedia card,... Wolfgang Schreiner 25
27 CPU Chips and uses Wolfgang Schreiner 26
28 CPU Chips ll modern CPUs are contained on a single chip. Ineraction with outside world through set of pins. Input signals, output signals, bidirectional signals. Connected to similar pins on memory chips and I/O chips via bus. ddress pins: CPU puts memory address on its address pins to load a memory cell. Data pins: Memory replies by putting requested word on the CPU s data pins. Control pins: CPU asserts via some control lines when it wants to read data. Memory asserts via some control lines when data are available. Wolfgang Schreiner 27
29 Control Pins us control. CPU tells bus whether it wants to use it. Interrupts. I/O devices tell CPU to interrupt current program. us arbitration. Used for regulating traffic on the bus. Coprocessor signaling. Used for making/granting requests to auxiliary processors. Status. ccept or provide status information. ddressing Data us control Interrupts Symbol for clock signal Typical Micro- Processor Φ +5v Power is 5volts us arbitration Coprocessor Status Miscellaneous Symbol for electrical ground Wolfgang Schreiner 28
30 Computer uses Electrical pathways shared between multiple devices. Various functions. Internal to CPU: transport data to and from LU. External to CPU: connect it to memory or to I/O devices. Multiple external buses with special properties. Memory bus, I/O bus, graphics bus,... CPU chip Registers uses us controller Memory bus Memory LU I/O bus On-chip bus Disk Modem Printer Wolfgang Schreiner 29
31 Computer uses Various types of buses: PCI bus (PCs), SCSI bus (PCs and workstations), Universal Serial us (US, PCs), FireWire (consumer electronics),... us Protocols: Sets of rules that devices must obey to use the bus. Masters: active devices that can initiate bus transfers. Slaves: passive devices that wait for requests. CPU master, I/O device slave: initiate data transfer. I/O device master, memory slave: DM (Direct Memory ccess). Design parameters: us width: number of address and data lines (e.g. 64 bits). us cycle time: number of transfers per second (e.g. 100 MHz). us bandwidth = data width * cycle time (781 M/s). Wolfgang Schreiner 30
32 Synchronous uses ll activities take a fixed number of bus cycles. Read cycle with 1 wait state T 1 T 2 T 3 Φ T D DDRESS Memory address to be read T DS DT Data MREQ T ML T M T MH RD T RH T RL T DH WIT Time (a) Wolfgang Schreiner 31 Symbol Parameter Min Max Unit T D ddress output delay 11 nsec
33 Example: Pentium PC Cache bus Local bus Memory bus Level 2 cache CPU PCI bridge Main memory PCI bus SCSI US IS bridge IDE disk Graphics adaptor vailable PCI slot Mouse Key- board IS bus Mon- itor Modem Sound card Printer vailable IS slot Wolfgang Schreiner 32
34 I/O Controllers URT: Universal synchronous Receiver Transmitter. Can read a byte from data bus and output it bit by bit on a serial line. Can read a byte bit by bit from a serial line and put it on the data bus. PIO: Parallel Input/Output chip. Chip that connects to the parallel interface of a computer. Computer writes 8 bit number into a register of the chip. Chip puts 8 bit number on the output lines until register is rewritten. CS 0-1 WR RD RESET D0-D Parallel I/O chip Port Port Port C Wolfgang Schreiner 33
35 Memory Mapped I/O I/O registers are assigned part of the memory address space. CPU reads/writes corresponding memory locations. Chip Select (CS) pin of PIO chip is wired to bus address lines. If corresponding address is issued, data pins of PIO chip take value from bus data lines. EPROM at address 0 RM at address 8000H PIO at FFFCH 0 ddress bus K 8K 12K 16K 20K 24K 28K 32K 36K 40K 44K 48K 52K 56K 60K 64K CS CS CS 2K 3 8 EPROM 2K 3 8 RM PI0 Wolfgang Schreiner 34 ddress bus 0 (a) 15
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