ABSTRACT. Gallium Nitride is an excellent material for power semiconductor applications due to its wide

Transcription

1 ABSTRACT KIRKPATRICK, CASEY JOE. Gate Stack Design for Threshold Voltage Control of Gallium Nitride Power Transistors. (Under the direction of Dr. Veena Misra). Gallium Nitride is an excellent material for power semiconductor applications due to its wide band gap, good thermal conductivity, high mobility and high breakdown field. The availability of high quality GaN on silicon substrates promotes GaN as a future low cost, high power semiconductor material. However, there are still challenges that need to be overcome before AlGaN/GaN devices can provide robust solutions for power applications. Particularly challenging, is that high mobility GaN transistors are normally-on, which requires a negative gate bias to turn off devices. A gate stack design to enable enhancement mode operation of GaN transistor devices has been developed. Gate dielectrics to reduce losses due to leakage deposited by atomic layer deposition have been characterized and evaluated. SiO 2 and HfAlO deposited by atomic layer deposition on GaN have been characterized electrically for the first time. The band alignment of these dielectrics with GaN as well as commonly used Al 2 O 3 and HfO 2 dielectrics has also been experimentally determined and reported for the first time. A novel device structure, termed the Flash MOS- HFET, has been designed, simulated and fabricated which allows for enhancement mode GaN transistor operation. This novel device has been characterized and materials and engineering concerns arising from the invented device have been addressed. An optimized Flash MOS-HFET device allows for continuous enhancement mode operation with high threshold voltage, high performance and low gate leakage facilitated by a gate insulator.

2 Copyright 2013 by Casey Joe Kirkpatrick All Rights Reserved

3 Gate Stack Design for Threshold Voltage Control of Gallium Nitride Power Transistors by Casey Joe Kirkpatrick A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Electrical Engineering Raleigh, North Carolina 2013 APPROVED BY: Dr. Veena Misra Committee Chair Dr. Alex Huang Dr. Mehmet Ozturk Dr. Zlatko Sitar

4 ii DEDICATION To my wife Sarah and my parents Yevette and Joe Kirkpatrick

5 iii BIOGRAPHY Casey Kirkpatrick was born in Hannibal, New York on June 17 th As an undergraduate at North Carolina State University, Casey worked under Dr. Mehmet Ozturk on Hall Effect characterization tools and strained SiGe contacts. In 2008, Casey participated in the National Science Foundation s research experience for undergraduates (REU) program at the Johns Hopkins University where he developed a three dimensional magnetic field sensor based on traditional silicon processing techniques. Casey graduated summa cum laude to receive his B.S. in electrical engineering in Immediately following graduation, Casey began a Ph.D. program under Dr. Veena Misra focusing on wide band gap semiconductors for future power applications.

6 iv ACKNOWLEDGMENTS I couldn t have got to this point without the help and support of my colleagues and friends. I first want to thank my advisor Veena Misra for everything she has done to guide this work and to build the exceptional group and environment I have had the privilege to work in. I also want thank Mehmet Ozturk who introduced me to semiconductor research so early in my undergraduate career and who introduced me to the Misra group. As an undergraduate, I was helped immensely by Emre Alptekin who helped me get my first hands on experience. Thank you to Jeong-Hyun Cho who made a 10 week stint at the Johns Hopkins University one of the most important things I did as an undergraduate. All of my fellow group members have given great feedback and discussion through the years. Steven Mills, Xiangyu Yang, Srikant Jayanti, Rahul Suri, Rebecca Thomas, Sarah Haney and Steven Novak have all been instrumental in making this happen. A special thanks to Narayanan Ramanan and Bongmook Lee who have worked so closely with me on GaN, as well as to Dan Lichtenwalner for helping me get a strong start working with wide band gap semiconductors. Thank you to the rest of my committee Dr. Huang and Dr. Sitar for taking the time to work with me and for excellent guidance, especially during my preliminary exam. I want to thank the National Science Foundation in earnest for supporting this research through the FREEDM center, for supporting me as an undergraduate through the

7 v REU program and for making me even prouder of North Carolina State University with the new ASSIST center. Thank you to my parents Joe and Yevette Kirkpatrick for their continued support. I also want to thank my grandma Mary Kirkpatrick for always being supportive and inquisitive of my research. Finally, thank you to my wife Sarah Kirkpatrick who deserves an award for her constant support and patience.

8 vi TABLE OF CONTENTS LIST OF TABLES viii LIST OF FIGURES ix 1 INTRODUCTION Motivation Gallium Nitride for Power Electronics Goals of the Following Work Document Preview DEVICE STRUCTURES, CHARACTERIZATION AND SIMULATION TECHNIQUES Introduction to Chapter Atomic layer deposition Back to Back Capacitor Structure AlGaN/GaN transistor devices Heterojunction Field Effect Transistor Operation Electron Beam Lithography Electrical characterization methods Physical characterization Simulation PRELIMINARY GATE DIELECTRIC EVALUATION Chapter Introduction Surface Cleaning Post Dielectric Annealing Preliminary Electrical Evaluation Band Alignment of ALD SiO 2, HfAlO, HfO 2 and Al 2 O MOS-HFET DEVICES Introduction to Chapter ALD SiO 2 MOS-HFET Experimental ALD SiO 2 MOS-HFET Characteristics ALD SiO 2 Conclusions... 71

9 vii 4.5 ALD HfAlO and SiO 2 Comparison Technologies for Enhancement mode HFETs Recessed Gate MOS-HFET FLASH MOS-HFET Flash MOS-HFET introduction Flash MOS-HFET Simulation Flash MOS-HFET Fabrication Flash MOS-HFET Charging and Memory Characteristics Flash MOS-HFET High Power Considerations Retention Improvement of the Flash MOS-HFET CIRCUIT CONTROL OF THE FLASH MOS-HFET Introduction to Chapter Flash MOS-HFET Retention Conditions Flash MOS-HFET Stability by Field Driven Feedback Boost Converter Circuit with E-mode Flash MOS-HFET Alternative Charging Methods Flash MOS-HFET SFDF Conclusions SCALING AND SCALABILITY FOR POWER MOS-HFETS MOS-HFET Scaling by Electron Beam Lithography Scalability of GaN Power HFETs Practical MOS-HFET Scaling Limits CONCLUSIONS AND FUTURE WORK Conclusions Future Work GaN or SiC? A Perspective on the Future of Power Electronics REFERENCES

10 viii LIST OF TABLES Table 1.1 Typical material values for Si, SiC and GaN... 2 Table 2.1 Material parameters for wafers from different vendors Table 2.2 Spontaneous and piezoelectric polarization values Table 2.3 Standard processes for commonly used resists Table 2.4 Dependence of the spurious e.m.f.s... 35

11 ix LIST OF FIGURES Figure 1.1 Theoretical on-resistance as a function of breakdown voltage... 3 Figure 2.1 Top and cross-sectional view of a typical back to back capacitor structure... 8 Figure 2.2 Equivalent circuit of the back to back capacitor Figure 2.3 Partial GaN crystal illustration for visualization of polar atoms Figure 2.4 Origin of the polarization in GaN Figure 2.5 Illustration of the compensation of bound charge within a polarized material Figure 2.6 Band diagram illustrating the 2DEG confinement Figure 2.7 HFET and MOS-HFET structures with a GaN bulk layer Figure 2.8 Pinch off condition Figure 2.9 Ideal I D V D characteristics of an HFET Figure 2.10 The effect of spacing between groups of devices on stitching Figure 2.11 Typical Hall effect geometry and notation Figure 2.12 Commercially available Ecopia HMS-3000 Hall effect sample holder Figure 2.13 Proposed setup for Hall effect measurements Figure 2.14 Hall voltage measured as a function of time Figure 2.15 Averaged slope of V Hall for different magnetic fields Figure 3.1 Ga 2p 3/2 spectra for the GaN surface before and after cleaning Figure 3.2 Capacitance voltage characteristic at 1 MHz Figure 3.3 Ga 2p 2/3 spectra for thin Al 2 O 3 on GaN

12 x Figure 3.4 Integration of the C-V profile for back to back capacitors Figure khz capacitance voltage profile for Al 2 O 3, HfAlO and SiO Figure 3.6 Threshold voltage comparison from literature Figure 3.7 Threshold voltage as a function of EOT Figure 3.9 XPS spectra for thin and thick dielectrics Figure 3.10 Valence band spectra for clean substrate and each dielectric Figure 3.11 O 1s energy loss spectra for band gap determination of each dielectric Figure 3.12 Schematic band alignment for SiO 2, Al 2 O 3, HfO 2 and HfAlO Figure 4.1 Cross sectional TEM of the SiO 2 /GaN interface Figure 4.2 O 1s (a) and Si 2p (b) XPS spectra Figure 4.3 Electrical characteristics of MOS-HFET with 7 nm SiO Figure 4.4 I DS V GS characteristics at V DS =250 mv Figure 4.5 I DS V DS characteristics under DC and pulsed conditions Figure 4.6 Gate leakage current density comparison Figure 4.7 MOS-HFET transconductances Figure 4.8 Two dimensional electron gas concentration Figure 4.9 Transfer I-V characteristics at V ds =1 V for 5nm gate recess Figure 4.10 Output I-V characteristics for recessed gate transistor Figure 5.1 Cross-sectional view of Flash MOS-HFET device Figure 5.2 Synopsys TCAD structure for simulation of Flash MOS-HFET device Figure 5.3 Threshold voltage shift after charging... 82

13 xi Figure 5.4 Conduction band profile before and after charging Figure 5.5 Simulated sheet charge concentration as a function of charging time Figure 5.6 Band diagram illustrating the energy bands of the blocking dielectric Figure 5.7 ID-VD characteristics for Flash MOS-HFET devices before charging Figure 5.8 Threshold voltage shift with increasing programming voltage Figure 5.9 Nearly parallel shift in transconductance Figure 5.10 Shift in CV curves before and after programing Figure 5.11 Threshold voltage as a function of charging time Figure 5.12 Retention characteristics Figure 5.13 Reduced barrier to tunneling for trapped electrons Figure 5.14 Basic device characteristics Figure 5.15 Gate leakage before and after programming Figure 5.16 Threshold voltage shift with increasing charging voltage Figure 5.17 Threshold voltage shift with increasing charging time Figure 5.18 Threshold voltage as a function of elapsed time from charging Figure 5.19 Threshold voltage shift after drain stressing for 30 s Figure 5.20 Retention measurements at increased temperature Figure 5.21 Improved Retention Characteristics Figure 6.1 Change in threshold voltage for the active and passive conditions Figure 6.2 Simulated band diagram for the Flash MOS-HFET Figure 6.3 Threshold voltage stability for increasing overdrive voltage (V OD =V G -V T )

14 xii Figure 6.4 Circuit model of constructed boost converter circuit Figure 6.5 Simulated output voltage for constructed boost converter Figure 6.6 Boost converter input and output as a function of time Figure 6.7 Threshold voltage remains stable Figure 6.8 charginge by applying gate bias at the operating voltage and frequency Figure 6.9 Charging by applying a low frequency pulse followed by the operating pulse Figure 7.1 SEM image of fabricated MOS-HFET Figure 7.2 I D -V G characteristics for a 150 nm L G..117 Figure 7.3 I D -V D characteristics for devices with a gate length of 150 nm Figure 7.4 SEM image of a 1A MOS-HFET device Figure 7.5 R ON as a function of L GD for devices fabricated by electron beam lithography Figure 7.6 HFET breakdown voltage taken at a drain current of 0.1 ma/mm Figure 7.7 Decreasing gate length makes the threshold voltage more negatived Figure 7.8 As the drain voltage is increased, threshold voltage decreases Figure 7.9 Expected R ON for a combination of state of the art technologies Figure 7.10 Expected R ON as a function of L G for a gate to drain spacing of 12 μ

15 1 1 INTRODUCTION 1.1 Motivation Power electronics are critical in enabling efficient energy distribution from generation, such as at power plant or a wind mill, to consumption. Energy is converted by power electronic devices several times from high to low voltage and vice versa before it reaches its final destination such as a computer chip or a wall socket. In order to meet the rapidly increasing energy needs of our society in a sustainable and environmentally responsible manner, intelligent, efficient energy conversion is required. For low voltage conversion applications (<600), Si solid state power converters are conventionally applied. Si devices have reached their theoretical limit for efficient operation, and cannot be applied for higher voltage applications efficiently. This has led to the exploration of wide band gap semiconductor materials such as silicon carbide, gallium nitride (GaN) and diamond which can operate more than 100 times more efficiently than Si at high voltage. Of these, GaN is particularly interesting because epitaxial growth of GaN on Si has enabled 8 wafer production, decreasing material cost and promoting GaN devices as an economical replacement for lower performance Si devices [1], [2]. GaN has the potential to combine high efficiency with cost effectiveness for the next generation of power semiconductor devices.

16 Table 1.1 Typical material values for Si, SiC and GaN Gallium Nitride for Power Electronics Baliga s figure of merit (BFOM),, is commonly used to benchmark power semiconductors in terms of on-resistance and breakdown voltage [3]. The material properties of GaN as seen in table 1.1 are particularly well suited for power electronics applications as noted by its high BFOM. As seen in figure 1.1, GaN has potential to operate at a higher efficiency than Si and SiC. State of the art GaN power devices have been demonstrated with a breakdown voltage of 8.3 kv[4] for GaN on sapphire substrates. Breakdown voltages of 1.8 kv[5] and 2.2 kv [6] have been demonstrated for GaN on Si substrates. Boost converters utilizing a GaN on Si switching transistor has been realized with efficiency of 97.8 % [7]. Other GaN

17 3 Figure 1.1 Theoretical on-resistance as a function of breakdown voltage for an ideal case. GaN has potential to provide for the lowest on-resistance at a given breakdown voltage. DC-DC converters have been demonstrated for operation at 2 MHz with an integrated Si diode [8]. GaN field effect transistors with 100 A operation and 600 V operation have been demonstrated with an on-resistance of 9.3 mω cm 2 [9]. Despite promising results for power applications, commercialization of GaN devices has been challenging. Lateral GaN devices have high surface fields which can cause premature breakdown of the devices and requires optimization of field plates and passivation dielectrics. The on-resistance of GaN transistors in switching applications can be higher than the DC value of on-resistance in an effect know as dynamic on-resistance or current collapse [10]. While high quality GaN on Si wafers have been demonstrated, commercial availability of high quality wafers is limited. A final limiting factor to GaN commercialization is that GaN transistors are depletion mode (normally-on). Depletion mode devices require more complicated control and

18 4 protection strategies in circuits and the power industry has been reluctant to accept normallyon devices because of safety concerns. In order to overcome this limiting challenge material optimization and device design changes must be explored for GaN transistors. 1.3 Goals of the Following Work The goal of this work is to develop a novel gate stack for a GaN heterojunction field effect transistor (HFET) which enables normally-off operation. By precisely controlling the charge balance in the gate area of a GaN heterojunction device, threshold voltage can be controlled. The implemented gate stack should provide for low gate leakage by utilizing an insulating gate structure which will improve power converter efficiency. Threshold voltage of more than 1 V should be achieved to facilitate the harsh thermal and electromagnetic interference conditions common to power circuits. The gate stack should be implemented in a manner which results in the minimum possible on-resistance while enabling high voltage operation of up to 600V. 1.4 Document Preview Chapter one of this document briefly describes the motivation for developing a gate stack to control threshold voltage for GaN power devices Chapter two will introduce the critical fabrication, measurement and testing techniques applied in this work. A physical model of a GaN HFET will be derived to describe operation characteristics. Device simulation parameters and techniques will be addressed as well for Sentaurus TCAD simulator.

19 5 In chapter 3 surface cleaning prior to atomic layer deposition (ALD) of dielectrics will be explored, as well as the effect of post deposition annealing on surface oxide growth. A simple structure will be used to evaluate key electrical properties of several dielectrics to be considered for a gate insulator and compared in terms of expected threshold voltage with previously reported dielectrics. Finally, x-ray photoelectron spectroscopy (XPS) will be utilized to determine the band alignment several dielectrics deposited by ALD on GaN Chapter 4 will report transistor device characteristics with ALD SiO 2 dielectric for the first time. ALD SiO 2 dielectric will be compared with HfAlO dielectric in terms of performance and fundamental characteristics. A novel device based on charge storage in the gate stack of a GaN transistor device will be presented in chapter 5. This device will enable enhancement mode operation of GaN transistors. Simulation, fabrication and measurement of this device will be discussed as well as the implementation limitations of the device. Chapter 6 will address the issues of the novel device and its use in a power converter circuit. A simple boost converter circuit will be constructed and employed to further support the gate stack design utilized for normally-off operation. Chapter 7 will discuss scaling of GaN transistors as well as the practical limits to device scaling. Electron beam lithography will be utilized to manufacture nanoscale gate length devices which can achieve very low on-resistance. The effects of reducing gate length and the application of extremely small feature sizes enabled by electron beam lithography will be discussed.

20 6 Conclusions and suggested future work will be presented in chapter 8. A brief perspective of the ongoing debate of whether SiC or GaN is the best power semiconductor material will also be presented.

21 7 2 DEVICE STRUCTURES, CHARACTERIZATION AND SIMULATION TECHNIQUES 2.1 Introduction to Chapter The techniques and models used in this work will be discussed in this chapter. 2.2 Atomic layer deposition Atomic layer deposition (ALD) is a deposition method that allows for low temperature, highly conformal deposition of materials with precise thickness control. Initially atomic layer deposition was conceived as atomic layer epitaxy (ALE) in the late 1970 s in which the deposition material precursors where individually pulsed for a controlled time period with surface limited reactions allowing for monolayer by monolayer deposition [11]. With rapid scaling of Si, interest in ALD for deposition of high quality films greatly increased with state of the art Si IC s now integrating ALD gate dielectrics [12]. The ALD deposition process is a self-limiting technique in which a series of precursors each consisting of a target element and a volatile organic carrier are pulsed in succession in order to create the desired material. In a simple two precursor process such as that of Al 2 O 3, an aluminum precursor, typically trimethylaluminum (TMA: Al(CH 3 ) 3 ) is pulsed into the deposition chamber. The precursor then adsorbs to the surface of the deposition substrate until the surface of the substrate is coated with a monolayer of the precursor. After the substrate is completely covered with the initial precursor no additional precursor can be absorbed to the surface, limiting the first step of the reaction. Following the initial precursor pulse a second precursor (H 2 O) is pulsed which reacts with the initial

22 8 Figure 2.1 Top and cross-sectional view of a typical back to back capacitor structure on a GaN heterostructure precursor to form a single monolayer of the desired binary film while desorbing the undesired organic carriers. The chemical reaction per cycle for Al 2 O 3 is as follows ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Repeating this cycling process increases film thickness with thickness control at the atomic level. The precise material control facilitated by atomic layer deposition allows for the simple deposition of layered or nanolaminate dielectrics. HfAlO is formed by depositing one layer of Al 2 O 3 followed by one layer of HfO 2 with a reaction cycle of ( ) ( )

23 9 The resulting film is then annealed allowing for the intermixing of Al 2 O 3 and HfO 2 and resulting in the laminate film HfAlO [13]. Atomic layer deposition is also the preferred deposition method for materials which do not have a suitable native oxide such as GaN and AlGaN and thus will be used to deposit gate and passivation dielectrics for GaN devices. 2.3 Back to Back Capacitor Structure A back to back capacitor is an easily fabricated structure for rapid characterization of ALD dielectrics on GaN heterostructures [14]. The structure shown in figure 2.1 requires only a single mask step to define the device and can yield a wealth of information including, dielectric constant, AlGaN thickness, oxide capacitance, sheet carrier density, charge characteristics and expected threshold voltage of a transistor device. This last parameter is especially useful for power device applications given the strong desire for enhancement mode devices. The equivalent circuit of a back to back capacitor structure on GaN is shown in figure 2.2. In measurement, the large metal area between circular capacitors is grounded and the measurement signal is applied to the circular capacitor under test. At the AlGaN/GaN interface, the high conductivity of the 2DEG allows the resistance associated with the large capacitor to be ignored. Combined with the assumption that the large area capacitor has capacitance much much greater than the small circular device under test, the device can be modeled as small capacitor in series with a much larger capacitor. In this model, the small

24 10 Figure 2.2 Equivalent circuit of the back to back capacitor capacitor dominates the measured signal allowing for extraction of material properties with area defined as that of the smaller circular capacitor. 2.4 AlGaN/GaN transistor devices Notes on terminology Terminology in describing the same or similar heterojunction device structures varies widely and can lead to some confusion. HEMT (high electron mobility transistor), HFET (heterojunction field effect transistor), MOS-HFET or MOSHFET (metal oxide semiconductor heterojunction field effect transistor) and MIS-HFE T or MISHFET (metal insulator semiconductor heterojunction field effect transistor) have been used interchangeable to describe a common heterojunction transistor device. For clarity in this work, the term HFET will be used to refer to heterojunction devices without a gate dielectric.

25 11 Figure 2.3 Partial GaN crystal illustration for visualization of polar atoms MOS-HFET will be used to describe devices with a gate dielectric regardless of whether the gate insulator is SiO 2 or some other dielectric such as Al 2 O 3. All MOS-HFETs are HFETs and all HFETs are HEMTs, as such all transistor devices in this work can be termed HEMT s or HFET s but will be labeled as previously stated III-Nitride Polarity and Two Dimensional Electron Gas Formation III-nitride semiconductors demonstrate a polarization effect due to a lack of inversion symmetry combined with a uniaxial nature and iconicity. In a GaN crystal lattice as partially illustrated in figure 2.3, Ga atoms carry a positive charge and N atoms have negative charge. These charges can be treated as sheet charges for the GaN crystal stacking in the (0001) direction. Figure 2.4 schematically illustrates how this stacking can result in a net polarization in the crystal. In the repeated unit which builds the GaN lattice, the average position of negative charge is at the middle of the cell whereas the average position of the positive charge is slightly below that of the negative charge. The resulting charge distribution causes the polarization of GaN and other III-Nitride semiconductors.

26 12 Figure 2.4 Origin of the polarization in GaN While III-Nitride semiconductors are electrically neutral when considering the overall crystal, the polarization of the material results in bound surface charge at the material termination. A large separation between the top and bottom surfaces leads to poor charge compensation. This will result in external charge compensation at the material surface by electrons, holes or ions whether in air or with another material as depicted in figure 2.5. For the case of AlGaN/GaN heterojunction the magnitude of the AlGaN polarization and corresponding bound surface charge is higher than that of GaN. The bound surface charge at the material interface has a sheet charge density which can be quantified as [15] ( )

27 13 Figure 2.5 Illustration of the compensation of bound charge within a polarized material where P is the magnitude of the total polarization. For GaN grown by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) in the most common case of the (0001) direction, the direction of the polarity of the polarization charge results in a positive bound sheet charge density which will attract electrons. A two dimensional electron gas (2DEG) will form to compensate this excess bound charge in the GaN layer as illustrated in the pictorial band diagram shown in figure 2.6. The 2DEG electron gas is a Figure 2.6 Band diagram illustrating the 2DEG confinement

28 14 highly conductive sheet of electrons which forms in the GaN at the AlGaN/GaN interface and is confined to a thin (1-2 nm) quantum well formed at the heterojunction interface lending to its two dimensional nature. The 2DEG electron gas can be formed at equilibrium without doping of the GaN or AlGaN. This minimizes ionized impurity scattering allowing for higher 2DEG mobility than that of bulk GaN. It was proposed by Ibbetson et al. [16] that the 2DEG is populated by electrons from surface states at the surface of the material. Miao et al. rigorously supports this proposal through theoretical work compared with experimental data [17]. In an HFET device or MOS-HFET device the 2DEG electron gas acts as the conducting channel, eliminating the need for carrier inversion seen in traditional MOSFETs Device structures The structure of a HFET and a MOS-HFET device is shown in figure 2.7. The device consists of a GaN bulk layer on a growth substrate (Si, SiC or sapphire) and transition layer Table 2.1 Material parameters for wafers from different vendors. 1 Buffer thickness includes transition layer thickness consisting of layered GaN and Al x Ga 1-x N layers. *Proprietary material parameters

29 15 Figure 2.7 HFET and MOS-HFET structures with a GaN bulk layer. Devices presented in this work have an AlGaN barrier layer. materials to mitigate physical and thermal strain. Following the bulk GaN is a barrier layer, in this work AlGaN, which facilitates 2DEG formation. The structure is then capped with a thin GaN layer which helps stabilize the surface and is inherent in the growth process [18]. All device fabrication presented in this work will start with substrates consisting of these layers. Substrates have been provided by Nitronex (GaN on Si), RFMD (GaN in SiC), Kopin (GaN on sapphire) or Azzuro (GaN on Si). Material parameters for the substrates provided from each vendor are shown in table 2.1. For the simplest device structures as seen in figure 2.7 ohmic contacts consisting of Ti/Al/Ni/Au metals are patterned, deposited and annealed to form the source and drain regions. At zero bias, the 2DEG is populated over the entire area of the wafer. In order to create discrete devices, the devices must be isolated by permanently removing the 2DEG between devices. This step, known as mesa isolation, is typically performed by reactive ion etching of the entire AlGaN layer such that the heterojunction interface no longer exists.

30 16 Isolation may also be performed by implantation of N or other atoms [19], [20]. For a MOS- HFET structure, a gate dielectric is deposited following isolation. A gate metal is then deposited on the oxide (MOS-HFET) or GaN surface (HFET) completing the device. A passivation dielectric is usually deposited following gate metallization for the HFET device. In many cases a blanket deposition of the gate dielectric for the MOS-HFET device allows for the gate insulator to serve as the passivation dielectric. 2.5 Heterojunction Field Effect Transistor Operation The HFET is a three terminal device in which a two dimensional electron gas between source and drain is modulated via a gate bias. The conductivity of the devices is determined by the 2DEG gas carrier density n s which is material dependent with conduction band discontinuity, doping density, barrier thickness, barrier dielectric constant, and polarization as determining factors Equilibrium Carrier Concentration In order to determine the band profile of HFET devices an iterative process is necessary. The quantum well associated with the 2DEG necessitates solving of the Schrödinger equation to determine charge profile in the quantum well. This solution will be used to solve the Poisson equation which will be fed back into the Schrödinger equation until convergence of the Poisson equation is reached. Iteration of this procedure will allow for calculation of the conduction band profile and sheet carrier density.

31 17 The GaN/barrier interface is treated as an ideal, abrupt interface. Polarization charge at the interface is included as P total. The boundary condition at the interface is given as where and are the dielectric constants of the barrier layer and GaN respectively, and and are the electric fields in the corresponding materials. The magnitude of the piezoelectric polarization vector is [21] ( ) ( ) where and are the lattice constants for the barrier layer and GaN. The other constants and are the piezoelectric and elastic constants. Typical values for piezoelectric and spontaneous polarization are given in table 2.2 [22], [23]. The polarization values are similar to typical heterojunction carrier densities and therefore will have a strong effect on device performance. In one dimension, the Poisson equation can be written as ( ) ( ) ( )

32 18 where ( ) is the dielectric constant which changes according to the semiconductor material. The charge density consists of ionized impurities due to the effective doping (whether intentional or unintentional), free carrier concentrations and the charge contained within the quantum well. ( ) ( ( ) ( )) Here and are the effective donor and acceptor doping concentrations, and are the free carrier concentrations of electrons and holes respectively and the summation relates the occupation of the quantum well by electrons with a corresponding wave function ( ). Effective impurity concentrations are as follows ( ) Table 2.2 Spontaneous and piezoelectric polarization values for commonly fabricated barrier layers on GaN. Conduction band discontinuity is also given.

33 19 ( ) where and are the donor and acceptor concentrations with an energy level at and. Free carrier concentrations are often high, close to degeneracy. In this case, Fermi-Dirac statistics are used for free carrier concentration. ( ) ( ( ) ) The three dimensional density of states is used for determination of free carrier density; however two dimensional electron confinement is present near the material interface. Taking this into account, a lower energy boundary is set in order to determine free carrier concentration with carriers below this energy, E min, removed from ( ) calculations and confined to the two-dimensional quantum well. In order to calculate carrier concentrations at energy below E min the one-dimensional Schrödinger equation ( ) [ ( )] ( ) is solved to determine wave functions and energy levels within the quantum well. After determining wave functions and energy levels, occupation of these states can written as [24] [ ( )] where is the in-plane effective mass.

34 20 Analytical solving of these equations proceeds by first guessing a potential V(z) and calculating energy levels and wave functions by solving the Schrödinger equation. Then, this charge profile is inserted into the charge balance equation allowing for the Poisson equation to be solved for the conduction band profile Charge Control with Schottky Gates In order to model IV characteristics, the sheet carrier density modulation by an applied bias must be explored. In this formulation, the barrier layer is assumed to be fully depleted. The depletion approximation is assumed. The Poisson equation for the barrier region is with 0 corresponding to the metal interface and d the heterojunction interface. Integrating yields ( ) ( ) ( ) ( ) At a distance d ( ) ( ) Rewriting potential as

35 21 ( ) [ ( )] The potential evaluated at d which is the potential at the heterojunction interface is ( ) ( ) Defining, the pinch off voltage, as Gives an interface field E 2 of ( ) ( ) V 2 can be written in terms of given parameters as ( ) where is the applied bias, is the Schottky barrier height and is the equilibrium carrier concentration. ( ) defining threshold voltage as ( ) allows sheet carrier density to be written in terms of and

36 22 ( ) at is at a maximum where IV Model of the HFET In the gated region of an HFET, current conduction can be approximated as dominated by drift current and therefore given as Diffusion current will be neglected as the contribution due to diffusion current under the gate is small [25]. N s is the two dimensional electron gas concentration, is the gate width, and is the electron drift velocity. Drift velocity can be represented by the piecewise function ( ) { where is electron mobility, and is the critical field at which saturation velocity,, is reached. From the previous derivation of as a function of, can be represented as { ( ) where is the gate capacitance., which is the difference between the Fermi level of the gate and the Fermi level of the channel. In all calculations voltage will be referenced to source voltage fixed at 0 V. Accounting for variation along channel

37 23 Figure 2.8 With increasing drain bias, the 2DEG becomes depleted at the so called pinch off condition. This results in saturation of the drain current ( ) ( ) For electric fields smaller than the critical electric field ( ). Integrating from source to channel position gives ( ) The channel voltage can be solved for as ( ) ( ) (( ) ) Taking at L g gives V D. Solving for I D gives ( ) (( ) )

38 24 The transconductance g m is therefore This solution is valid for the region of operation where the 2DEG concentration is > 0 for all area under the gate. When determining N s, the Schrödinger equation was solved in one dimension, thus in order for sheet carrier concentrations to behave as expected gradual change in the channel field is assumed (gradual-change approximation). As seen in figure 2.8, as V D approaches V G -V T sheet carrier concentration at the drain edge of the gate goes to 0 [26]. The resulting field dropped across this depleted region at the drain-side gate edge becomes large and the gradual-change approximation is no longer valid. At pinch off, all additional voltage that is applied to the drain is dropped across the depletion region at the drain edge of the gate [26]. The resulting drain current is independent of such that becomes ( ) and ( )

39 25 Figure 2.9 Ideal I D V D characteristics of an HFET Drain current as a function of drain bias for an ideal HFET device is shown in figure 2.9. It is important to note that this analysis gives identical results to that of the standard Si MOSFET device. This similarity between HFET and MOSFET device operation allows for MOSFET testing and parameter extraction techniques to be applied to the HFET device with little to no modification. 2.6 Electron Beam Lithography Introduction Electron beam lithography (e-beam lithography) is a powerful lithography tool which enables feature sizes down to 20 nm to be patterned. In traditional photolithography, a photosensitive resist is exposed to ultra violet light with features defined by a mask consisting of chrome patterns which block light exposure. With e-beam lithography a focused beam of electrons in swept across an electron sensitive resist to form a pattern which is defined by a computer aided design (CAD) program. E-beam lithography can produce

40 26 Figure 2.10 The effect of spacing between groups of devices on stitching extremely small feature sizes, but because only a small area is exposed at one time, the exposure can be time consuming. The small feature size enabled by electron beam lithography combined with the rapid prototyping allowed by a CAD defined mask, make e- beam lithography an excellent tool for defining devices with gate lengths under 1µm. E-beam lithography was performed using an Elionix 7500 EX electron beam lithography system Mask Definition E-beam mask sets were defined using AutoCAD 2010 software. AutoCAD drawings were then converted from the AutoCAD 2007.dxf file type using Weca S software to a format acceptable for the e-beam lithography system. There are several challenges associated

41 27 with CAD design which are unique to design for an e-beam system. One specific issue relates to the write field of the electron beam. The e-beam lithography tool will write a large pattern by breaking the entire write area into individual fields which can be completely written without moving the sample being exposed. A single field will be exposed, the substrate will then be moved and the next field will be exposed. Any time a pattern spans more than one exposure field, a stitching error will occur such that the pattern will have a small disconnect at the edge of the write filed. In a well-designed e-beam mask, patterns should be spaced such that stitching error is eliminated or minimized. Patterns with and without stitching error are shown in figure Stitching error is non-trivial and must be handled with the proper care to avoid unexpected errors Resist Processes Multiple resist processes have been developed for use with e-beam lithography. A summary of these processes along with processes for resists used for contact based lithography is shown in table 2.3. All resists are removed using NMP at 60 C Negative Process Standard e-beam resists are positive resists in which the exposed area is removed in Table 2.3 Standard processes for commonly used resists

42 28 the developer solution. It is therefore less time consuming to remove a small area of resist than a large area. Removing a large area of resist is occasionally required in device processing which proves challenging for e-beam lithography. Ideally, a negative e-beam resist could be used to address this issue. The most common negative e-beam resist is SU-8 which is undesirable for some processes as the remaining resist after patterning cannot be removed easily [27]. A negative process has thus been developed in which a pattern is patterned by a positive resist and then the negative of that pattern is transferred to an oxide mask. First an e-beam resist (PMMA 950 C2 on PMGI SF9) is patterned and developed for which the negative image is the desired pattern. SiO 2 is then deposited by PECVD at 150 C which is below the glass transition temperature of the e-beam resist. A lift-off process is then performed by soaking the sample in NMP at 60 C. Following lift-off, the sample is annealed by RTA at 600 C for 60 s to densify the SiO 2. At this point the SiO 2 will be the negative of the original e-beam pattern and can be used for an etch pattern or otherwise. 2.7 Electrical characterization methods Measurement Equipment Electrical measurements were carried out using a Keithly 4200 SCS characterization system in conjunction with a Cascade Model probe station equipped with a chuck capable of measurement temperatures up to 200 C. An HP 4284 LCR meter was used for high frequency capacitance-voltage profiling. Many of the characterization methods presented in this dissertation are device specific and non-typical due to a novel device structure. The

43 29 measurement setup for these device specific measurements will be described in subsequent chapters Hall Effect Characterization The Hall effect is a commonly used semiconductor characterization technique which provides essential information about a semiconductor, namely, µ Hall and sheet carrier density n s. Several Hall effect measurement systems are commercially available with a typical Hall Effect measurement setup consists of (1) a movable/rotating sample holder, (2) a high power electromagnet, (3) a computer controlled current/voltage controller and measurement system, (4) an electromagnet power supply, (5) an electromagnet cooling system. The wellestablished method for obtaining n s and µ Hall by a traditional Hall effect measurement system has several disadvantages/limitations: (1) movable sample holders most often have fixed probe locations limiting sample size (2) sample holders are most commonly rotated 90 such that the sample may be moved between the plates of the electromagnet. The combination of 1 and 2 prevent wafer level testing of multiple samples and most systems require wafers to be diced before performing measurements. Thus, typical Hall measurements do not allow for production line characterization. (3) Probing the sample in traditional Hall setups is nontrivial with either large fixed probes causing difficulty in making electrical contact, or the requirement of wire bonding a lead to the semiconductor contact. These methods of probing require a large contact area which increase the test area size and reduce accuracy. (4) Electromagnet systems are costly. In order to reduce cost and increase the flexibility of Hall

44 30 effect measurements a new method for determining Hall parameters has been proposed and characterized Hall Effect in Equilibrium In equilibrium as given by the Boltzmann transport equation. ( ) Applying a magnetic field as gives For a case in which then Which gives

45 31 after neglecting the second order term dependent on B z. Rearranging and putting in terms of macroscopic parameters yields V Hall is the Hall voltage, n s is the sheet carrier density, W is the width of the sample in the y- direction and L is the length of the sample in the x-direction. For a commonly used square sample, W=L allowing for these geometric parameters to remain unknown. It is also useful to define the quantity defining R H as the Hall coefficient. It is apparent from these expressions that for a given I x the voltage V Hall may be measured electrically given the constraint of J y =0. Mobility can then be determined as where R s is the sheet resistance of the semiconductor which can be determined by the Van Der Pauw method or otherwise. Thus important semiconductor properties µ Hall and n s may be

46 32 determined electrically. Measurement considerations and sample geometry will be discussed in the next section Traditional Hall Effect Measurements A. Adjustments to V Hall There are several spurious voltages which arise during measurement of V Hall which can lead to error. These must be considered for determination of an appropriate procedure to measure V Hall. (1) The geometric misalignment between the contacts parallel to the hall voltage results in a significant error especially for small Hall voltages. This error, V M is proportional to measurement current and not magnetic field. (2) For a sample mounted to a measurement substrate which is subject to a thermal gradient transverse to the direction of the applied current, the contacts parallel to V Hall will make a thermoelectric couple and give rise to voltage V S. This effect is known as the Seebeck effect and is not proportional to current or magnetic field on the first order. (3) In the absence of an external thermal gradient there will exist an internal thermal gradient which is developed due to the difference in the Lorentz force (evxb) on cold (slow) and hot (fast) electrons. This internal thermal gradient generates a voltage V E which is proportional to both current and magnetic field. This effect is termed the Ettingshausen effect.

47 33 (4) In the presence of an external thermal gradient which results in a hot end and a cold end of the sample, there will be diffusion of electrons from the hot end to the cold end. This diffusion current will be subject to the Hall effect because of the applied magnetic field B z. The resulting voltage V N is proportional only to the magnetic field B z. This effect is known as the Nerst Effect. (5) In a similar manner to the Ettingshausen effect, the diffusion electrons from the Nerst Effect resulting from a thermal gradient will also be subject to the Hall effect. This will create a voltage V R known as the Righi-Leduc voltage which is proportional to magnetic field but not current. The total voltage measured is therefore [28] It will be shown that for both the typical measurement and the proposed new method for determining Hall characteristics that all spurious e.m.f.s may be canceled with the exception of the Ettingshausen voltage V E. B. Typical Measurement Following fabrication the sample is diced and mounted to a sample holder which is then placed between the plates of an electromagnet following sheet resistance extraction by Van Der Pauw method. In order to cancel the majority of spurious electromagnetic fields as described previously, several measurement directions and polarities are applied. Consider the

48 34 Figure 2.11 Typical Hall effect geometry and notation most common geometry presented in figure 2.11with contacts labeled 1-4. The current I 13P is the current between contacts 1 and 3 such that current is injected into contact 1 in the presence of a positive magnetic field. Like-wise the voltage V 24P is the voltage measure between contact 2 and 4 with the current injection and magnetic field conditions of I 13P. The procedure for determining the hall voltage is then [29] (1) Apply magnetic field in the positive z direction (2) Apply I 13P and measure V 24P (3) Reverse current applying I 31 and measuring V 24P (4) In the same fashion measure V 13P and V 31p with I 42 and I 24 (5) Reverse the magnetic field such that B z is now in the negative z direction (6) Measure V 24N, V 42N, V 13N and V 31N with I 13, I 31, I 42, and I 24, respectively

49 35 Table 2.4 Dependence of the spurious e.m.f.s on polarity of applied current and magnetic field Combining the voltages in the form [ ] Gives averaging can be achieved by also considering the set of measured voltages [ ] however measuring this additional set of voltages is not strictly necessary. Following this procedure, the spurious e.m.f.s whose polarities for each measurement condition are shown in table 2.4 are canceled, with the exception of V E. The measured Hall voltage is therefore dependent on both the Hall and Ettingshausen coefficients as

50 36 Figure 2.12 Commercially available Ecopia HMS-3000 Hall effect sample holder. This type of sample holder is typical of Hall effect measurement systems. It is apparent that due to the constraints of the sample holder that external contact area must be large. Additionally the sample size and contact location is strongly restricted and requires a wafer to be diced for testing where P is the Ettingshausen coefficient and Θ is the thermoelectric power. In most cases R H >>PΘ allowing for this term to be neglected. C. Contact Area Considerations In an ideal situation the contact area for the measured sample is considered to be infinitesimally small. In practice, contact size must be considered with larger contacts leading to increased error in the measurement of R S by the Van Der Pauw method and in R H utilizing the Hall effect. Chwang et al. theoretically determined an error factor in the Hall voltage for a square sample geometry with triangular contacts of finite size as ( )

51 37 Where θ is the Hall angle defined as and I s is the current flowing through the semiconductor[30]. Numerically solving this equation yields that for a contact of width δ and a sample of width l that an error of approximately 15 % will be seen for a contact width to sample width ratio of δ/l=1/6 (which is commonly used). For illustration, a commercially available Hall effect measurement sample holder is shown in figure 2.12 [31]. In order to accommodate this common type of sample holder contact areas need to be approximately 1 mm is size. In order to achieve an error of less than 15% of the measured Hall voltage, it is necessary to have a sample size of more than 6 mm 2 for this type of sample holder. It is possible to photolithographically define contacts which are small in area on the order 10 µm which substantially reduces the required sample area for accurate measurement; however there is still a requirement for large area contacts to connect to the external measurement units. It would therefore be desirable to implement a versatile Hall effect measurement which allows for both small internal and external contact sizes while minimizing the error induced by the δ/l ratio.

52 Proposed Novel Hall Effect Measurement A. Setup In order to reduce cost and increase measurement accuracy in a method suitable for both academic applications and high speed wafer level processing, a new method for determining Hall parameters is proposed. In this method, a permanent magnet (or series of permanent magnets) is utilized to apply the magnetic field. This removes the electromagnet from the measurement system reducing cost and allowing for increased measurement flexibility while enabling wafer level processing. This method will require that the fixed magnet provide a varying magnetic field. The magnetic field from a fixed magnet may be applied and varied by increasing or decreasing the distance between the sample surface and the permanent magnet. For a given magnet, that magnet may be affixed to a micro-positioner and the magnet raised or lowed. The magnetic field at several distances from the surface of the sample can be measured using a gaussmeter resulting in a known magnetic field value for a given height from the surface of the sample. The magnetic field may also be altered by using a series of progressively stronger fixed magnets of the same diameter such that a different magnet corresponds to a different magnetic field. An estimated 3 steps in magnetic field should prove sufficient for accurate measurement requiring 3 permanent magnets for this method. The diameter of the fixed magnet should be such that the area of the Hall measurement sample is << than the area of the magnet which minimizes variation in the magnetic field across the sample. Due to the reduced size of contacts which is facilitated by this method the previous constraint is easily achieved. In the proposed setup, a small fixed

53 39 Figure 2.13 Proposed setup for Hall effect measurements. By an inexpensive modification of commonly found electronic lab equipment with a permanent magnet affixed to a micropositioner, Hall effect measurements can be achieved. magnet is connected to a micro-positioner which is then placed underneath the sample for testing which is held at a fixed height. The magnetic field is increased by moving the surface of the permanent magnet closer the sample surface. Since B z α 1/r 3 only a very small change in micro-positioner distance is necessary to apply steps in the magnetic field allowing for a low profile design. This micro-positioner and magnet setup can thus be inserted into a typical academic probe station and connected to commonly available IV meter/sources. Figure 2.13 shows a schematic diagram of the proposed setup. B. Measurement By utilizing the following procedure it will be possible to determine Hall parameters by an inexpensive non-destructive modification of a common electronic research lab setup. Consider applying a known linearly varying with time current of the form

54 40 Measuring the Hall voltage gives ( ) Where V 0 is, and taking the term This expression is approximate as the Hall factor, r H, is dependent on scattering mechanisms and temperature but is often taken to be one due to the complexity and often unknown mechanisms of scattering in the sample to be characterized. Additionally, applying a time varying current I with time invalidates the equilibrium condition which was assumed when deriving the Hall voltage from the Boltzmann transport equation. When a applying the linearly varying current m I, which is a measurement parameter, m I should be small such that I is slowly varying with time. Under this condition I x0+δt I x0 and the solutions to the Boltzmann transport equation are approximately correct. Taking the derivative of the measured Hall voltage and

55 41 Since V S, V N, and V R do not depend on current such that Differentiating again with respect to magnetic field B z is independent of magnetic field yielding Rewriting ( ) for <<

56 42 The following method can thus be used extract the Hall voltage. The magnetic field for a given magnet or separation from the sample is measured (if unknown). A known current linearly varying with time is applied. The hall voltage is simultaneously measured with respect to time. The magnetic field is then increased. V Hall is then plotted as a function of time for each magnetic field with V Hall varying linearly with respect to time. A linear fit is applied to curve resulting in an average. This averaging increasing the measurement accuracy as several hundred measurement samples may be accounted for very quickly. The slope of the fitted curves corresponding to is then plotted against the measured magnetic field. This curve is then linearly fitted with the slope equivalent to. Sheet carrier density can now be extracted with value of m I known. R s can be measured by the Van der Pauw method or some other method allowing for the extraction of µ Hall by Unlike other averaging Hall Effect methods which utilize pulsed current [32], this method does not require a pulse generator, oscilloscope or voltage amplifier. Additionally the slope of the applied current m I can be altered with increased m I allowing for a smaller magnetic field to be applied for the measurement or for lower magnitude mobility to be measured with a fixed magnetic field.

57 Experimental Proof of Concept As a proof of concept, experimental results will be presented utilizing this proposed method of Hall effect characterization. Measured samples consist of square Hall effect structures on an AlGaN/GaN heterostructure with 100 µm Ti/Al/Ni/Au contacts. Contacts are labeled 1-4 as seen in figure Current is applied between contacts 1 and 3 (I 13 ) with a slope of m I =5.095 ua/s and Hall voltage (V 24 ) is measured as a function of time. Current is applied using a Keithly 4200 SCS system by current ramping between 30 ua and 100 ua. Ramp rate m I can be altered by altering the measurement speed time constant in the Keithly 4200 Figure 2.14 Hall voltage measured as a function of time for a magnetic field increasing in increments. A linear dependence of V Hall on time can be seen, as expected. The applied time varying current is also depicted

58 44 control software (KITE). Hall voltage is simultaneously measured using the Keithly 4200 system. Magnetic field was applied by placing the test sample on a flat, circular permanent magnet with an area much greater than that of the Hall test sample. Magnetic field was measured at the surface of the device under test with a gaussmeter. Following current application and voltage measurement, the magnetic field is increased by stacking another permanent magnet on top of the original magnet. This increases the magnetic field seen by the sample when placed on top of the magnet stack. Again, this magnetic field is measured by gaussmeter and current is applied and Hall voltage measured. A final magnetic field step was performed by adding another permanent magnet to the magnet stack for a total of 3 magnets. The measured Hall voltage for several steps of magnetic field is shown in figure Taking the average slope of the Hall voltage over time curves allows for the determination of as seen in Figure The extracted sheet carrier density for these samples is 7.22 x10 12 which is near the expected value of 8 x10 12 based on material parameters. The corresponding mobility value for this sample is 1627 cm 2 /Vs which corresponds well with electrical measurements. Additionally, from figure 2.15 it can be seen that for this range of magnetic field a linear fit is a good approximation. This corresponds with the assumption << further validating this procedure. This method allows for a drastic reduction in the cost and complexity of obtaining Hall effect measurements and additionally allows for wafer level Hall effect measurements. Further Hall Effect measurements presented in this work will be obtained by this method.

59 45 Figure 2.15 Averaged slope of V Hall for different magnetic fields. The slope of this plot corresponds to and allows for the extraction of n s. 2.8 Physical characterization Scanning Electron Microscopy Scanning electron microscopy (SEM) allows for the magnification and imaging of features down to 15 nm and is a critical feature of electron beam lithography. The operating principle of SEM is that a beam of electrons is rastered in vacuum across the surface of the sample to be imaged. Electrons for the beam collide with the surface of the sample and transfer some portion of their energy to secondary electrons from the surface. If these secondary electrons have enough energy there are ejected from the sample being images and collected by a detector. The energy of these collected electrons is interpreted by the software as contrast and is then rastered to a computer monitor synched with the beam raster [33]. Features resolved with electron beam lithography can be as small as 10 nm and therefore SEM imaging is required for imaging critical electron beam lithography features.

60 46 Additionally, since electron beam lithography takes place in vacuum all visualization of the sample is done in real time using SEM. This is critical for alignment in electron beam lithography as SEM is used to find alignment marks and correlate the physical location of alignment marks with the programmed location of the alignment marks in the electron beam lithography mask X-ray Photoelectron Spectroscopy X-ray photoelectron spectroscopy (XPS) is a powerful tool which allows the chemical composition and chemical interactions between materials to be analyzed. In the XPS measurement technique an X-ray source of a known energy is focused on the surface of the sample under test. The energy from the X-ray is transferred to the electrons in the sample resulting in the ejection of the electrons from the sample. These ejected electrons are collected utilizing a cylindrical mirror analyzer which extracts the number of electrons as a function of kinetic energy. The resulting spectrum of intensity as a function of kinetic energy allows for the extraction of numerous material parameters [34]. Many dielectrics presented in this work had not previously been deposited on GaN making XPS an extremely useful tool for determining dielectric and interface properties. XPS analysis is performed ex situ using a Kratos Axis Ultra spectrometer equipped with a monochromatic Al Kα X-ray source ( ev) with a pass energy of 20 ev and a 90 or 30 take-off angle (normal to surface) with the charge neutralizer on. All samples are

61 47 referenced to the 285 ev peak of adventitious carbon to account for charging and calibration effects. 2.9 Simulation Simulations were performed using Sentaurus TCAD simulator. The simulator solves finite difference equations at each point of a mesh representing the device under simulation. At each mesh point in the presented simulation data, Poisson and continuity equations for both holes and electrons were solved. To simplify simulations and aid in conversion several simplifications have been used. (1) The two dimensional electron gas is represented as a continuous sheet charge at the AlGaN/GaN interface (2) A GaN capping layer has not been included in the simulation (3) There are no charges in the bulk of the gate dielectrics or at the dielectric interfaces (4) There are no charges or traps in the bulk of the GaN or AlGaN (5) Ohmic contacts are assumed and represented as highly doped AlGaN in contact with the 2DEG (6) Metals for floating gate simulation are represented as semiconductors with an electron affinity that is equal to the work function of the metal being represented and a band gap of 25 mev. This representation aids in simulation conversion. At

62 48 room temperature all electrons reside in the conduction band of the metalsemiconductor which accurately represents the free electrons at the energy level of the work function of a metal. (7) Fowler-Nordheim tunneling is the only tunneling model considered

63 49 Figure 3.1 Ga 2p 3/2 spectra for the GaN surface before and after cleaning with NH 4 OH and HCl+HF chemistries. Both chemical treatments succeed in partially, but not completely, removing Ga 2 O 3. 3 PRELIMINARY GATE DIELECTRIC EVALUATION 3.1 Chapter Introduction The choice of gate dielectric for a MOS-HFET will strongly affect device characteristics. Potential gate dielectric materials are characterized and evaluated in this chapter. The critical process steps developed for a GaN MOS-HFET process flow which enable dielectric evaluation are also presented. 3.2 Surface Cleaning Gallium nitride will form a thin native oxide of mostly Ga 2 O 3 [35] in air ambient which will impact the dielectric/gan interface for a deposited dielectric. Therefore, before

64 50 beginning characterization of dielectrics on GaN it is necessary to establish an appropriate surface cleaning method. Multiple surface cleaning techniques have been reported in literature with the most common chemical cleans consisting of NH 4 OH or HCl followed by HF chemistries [36]. To evaluate the efficacy of these cleaning chemistries GaN samples were prepared for characterization utilizing either a NH 4 OH or an HCl and HF clean. Samples receiving the NH 4 OH clean were soaked in NH 4 OH for 1 min at room temperature. Samples with the acid clean were exposed to HCl:H 2 O 1:1 for 1 min followed by HF 1% for one minute. These samples, as well as samples in the as received (no clean) condition were then characterized by XPS. All samples were cleaned ex-situ and exposed to air ambient for approximately two hours prior to sample loading in the XPS chamber. It is expected that some native oxide growth will occur during this exposure to ambient. The Ga 2p 3/2 spectra for each cleaning condition are shown in figure 3.1 for two incidence angles. The GaN substrate peak can be seen at , which corresponds to Ga-N bonding [37]. The Ga-O peak at separated 0.9 ev from the main peak corresponds to the Ga 3+ bonding of Ga 2 O 3 [38], [39]. The relative concentration of Ga-O and Ga-N bonding was fit using these peak positions, the 0.1 ev measurement error expected in these measurements may slightly alter fitted peak profiles. A reduction in the intensity of the Ga-O peak is observed for both NH 4 OH and HCl+HF cleans, however, neither cleaning method was able to completely remove the Ga-O peak [40]. It is expected that ex-situ measurement with exposure to ambient air for an extended time period prior to XPS measurement results in oxide formation after cleaning. The oxygen coverage for oxidation of Ga (0001) in oxygen ambient as

65 51 reported by Janzen et al. is saturated at approximately 0.79 monolayers at room temperature [41]. HCl+HF cleaning is seen to be slightly more effective at removing surface oxides than NH 4 OH as seen in the more surface resolved spectra at the incidence angle of 30. In order to further evaluate the surface clean, back to back capacitors were fabricated on HCl+HF cleaned GaN and untreated GaN. Capacitance voltage characteristics for these conditions with an 11 nm Al 2 O 3 dielectric are seen in figure 3.2. In the case without cleaning the hysteresis is non-symmetric corresponding to a high interface state density. Following acid cleaning, the hysteresis becomes symmetric and reduces in magnitude. This symmetric behavior is an indicator of an improved GaN/Al 2 O 3 interface with the observed hysteresis coming from bulk traps in the Al 2 O 3. HCl+HF cleaning will therefore be used for inorganic surface cleaning before dielectric and metal depositions on the GaN surface. Figure 3.2 Capacitance voltage characteristic at 1 MHz for HCl+HF cleaned samples as well as samples without surface cleaning.

66 Post Dielectric Annealing Following ALD deposition, densification of the oxide is achieved by rapid thermal annealing (RTA) at temperatures in the range of C [42]. In other Ga based systems, such as GaAs, temperatures of 600 C will result in oxide formation at the material surface [43]. This oxide formation can result in reduced interface quality with a deposited dielectric. In order to ensure the stability of the GaN interface during RTA of the ALD oxide, XPS measurements were performed for samples with a thin Al 2 O 3 dielectric deposited by ALD and annealed at various temperatures. Samples were first cleaned utilizing HCl followed by HF and immediately loaded into the ALD chamber. Al 2 O 3 was deposited at 150 C after which samples were then removed from the ALD chamber and loaded into the RTA system. Samples were exposed to ambient air for approximately one hour during transfer and loading time. Al 2 O 3 has been demonstrated as an excellent capping layer in ambient air for time periods of more than one month and it is therefore expected that no Ga 2 O 3 growth occurs during this time due to air ambient [44]. GaN on Si samples were annealed in a Heatpulse 210 system with temperature monitored by a Si thermal couple in close proximity to the sample. The temperature measured by this thermal couple is an approximate value for the GaN epitaxial layer temperature. The wide band gap of GaN will mostly transmit the IR radiation provided by W halogen bulbs used in the RTA system. Sample heating is therefore mainly achieved in the Si substrate layer and transferred by conduction to the relatively thin GaN epitaxial layer. It is expected that the error in temperature is small, but not negligible given the relative thinness of the GaN compared with the Si substrate. The Ga 2p 3/2 XPS spectra for these samples taken ex-situ following RTA are seen in figure 3.3. As shown, there

67 53 Figure 3.3 Ga 2p 2/3 spectra for thin Al 2 O 3 on GaN. Annealing temperatures up to 600 C do not result in additional interfacial oxide growth is no increase in the concentration of Ga-O bonding with annealing temperatures up to 600 C suggesting that the GaN/dielectric interface remains stable to at least 600 C. 3.4 Preliminary Electrical Evaluation Gate dielectrics Al 2 O 3, HfAlO and SiO 2 were selected for evaluation, deposited by ALD and evaluated using the back to back capacitor fabrication procedure. All dielectrics received a post deposition rapid thermal anneal at 600 C for 60 s. HfAlO and ALD SiO 2 were previously unexplored for GaN devices. Capacitance voltage profiles for the back to back capacitors with each dielectric are shown in figure 3.4. The dielectric constant of each dielectric is extracted from the accumulation capacitance of the 2DEG. As expected, HfAlO has the highest dielectric constant of k=13, with Al 2 O 3 having k=8 and SiO 2 with k=3.9.

68 54 Figure khz capacitance voltage profile for Al 2 O 3, HfAlO and SiO 2 back to back capacitors. Dielectric constant k is extracted from 2DEG accumulation capacitance Figure 3.5 Integration of the C-V profile for back to back capacitors allows the expected threshold voltage for an MOS-HFET device to be extracted by linear extrapolation. 2DEG Charge at 0 bias can also be determined. Integrating the capacitance-voltage profile allows for the sheet charge concentration as well as the expected threshold voltage for a MOS-HFET device to be extrapolated [45]. The integrated capacitance voltage profile for each dielectric is shown in figure 3.5. The expected threshold voltage for the Al 2 O 3 device is -4.3 V by linear extrapolation. HfAlO and SiO 2 show threshold voltages of -3.7 V and -2.1 V respectively. Figure 3.6 shows the threshold voltage of Al 2 O 3, HfAlO and SiO 2 in comparison to previously reported dielectrics. With enhancement mode operation in mind, ALD SiO 2

69 55 Figure 3.6 Threshold voltage comparison from literature appears particularly attractive with a threshold voltage approximately 2 V closer to zero than other previously reported dielectrics (including SiO 2 by PECVD). Threshold voltage information as conveyed in figure 3.6 allows for a quick understanding of threshold voltage trends but has the potential to be misleading. Threshold voltage will decrease with increased gate dielectric thickness because of the increased gate/2deg separation according to the relationship ( ) ( ) where V Schottky is the threshold voltage that would be obtained by forming the same gate stack without a gate dielectric. This voltage V Schottky is equivalent to the threshold voltage of a HFET device. As the capacitance of the gate dielectric increases either by decreasing dielectric thickness or by an increase in dielectric constant, the threshold voltage will move

70 56 Figure 3.7 Threshold voltage as a function of EOT. Dotted and dashed lines are isocoulombic lines for increasing dielectric charge represented as fixed charge at the dielectric interface. in the positive direction. Therefore to more accurately assess threshold voltage information, V T can be plotted as a function of EOT as seen in Figure 3.7. This representation normalizes dielectric constant allowing for dielectrics of the same EOT to be represented. Inserting the dielectric capacitance into equation 3.1 yields ( ) ( ) As seen in equation 3.2, threshold voltage linearly increases relative to EOT with a slope of ( ). The dashed line in figure 3.7 labeled expected threshold voltage displays the line described in equation 3.2. For the dashed line, the gate stack is ideal without

71 57 any dielectric charge, interface charges or dipole effects. The dotted lines are isocoulombic lines of the same slope for cases of higher charge concentrations. Following these lines visually allows dielectrics of different EOT to be compared relative to one another where the perpendicular distance between the dielectric and a dashed line represents the level of charge in the gate stack. A lower charge concentration will thus lead to a more positive threshold voltage for the same EOT. In both representations of threshold voltage, it can be seen that ALD SiO 2 provides the most positive threshold voltage of any previously reported dielectric. Additionally, ALD of lower dielectric constant SiO 2 warrants investigation with potential for lower-k passivation and reduced gate leakage due to the high band gap of SiO 2. For this reason, ALD SiO 2 was selected as a MOS-HFET gate dielectric for further evaluation. 3.5 Band Alignment of ALD SiO 2, HfAlO, HfO 2 and Al 2 O 3 To further understand the physical properties of ALD dielectrics, the band alignment of the dielectric with GaN should be experimentally determined. The band gap and conduction band offset of gate and passivation dielectrics on GaN will have a strong effect on device performance. Leakage current is correlated to conduction band offset with band offsets less than 1 ev considered unsuitable for low leakage dielectric applications [46]. Additionally, larger conduction band offsets can lead to improved reliability by reducing hot carrier effects and current driven dielectric degradation. The band alignment of many ALD dielectrics on GaN remains unreported, and in cases where valence band offsets between GaN and a dielectric are reported the conduction band offset is given based on an assumed

72 58 band gap value [46], [47]. Dielectrics deposited by atomic layer deposition often have a smaller band gap than their bulk crystalline counterparts [48] as ALD dielectrics tend to be amorphous or nanocrystalline which changes the atomic ordering consequently effecting band gap. Al 2 O 3 is a prime example of this with crystalline Al 2 O 3 (sapphire) having a band gap of 8.8 while Al 2 O 3 deposited by ALD shows a band gap ranging from [13], [48]. Therefore, to accurately determine conduction band offset both valence band offset and band gap must be measured for the given dielectric/substrate. Utilizing XPS the band alignment of SiO 2, HfO 2, Al 2 O 3 and HfAlO dielectrics deposited by ALD on GaN (0001) was determined. Valance band offset as well as band gap was measured in order to accurately determine conduction band offset. GaN (0001) samples grown by MOCVD on Si substrates by Nitronex Corporation were prepared for XPS. Samples were cleaned in an HCl:H 2 O 1:1 solution followed by HF 1% cleaning. Immediately following cleaning, samples were loaded into the ALD chamber. Two samples were prepared for each dielectric; a thin sample with thickness of 2 nm and a thick sample with thickness of 10 nm (30 nm for SiO 2 ). Al 2 O 3 was deposited at 200 C using trimethylaluminum (TMA) and water precursors. HfO 2 was deposited at 200 C using tetrakis(dimethylamido)hafnium[iv] (TDMAH) precursors and water. HfAlO was deposited at 200 C by alternatingly depositing 1 cycle of Al 2 O 3 followed by 1 cycle of HfO 2. SiO 2 deposition was performed at 150 C with 3-Aminopropyltriethoxysilane (APTS), ozone and water precursors. Following atomic layer deposition, all samples were annealed at 600 C

73 59 Figure 3.8 N 1s and Ga 3d core level spectra for the GaN substrate following clean and for each dielectric. The shift in binding energy observed for HfO 2, HfAlO and Al 2 O 3 dielectrics corresponds to band bending at the GaN dielectric interface for 60 s in N 2 ambient. XPS measurements were performed ex-situ with samples exposed to air ambient for approximately 1 day following ALD deposition. Figure 3.8 depicts the N 1s and Ga 3d core level spectra for the substrate following acid cleaning as well as for each dielectric as obtained by XPS. The peak at ev in the N 1s spectra observed for clean GaN and GaN with SiO 2 dielectric corresponds to N-Ga bonding from the GaN substrate [49]. However, a shift in the N core level peak position from ev to ev is observed for samples with Al 2 O 3, HfO 2 and HfAlO dielectrics. A similar cove level shift was observed from the Ga 3d core level spectra as shown in figure 3.8(b). The peak observed at 20.1 ev for clean GaN and GaN with SiO 2 corresponds to Ga-N

74 60 bonding [49] whereas peak position for samples with Al 2 O 3, HfO 2 and HfAlO dielectrics are located at 19.7 ev. This shift in peak position of 0.4 ev seen in both N 1s and Ga 3d spectra is characteristic of band bending at the GaN dielectric interface. A shift to lower binding energy corresponds to upward band bending at the semiconductor dielectric interface [50]. The spontaneous and piezoelectric polarization of the GaN (0001) surface will result in bound negative charge at the surface. This charge will be screened by ionized donors resulting in upward band bending [47], [50]. The GaN valance band maximum is referenced to the Fermi level at the surface of the sample. The measured GaN valance band maximum is therefore the difference between the GaN Fermi level and the energy of the surface of the sample inclusive of band bending.the photoelectron escape depth for this measurement is approximately ~2 nm with an expected band bending width of ~100 nm. The small escape depth length relative to the band bending width results in negligible variation in the measured surface energy due to band bending at the GaN surface [51]. Valence band offset measurements were performed according to Krauts method [51]. According to this method the energy separation between the substrate core level and the valence band edge is the same before and after dielectric deposition. Valence band offset can be calculated according to the following equation ( ) ( ) ( ) ( )

75 61 where Ga 3d is selected as the reference core level for the substrate. The reference selected for SiO 2 is Si 2s due to its overlap in energy range with the Ga 3s peak. For HfO 2 the reference is Hf 4f 7/2 and for Al 2 O 3 as well as HfAlO, Al 2p 3/2 is used as the reference. XPS spectra for thin and thick dielectrics are shown in figure 3.9. The energy peak in figure 3.9(a) at corresponds to Si-O bonding [52]. The peak in figure 3.9(b) at 16.9 corresponds to Hf-O bonding in the HfO 2 dielectric [53]. The Al 2p spectra in figure 3.9(c) show a peak at 74.8 corresponding to Al 2 O 3 bonding [54]. The Al 2p spectra for HfAlO with a peak at 74.4 are shown in figure 3.9(d). The shift in binding energy of the Al 2p 3/2 peak seen in figure 3.9(d) corresponds to a laminate HfAlO rather than a layered HfO 2, Al 2 O 3 dielectric [13]. For all dielectrics it can be seen that the peak position for thin and thick dielectrics are identical. Figure 3.9 XPS spectra for thin and thick dielectrics. Ga 3s (a) and 3d (b) peaks can be seen for samples with thin dielectrics

76 62 Therefore ( ) allowing equation 3.5 to be simplified as ( ) ( ) Valence band maximum (VBM) was found by linear extrapolation of the leading edge of the valence band spectra as illustrated in figure The position of the VBM was determined to be 2.72 ev for the GaN sample following acid cleaning. VBM was measure as 5.08 ev for SiO 2, 2.81 ev for HfO 2, 3.56 ev for Al 2 O 3 and 3.11 ev for HfAlO. Valence band offset at the GaN/dielectric interface was determined utilizing equation 3.4 to be 2.36 ev for SiO 2, Figure 3.10 Valence band spectra for clean substrate and each dielectric

77 63 Figure 3.11 O 1s energy loss spectra for band gap determination of each dielectric 0.49 ev for HfO 2, 1.24 ev for Al 2 O 3 and 0.79 ev for HfAlO. Conduction band offset can be determined by ( ) ( ) ( ) The XPS O 1s spectra for thick Al 2 O 3, HfO 2, HfAlO, and SiO 2 films are shown in figure The onset of single particle excitation or band-to-band transition can be used to determine the band gap of the dielectric [55]. The measured band gap for SiO 2 is 8.8 ev as given by linear extrapolation. The measured band gaps for Al 2 O 3, HfAlO and HfO 2 are 6.7 ev, 6.4 ev, and 5.2 ev respectively. Figure 3.12 schematically shows the band alignment of these dielectrics at room temperature. The conduction band offsets for SiO 2, Al 2 O 3, HfAlO and HfO 2 are 3.04 ev, 2.06 ev, 2.21 ev and 1.31 ev respectively. SiO 2, as expected, has the highest conduction band offset resulting from its large band gap. Of particular interest is the conduction band offset of HfAlO which is measured to be larger than the conduction band offset of Al 2 O 3. This larger conduction band offset will result in lower leakage characteristics

78 64 Figure 3.12 Schematic band alignment for SiO 2, Al 2 O 3, HfO 2 and HfAlO dielectrics on GaN (0001) for MOS gated devices. Large conduction band offset combined with an increased dielectric constant of HfAlO over Al 2 O 3, which allows for increased dielectric thickness for the same EOT, suggests that HfAlO is an excellent candidate for high-k MOS gated devices.

79 65 4 MOS-HFET DEVICES 4.1 Introduction to Chapter Back to back capacitor results and XPS measurements presented in chapter 3 suggest that both SiO 2 and HfAlO are good gate dielectric candidates for a MOS-HFET device. SiO 2 has a large band offset which has the potential to provide for low leakage. The relative dielectric constant of 3.9 for SiO 2 is also interesting because it has potential to minimize the capacitance in the passivation region of the MOS-HFET which in turn increases the potential operating frequency of the device. In addition to capacitive effects, dielectric constant will also change the field distribution of a device. When an electric field is applied at the SiO 2 /GaN interface, the interaction between the low dielectric constant of SiO 2 (k=3.9) and the higher dielectric constant of GaN (k=8.9) results in roughly twice as much electric field supported in an SiO 2 relative to a GaN layer. In cases where field is particularly high, such as the drain-side gate edge of a power device, minimizing the field in the GaN and AlGaN layers can reduce the stress in those layers and prevent current collapse induced performance degradation [56]. In contrast to the SiO 2 case, HfAlO has a higher dielectric constant of k=13. While a higher dielectric constant will increase the passivation capacitance, it will also increase the gate capacitance. As seen in equation 3.1, increasing the gate dielectric capacitance will result in a more positive threshold voltage. A high dielectric constant film can also be thicker than a lower-k film while maintaining the same capacitance. This increase in physical thickness will reduce the leakage current of a MOS-HFET device. In this chapter MOS-

80 66 Figure 4.1 Cross sectional TEM of the SiO 2 /GaN interface HFETs with SiO 2 or HfAlO gate dielectrics will be characterized and compared. Gate recess for threshold voltage shifting with a SiO 2 dielectric will also be evaluated. 4.2 ALD SiO 2 MOS-HFET Experimental Al 0.26 Ga 0.74 N/GaN heterostructures on a Si substrate were received from Nitronex Corporation. The buffer and transition layer thickness is 1.8 µm followed by a 17.5 nm Al 0.26 Ga 0.74 N barrier layer and terminated with a 2 nm GaN capping layer. Prior to contact formation and gate dielectric formation, devices underwent a solvent clean followed by an HCl: H2O 1:1 dip. Contacts were formed by RF sputtering of Ti/Al/Ni metals followed by Ti/Au deposition via electron beam deposition. Mesa isolation was performed by inductively coupled plasma reactive ion etching (ICPRIE) employing BCl 3 for 3 minutes with an RF power of 100 W and an ICP power of 300 W. SiO 2 gate dielectric was deposited by ALD at 150 C using 3-Aminopropyltriethoxysilane, ozone and water precursors [57]. The dielectric

81 67 thickness is 70 Å with a growth rate of 0.5 Å/cycle. Following dielectric deposition, samples undergo rapid thermal annealing (RTA) at 600 C for 60 s in N 2 ambient. For comparison, Schottky gated HFET devices were fabricated in tandem with MOS-HFET devices. In Schottky gated HFET samples, SiO 2 is etched in the gate region prior to gate metal deposition. ALD SiO 2 serves as passivation for both HFET and MOS-HFET devices. TaN gate metal capped with W was deposited by RF sputtering. A 400 C RTA for 60 s in N 2 following gate deposition serves to reduce sputtering damage. MOS-HFET devices had gate lengths of 50 µm or 7 µm. 4.3 ALD SiO 2 MOS-HFET Characteristics A high-resolution transmission electron microscopy (HR-TEM) image of the ALD Figure 4.2 O 1s (a) and Si 2p (b) XPS spectra with binding energy peaks corresponding to fully oxidized SiO 2. XPS spectrum of clean GaN surface (c) and GaN/SiO 2 interface (d) with thin (~2 nm) SiO 2.

82 68 SiO 2 interface with GaN is shown in figure 4.1. A sharp interface between GaN and SiO 2 indicates minimal reaction at the interface and suggests a good GaN/SiO 2 interface. The measured SiO 2 thickness from the TEM image is 7 nm which corresponds well to the electrically extracted oxide thickness. To gain further insight into the quality of ALD SiO 2 and interfacial reaction, XPS analysis was performed. Figure 4.2 (a) and (b) illustrate O 1s and Si 2p core level XPS spectra from a 7 nm SiO 2 film. The O 1s peak position in Figure 4.2(a) occurs at ev while The Si 2p peak position in Figure 4.2 (b) occurs at ev. Both peaks are a strong evidence of silicon bound to oxygen and the binding energy position correlates well with that for Si-O bonding as observed by others [58], [59]. Thus, a fully oxidized, stoichiometric SiO 2 film is formed during this ALD process. In order to further investigate the interfacial layer formation between the dielectric and GaN, a 2nm SiO 2 film on the GaN substrate was prepared and analyzed by XPS. Figure 4.2 (c) shows the Ga 2p 3/2 spectra for the GaN substrate following acid cleaning. The Ga 2p 3/2 spectra with 2nm SiO 2 on GaN is shown in Figure 4.2 (d). The main peak at ev is attributed to Ga-N bonding from the GaN and the AlGaN layers [60]. A second peak at ev corresponds to Ga-O bonding attributed to Ga 2 O 3 or Ga 3+ oxide of gallium [61], [62]. Following ALD deposition of SiO 2, there is negligible change in the Ga-O peak intensity suggesting negligible interfacial Ga 2 O 3 growth during ALD process or post dielectric annealing. This result agrees well with the interfacial Ga 2 O 3 data presented in chapter 3 for the case of an Al 2 O 3 dielectric. The band gap of SiO 2 reported in chapter 3 is 8.8 ev, suggesting bulk film properties similar to thermal SiO 2 formed on Si substrates. To further compare ALD SiO 2 to thermal SiO 2

83 69 grown on Si, the oxide etch rate in 1 % HF solution was measured. The etch rate of ALD SiO 2 is 1.1 Å/s as compared to the ~1 Å/s etch rate of thermal SiO 2 [63]. Split C-V curves for the MOS-HFET device are shown in Figure 4.3(a). Hysteresis is less than 100 mv and there is negligible frequency dispersion between the 10 khz, 100 khz and 1 MHz C-V curves indicating minimal oxide and interface trapping and indicating a high quality film. Based on the film thickness extracted from TEM and the measured capacitance, the dielectric constant of ALD SiO 2 on GaN was found to be 3.9 agreeing with the measured dielectric constant from back to back capacitors. This value further validates the bulk properties of ALD SiO 2 as being comparable to thermal SiO 2. Expected threshold voltage for a MOS-HFET device relative to a HFET device can be extracted from capacitance values according to equation 3.1. The expected threshold for SiO 2 was found to be = -2V. Figure 4.3(b) shows the I ds -V gs characteristics at V DS of 10V. The extracted threshold voltage is -1.5 V at V DS =250 mv which is the most positive reported value for a MOS-HFET device with a similar AlGaN/GaN heterostructure and dielectric thickness [64]-[72]. This relative positive threshold voltage from the calculated value is attributed to a fixed negative charge concentration of -1.6x10 12 charges/cm 2 as compared with PECVD SiO 2 gate dielectric on GaN reported with charge concentrations of 8.6x10 12 [73]. Atomic layer deposition of SiO 2 permits the combination of lower absolute charge concentration and negative charge polarity corresponding to a threshold voltage with a slight, favorable shift from ideal. Figure 4.3 (c) illustrates off-state characteristics with I ON /I OFF greater than 9 orders of magnitude for V DS of 10 V. Figure 4.3 (d) shows gate leakage current characteristics for the SiO 2 MOS-HFET and

84 70 Schottky HFET. ALD SiO 2 reduces gate leakage by 3 orders of magnitude over the Schottky gated case as expected for a MOS-HFET compared with a conventional HFET. In order to assess the passivation properties of ALD SiO 2, I DS -V DS characteristics Figure 4.3 Electrical characteristics of MOS-HFET with 7 nm SiO 2 gate dielectric. (a) Split C- V for SiO 2 including frequency dispersion and hysteresis. (b) HFET and SiO 2 MOS-HFET I d - V g and transconductance. (c) MOS-HFET off current with V DS =10 and two terminal gate leakage characteristics (d). (e) DC and pulse I d -V d with gate bias pulse width of 100 ns for a gate length of 50 µm. (f) Specific on resistance and breakdown voltage for MOS-HFET devices with L of 7 µm.

85 71 under DC gate bias and pulsed gate bias are shown in figure 4.3 (e). In this measurement the gate bias is pulse from zero volts to the step voltage with a pulse width of 100 ns. MOS- HFET devices show good DC characteristics. Under pulse conditions, drain current is slightly reduced as compared with the DC case due to trapping effects. However, this pulse- DC dispersion is comparable to reported SiN passivation layers [74]. To further qualify ALD SiO 2 as a potential dielectric for GaN/AlGaN transistor applications, device breakdown characteristic of ALD SiO 2 MOS-HFET devices with L gd from 8 µm to 28 µm were fabricated. Three terminal breakdown voltage measurements with V G below pinch-off at -5 V are shown in figure 4.3 (f). MOS-HFET devices with ALD SiO 2 show a maximum breakdown voltage of 800 V with an on-resistance of 12.4 mω-cm ALD SiO 2 Conclusions Electrical characteristics of a GaN MOS-HFET with ALD SiO 2 have been demonstrated. ALD SiO 2 dielectric provides a large band gap with a high quality interface between GaN and ALD SiO 2 leading to low gate leakage and a promising V T for obtaining enhancement mode operation [75], [76].

86 72 Figure 4.4 I DS V GS characteristics at V DS =250 mv. Threshold extracted by the linear extrapolation method 4.5 ALD HfAlO and SiO 2 Comparison HfAlO was also explored as a possible gate and passivation dielectric and compared with ALD SiO 2 gate and passivation dielectrics. MOS-HFET devices were prepared as described in 4.2 with ALD HfAlO deposited by alternatingly depositing 3 layers of Al 2 O 3 and then 3 layers of HfO 2. After annealing at 600 C for 60s the laminate HfAlO is formed. The gate length for all samples is 50 µm. Transistor I DS V GS characteristics are shown in figure 4.4. Threshold voltages (V TH ) as determined by the linear extrapolation method are V for HfAlO, -1.5 V for SiO 2 and -1.0 V for the Schottky case. HfAlO dielectric is shifted from an expected V TH of -2.1 with a corresponding positive fixed oxide charge of +6.0x10 12 charges/cm 2. Similar shifts are reported for as-deposited Al 2 O 3 on GaN with fixed charge of +6.2 x10 12 charges/cm 2 [77]. I ds V gs characteristics under DC and pulsed gate bias are shown in figure 4.5. SiO 2 shows some small dispersion between DC and pulse

87 73 Figure 4.5 I DS V DS characteristics under DC and pulsed conditions. Gate voltage pulse has a width of 100 ns characteristics, DC and pulse characteristics for HfAlO are nearly identical suggesting minimal surface states and promoting HfAlO as a high quality passivation dielectric in the channel region. It has been demonstrated that moisture in ambient air has a strong effect on AC-DC dispersion in GaN transistor devices and that by applying a hydrophobic coating, AC-DC dispersion can be suppressed [78]. The passivation characteristics of HfAlO are likely a result of the increased hydrophobicity of Hf based films relative that of SiO 2 films [79]. SiO 2 is hydrophilic, with potential to draw moisture from the air resulting in the AC-DC dispersion. HfAlO, being hydrophobic, will effective seal the GaN surface from interaction with water vapour resulting in the elimination of AC-DC dispersion.

88 74 Figure 4.6 Gate leakage current density comparison Gate leakage current density as a function of applied bias is shown in figure 4.6. As compared with the Schottky gated case, SiO 2 and HfAlO have at least 3 orders of magnitude reduced gate leakage. MOS-HFET devices will substantially reduce losses as compared to the HFET case for power semiconductor devices. In the forward bias regime, the onset of Fowler-Nordheim (FN) tunnelling is seen at 1 V for SiO 2, whereas FN tunnelling starts at ~2 V for HfAlO. The lower dielectric constant of SiO 2 relative to AlGaN results in a larger field supported by SiO 2 which combined with the thinner physical thickness of SiO 2 relative to HfAlO allows for gate leakage via tunnelling at lower voltages. The high-k of HfAlO in the gate region reduces leakage above 0 V at the cost of the increased threshold voltage provided by low-k SiO 2.

89 75 Figure 4.7 MOS-HFET transconductances (measured at VDS=0.25V) corresponding to a high quality 2DEG MOSHFET transconductances are shown in figure 4.7. Extracting field effect mobility as given by L G m /(W Cox V ds ) gives a peak mobility for SiO 2 and HfAlO of 1527 cm 2 /V-s and 1437 cm 2 /V-s respectively and thus a high quality 2DEG remains intact for these dielectrics. Measuring transconductance at V DS =2 V and extracting the voltage range where G m is within 10 % of peak G m yields 49 mv for the HFET case, 54 mv for SiO 2 and 81 mv for HfAlO. Incorporating a gate dielectric increases transconductance linearity for both dielectrics with HfAlO having the strongest impacted on linearity increasing linearity by a factor of Technologies for Enhancement mode HFETs Enhancement mode operation is critical for power electronic transistors and several methods have been proposed to shift threshold voltage from the value below zero of a

90 76 Figure 4.8 Two dimensional electron gas concentration as a function of Al x Ga 1-x N thickness and Al concentration. Reducing AlGaN thickness or concentration reduces 2DEG concentration and can be used to shift threshold voltage in the positive direction at the expense of conductivity reduction standard HFET. The prominent methods of threshold shifting are gate recess etching [80] in which reactive ion etching is used to remove some of the AlGaN barrier layer under the gate. The reduction in barrier thickness reduces the 2DEG under the gate and shifts threshold voltage in the positive direction as seen in figure 4.8 [81]. There are several drawbacks to this approach (1) Reducing the 2DEG concentration inherently reduces device performance by limiting carrier concentration under the gate (2) Threshold voltage of more than 1 V is difficult to obtain (3) RIE of the surface damages the surface and can lead to reduced mobility

91 77 (4) RIE of the surface removes the GaN cap and exposes reactive AlGaN to atmosphere (5) Etch depth control is difficult unless some layer is intentionally grown as an etch stop within the AlGaN Layer (6) Large area etch uniformity is challenging While this method presents issues, barrier thickness reduction is a requirement for gate control in short gate length devices such as RF devices and therefore AlGaN etching is commonly used [82]. Fluorine plasma treatment [83] has also been demonstrated to shift threshold voltage in which fluorine ions are used to balance charge with the 2DEG therefore shifting the threshold voltage. This method provides for a threshold voltage very close to zero which prevents gate dielectric incorporation. P-GaN gate formation is another proposed method in which the gate metal is replaced by a P-GaN layer grown in-situ with the GaN and AlGaN barrier growth [84]. The P-type GaN layer increases the conduction band potential of the AlGaN barrier layer allowing for enhancement mode operation. This approach provides for a threshold voltage of 1 V but a gate dielectric cannot be incorporated and the growth technique requiring P-type GaN is challenging, proprietary and expensive. Piezoelectric neutralization [85] has also been proposed in which several charge inducing layers are grown on top of the AlGaN barrier reducing the 2DEG. This presents many of the challenges seen with the P-GaN gate with a difficult and expensive growth process. All of these methods are often used in combination with high work function metal gates to maximize V T. In all of the

92 78 Figure 4.9 Transfer I-V characteristics at V ds =1 V for 5nm gate recess with ALD SiO 2 dielectric. Gate recess allows for enhancement mode operation. described threshold shifting methods, obtaining a threshold voltage of more than 1V with incorporation of a gate dielectric to reduce leakage is unattainable. 4.7 Recessed Gate MOS-HFET The simplicity of the gate recess approach warrants further exploration of this method for obtaining enhancement mode, despite the drawbacks of this approach. Following the same experimental flow as the ALD SiO 2 MOS-HFET, gate recessed transistors were formed. For gate recess transistors, ~5 nm of AlGaN is etched under the gate region using ICP-RIE in BCl 3. I DS V GS characteristics and transconductance for a recessed gate device are shown in figure 4.9. The extracted threshold voltage for these devices is V TH =0.79 V. By combining gate recess and ALD SiO 2 dielectric, enhancement mode devices have been realized. The peak transconductance for recessed gate devices is 3 orders of magnitude lower

93 79 Figure 4.10 Output I-V characteristics for recessed gate transistor with ALD SiO 2 dielectric. than for those without gate recessing. It is expected that RIE of the semiconductor surface will damage the semiconductor resulting in reduced performance. The etching step also removes the thin GaN capping layer on AlGaN. Exposing AlGaN to atmosphere has the potential to form interfacial oxides which can further degrading channel mobility. Device transistor operation is verified in figure While enhancement mode operation is achieved with this approach, the current levels and transconductance are not acceptably high enough for the goals of this work. Rather than spend excessive time on refining the gate recess etch, which inherently reduces device performance, a new approach will be considered to obtain enhancement mode devices.

94 80 5 FLASH MOS-HFET 5.1 Flash MOS-HFET introduction In order to obtain a positive threshold voltage without degrading device performance a novel device structure has been designed, simulated and fabricated. This new device combines the operating principle of flash memory with the MOS-HFET device structure and will be referred to as a Flash MOS-HFET. The basic device structure is shown in figure 5.1. The device consists of source and drain contacts and a gate stack made of a thin tunnel dielectric and a charge storage layer followed by a thicker blocking dielectric. When high voltage is applied to the gate with source and drain held at ground, electrons tunnel from the 2DEG through the tunnel dielectric and are blocked by the thicker blocking dielectric. When gate bias is reduced the electrons are trapped in a potential well between the blocking dielectric and the tunnel dielectric and are stored. In a Flash MOS-HFET structure, charge is stored within the gate stack during an initial programming step known as charging or writing. Storage of negative charge results in a positive threshold voltage shift. With proper dielectric design and owning to the small concentration of holes (which could facilitate electron recombination) within the GaN material system, charge and correspondingly V T remains fixed. This theory of operation is the basis for Flash memory devices which are well established on Si. The origin of V T shift in the Flash MOS-HFET structure is independent of the substrate.

95 81 Figure 5.1 Cross-sectional view of FLASH MOS-HFET device 5.2 Flash MOS-HFET Simulation Simulations were performed using Sentaurus TCAD simulator. The structure as simulated is seen in figure nm SiO 2 is used for the tunnel dielectric in this simulation with a blocking dielectric consisting of 10 nm SiO 2. The charge storage layer is modeled as a continuous metal layer with a work function of 4.6 ev representing a TaN floating gate. Gate Figure 5.2 Synopsys TCAD structure for simulation of Flash MOS-HFET device

96 82 Figure 5.3 Threshold voltage shift after charging by applying high bias to the gate and holding source and drain at 0 volts. to drain spacing is 3 μm to minimize the number of simulated nodes. The simulation proceeds by first measuring I D -V G characteristics for the device. The gate is then swept to 20 V while holding source and drain at 0 V. Time transient simulations are then performed with the gate bias at 20V allowing for charge to tunnel to the storage layer by Fowler-Nordheim tunneling. Following charging, the I D -V G characterization is performed again. The simulated I D -V G characteristics before and after the charging step are shown in figure 5.3. Initially the device is depletion mode with a threshold voltage of -4 V. Following charging, the threshold voltage is shifted by 9 V in the positive direction resulting in a threshold voltage of 5 V. The I D -V G characteristics display a parallel shift in threshold voltage without degradation of the current level from a depletion mode device to and enhancement mode device.

97 83 Figure 5.4 Conduction band profile before and after charging showing the conduction band rising above the Fermi level after charging The zero bias conduction band profile before and after the charging step can be seen in figure 5.4. Before charging, the Fermi level intersects with the conduction band profile in the 2DEG region. The 2DEG is populated in this state resulting in the normally-on operation observed in the I D -V G curve before charging. After charging, the charge stored in the metal layer lifts the conduction band potential so that the 2DEG gas is no longer populated at zero bias resulting in an enhancement mode device. Charge concentration as a function of charging time is shown in figure 5.5. After a charging time of approximately 200 ms the stored charge concentration begins to saturate, limiting the maximum threshold voltage shift of the device. Simulation suggests that the Flash MOS-HFET, with a threshold voltage of 5 V while incorporating a gate dielectric, is a potential solution to obtaining enhancement mode GaN MOS-HFET devices without sacrificing performance.

98 84 Figure 5.5 Simulated sheet charge concentration as a function of charging time on a log (a) and linear (b) time scale. Saturation of charge concentration can be seen for charging times greater than 200 ms. Charge polarity is negative. 5.3 Flash MOS-HFET Fabrication Substrates received from Nitronex Corporation consist of a 2 nm GaN capping layer, a 17.5 nm Al 0.26 Ga 0.74 N barrier layer and a 1.8 µm GaN buffer and transition layer grown on Figure 5.6 Band diagram illustrating the energy bands of the blocking dielectric with an applied gate bias of 15 V. For the case of HAH blocking dielectric (solid), electrons have a longer tunneling distance than for the case of a single Al 2 O 3 blocking dielectric (dot).

99 85 Si. HCl:H 2 O 1:1 and HF 1% surface cleaning was performed following solvent cleaning. Ti/Al/Ni/Ti/Au ohmic contacts were formed by RF sputtering of Ti/Al/Ni followed by electron beam evaporation of Ti/Au and rapid thermal annealing at 850 C for 30 s. Mesa isolation was performed by inductively coupled plasma reactive ion etching (ICPRIE) of the substrate with BCl 3. Following isolation, a 7 nm tunnel dielectric (either SiO 2 or HfO 2 ) was deposited by atomic layer deposition (ALD). The dielectric is annealed at 600 C for 60 s in N 2 ambient. 7nm TaN floating gates were deposited by RF sputtering. An HfO 2 /Al 2 O 3 /HfO 2 (HAH) or an HfO 2 blocking dielectric was then deposited by atomic layer deposition at 200 C. The TaN floating gate and HAH blocking dielectric are chosen to obtain good charging characteristics and minimal gate leakage [86]. Figure 5.6 illustrates the band diagram for a TaN FG Flash MOS-HFET device with a HAH (solid) or Al 2 O 3 (dot) blocking dielectric. Both dielectrics have the same EOT. Al 2 O 3 has a higher band offset than HfO 2 and could be expected to provide for lower leakage, but the field distribution in the Flash MOS-HFET device under positive gate bias is such that a composite HfO 2 Al 2 O 3 (HAH) dielectric increases the tunneling distance from the floating gate to the conduction band of the dielectric. The field distribution enabled by HAH will reduce gate leakage and increase the length of time charge can be stored on the TaN floating gate.

100 86 Figure 5.7 I D -V D characteristics for Flash MOS-HFET devices before charging 5.4 Flash MOS-HFET Charging and Memory Characteristics Figure 5.7 shows I D -V D characteristics before charging for Flash MOS-HFET devices. Device behavior is identical to standard MOS-HFET operation with a threshold voltage (before charging) of -4.1 for the SiO 2 /TaN/HAH stack or -7.8 for the Figure 5.8 Threshold voltage shift with increasing programming voltage

101 87 Figure 5.9 Nearly parallel shift in transconductance HfO 2 /TaN/HfO 2 stack. Devices are charged by holding source and drain at 0V and applying a gate voltage pulse. Following the gate voltage pulse threshold voltage was measured, being careful not to apply too much gate bias during measurement as to cause more charge to be stored. I D -V G characteristics following increasingly high gate voltage pulses are shown in figure 5.8. For the SiO 2 /TaN/HAH stack with a 7 V gate pulse the threshold voltage shifts Figure 5.10 Shift in CV curves before and after programing

102 88 Figure 5.11 Threshold voltage as a function of charging time from -4.1 V to 0.7 V realizing normally off behavior. Transconductance before and after charging is shown in figure 5.9. Transconductance curves show a nearly parallel shift in the positive direction corresponding to positive V T shift without channel degradation. Figure 5.10 further supports a nearly parallel shift in electrical characteristics with threshold voltage. The CV curve for SiO 2 does stretch slightly after the programming step suggesting that some charge may be stored within the SiO 2 tunnel dielectric itself along with the intended charge storage layer (TaN). The duration of the charging pulse also has an effect on the stored charge and corresponding threshold voltage as seen in figure Longer programming times increase the amount of charge which can tunnel to the floating gate and therefore result in larger V T shifts. Ideally, all charge trapped in the TaN floating gate will remain in place forever resulting in a permanent threshold voltage shift. Practically, with optimized gate stack design, charge can be trapped for time periods of 10 years or greater [87]. The ability of the charge storage layer to keep charge over time is known as retention. To measure retention, the gate is pulsed to charge the device. Threshold voltage is measured with a small gate and

103 89 Figure 5.12 Retention characteristics drain bias such that no charge is able to tunnel to or away from the floating gate. This threshold voltage is measure at logarithmically increasing time increments with the device at rest in between. Retention data can then be extrapolated over time for long term retention estimations. Retention data for both flash gate stacks as well as for a standard SiO 2 gate dielectric (no charge storage layer) MOS-HFET is shown in figure Stacks with either SiO 2 or HfO 2 tunnel dielectrics show a charge loss of less than 20% over a 10,000s time period. The SiO 2 control MOS-HFET shows some initial charging attributed to interface traps as further supported by the stretch out in CV curves seen immediately after charging; threshold voltage returns to its original value after 1,000s as interface traps relax. This illustrates that Flash MOS-HFET devices store charge within the TaN floating gate, rather than unintentionally in the tunnel dielectric, allowing for long retention times. 5.5 Flash MOS-HFET High Power Considerations Under high voltage operating conditions, the high field at the drain side edge of the gate presents a unique challenge for the Flash MOS-HFET device. In traditional power

104 90 Figure 5.13 Increased electric field at the drain side of the gate edge reduces the barrier to tunneling for trapped electrons transistor design the field at the drain side edge of the gate is mitigated using field plates such that the field at this gate edge is sufficiently low to prevent material breakdown in the high field area. While these field plates reduce the field to an acceptable level, the field at the gate edge is still high and has potential to affect the stored charge in a Flash MOS-HFET device. The high field at the gate edge reduces the barrier to electron tunnelling as shown by simulation in figure As electric field rises at the gate edge, the barrier becomes increasingly triangular increasing the probability of charge loss. The reduced barrier to tunnelling will be localized to the small portion of the total gate length which is very near the drain side edge of the gate. This localization of high electric field suggests that the type of charge storage layer may have an effect on the retention characteristics of a Flash MOS- HFET for high voltage applications.

105 Storage Layer Selection for High Voltage Operation Two types or charge storage layers are common for memory applications: dielectric charge traps (CT) and metal or polysilicon floating gate (FG) charge storage. In CT memory, electrons are trapped within a dielectric where they reside in individual, discontinuous locations. The physical location of each trapped electron can be considered essentially fixed within the charge trap layer without the influence of external electric fields. In FG memory, electrons reside in a quantum well between the blocking and tunnelling dielectrics. Within the quantum well the states are essentially continuous and electrons can easily move from one physical location to another along the storage layer, e.g., from the source side of the gate to the drain side. In order to further optimize the Flash MOS-HFET device design the method of charge storage should be explored with emphasis on high voltage effects Experimental Substrates received from Nitronex Corporation consist of a 2 nm GaN capping layer, a 17.5 nm Al 0.26 Ga 0.74 N barrier layer and a 1.8 µm GaN buffer and transition layer grown on Si. HCl:H 2 O 1:1 and HF 1% surface cleaning was performed following solvent cleaning. Ti/Al/Ni/Ti/Au ohmic contacts were formed by RF sputtering of Ti/Al/Ni followed by electron beam evaporation of Ti/Au and rapid thermal annealing at 850 C for 30 s. Mesa isolation was performed by inductively coupled plasma reactive ion etching (ICPRIE) of the substrate with BCl 3. Following isolation, a 9 nm SiO 2 tunnel dielectric was deposited by atomic layer deposition (ALD) at 150 C with 3-Aminopropyltriethoxysilane, water and

106 92 Figure 5.14 Basic device characteristics. After charging there is a linear shift in I D V D curves resulting in enhancement mode operation. I D V G measurements performed at 10 V drain bias ozone precursors. SiO 2 is annealed at 600 C for 60 s in N 2 ambient. For floating gate charge storage samples, 7 nm TaN floating gates were deposited by RF sputtering. Floating gates have a gate length of 3 µm. An HfO 2 3nm/Al 2 O 3 9nm/HfO 2 6nm blocking dielectric was then deposited by atomic layer deposition at 200 C. For charge trap samples, the 3 nm HfO 2 layer serves as the dielectric charge storage layer. TaN gates were then deposited by RF sputtering. All devices have a gate length of 7 µm Results Transistor I D -V G and I D -V D characteristics are shown in figure After charging by holding the gate voltage a 12 V for 300 ms, threshold voltage is shifted by more than 6 V

107 93 Figure 5.15 Gate leakage before and after programming is constant for floating gate and charge trap devices for both CT and FG samples. In both cases enhancement mode operation is realized after charging. Gate leakage before and after charging is seen in figure There is negligible change in gate leakage before and after pulsing at 12 V. Three terminal, off-state breakdown measurements were taken after charging. Breakdown was measured at drain current of 0.1 ma/mm with the device completely pinched off at a gate bias of 0 V. Devices were submerged in Fluorinert solution to prevent flashover. CT and FG devices have a breakdown voltage of 600 V for a gate to drain spacing of 20 µm. A maximum breakdown voltage of 750 V for FG devices and 700 V for CT devices is observed for a gate to drain spacing of 28 µm. Threshold voltage as a function of charging voltage is shown in figure The charging voltage is applied for 100 ms at each voltage step, after which threshold voltage is measured at a voltage range below the pulsing voltage so as not to cause charging during

108 94 Figure 5.16 Threshold voltage shift with increasing charging voltage measurement. Following measurement, the next charging voltage is applied to the same device such that threshold voltage shift is cumulative of the current charging voltage and previously applied voltages. For both devices, charging characteristics are similar with substantial charging after 4V and both devices obtaining positive threshold voltage after applying 5V. At higher voltages, the threshold voltage saturates due to saturation of the charge storage layers. Figure 5.17 shows threshold voltage as a function of charging time. A separate device is tested for each voltage step, however each charging time step is applied to the same device for a cumulative threshold voltage shift. The tunnel dielectric and blocking dielectric thickness for CT and FG samples is the same and as expected charging time and voltage

109 95 Figure 5.17 Threshold voltage shift with increasing charging time. Saturation of threshold voltage is seen for longer charging times dependencies are similar. Threshold voltage begins to saturate for pulse times greater than 100 ms, again suggesting saturation of the charge storage layer. Threshold voltage as a function of elapsed time following charging is shown in figure In this measurement of the storage layer s electron retention, a charging voltage of 12V is applied for 300 ms and threshold voltage is measured over time. CT devices show the least reduction in threshold voltage over time with less than 10 % of threshold shift lost after 10 4 s. Both CT and FG devices retain enhancement mode operation for the duration of the 4x10 4 s test period. FG devices have a photolithography defined floating gate edge and are subject to RF sputtering and lift off processing. Dielectric damage resulting from sputtering combined with edge roughness may reduce the retention capability of FG devices relative to CT devices.

110 96 Figure 5.18 Threshold voltage as a function of elapsed time from charging At high drain bias, the electric field at the drain-side gate edge is large. In the Flash MOS-HFET case, high electric field at the gate edge, even when reduced by field plates, reduces the potential barrier to electrons enabling tunnelling away from the charge storage layer. This barrier reduction can result in charge loss corresponding to negative threshold shift. Figure 5.19 shows the change in threshold voltage as a function of applied drain stress for CT and FG samples with gate to drain spacing of 8 µm. Drain stress is applied for 30 s to the device by biasing the drain while holding the gate below pinch off. Threshold voltage is then measured at V D =25 mv following which higher drain voltage is applied. After stressing, FG devices show more shift in threshold voltage than CT devices. FG devices can lose more charge due to this drain stress because charge is stored in a continuous metal layer. While the electric field is localized to the gate edge, the continuum of states allows charge to redistribute to the gate edge after electrons are lost due to the high field. As a result, localized

111 97 Figure 5.19 Threshold voltage shift after drain stressing for 30 s at stress voltage. Gate is held below pinch-off during stressing high electric field has a global effect on the charge storage layer and thus threshold voltage is decreased. In the CT device, charge storage is facilitated by discrete dielectric traps. At the gate edge, charge may be lost from the storage layer; however, unlike the FG case, charge will not redistribute to the gate edge. The charge stored by traps near the drain-side gate edge represents a small portion of the total storage layer such that a localized high electric field will not have a substantial global effect on threshold voltage Temperature Dependence of Retention For a device operating at high power, the effect of temperature on retention must be considered. Increasing the temperature of the device will give more energy to the electrons trapped in the charge storage layer potentially giving them enough energy to be move out of the storage layer. Figure 5.20 shows the temperature dependence of retention in a Flash

112 98 Figure Retention measurements at increased temperature for a CT sample with a 9 nm SiO 2 tunnel dielectric and an HfO 2 3nm/Al 2 O 3 9nm/ HfO 2 6nm blocking oxide. Increasing temperature reduces retention characteristics MOS-HFET with a CT storage layer. As temperature is increased the retention of the device decreases. Samples at 125 C charged to an initial threshold voltage of 1.1 V lose enough charge to become depletion mode after 5000s. While the retention of these devices is not ideal, there are several design and operational strategies that can be employed to improve retention as will be discussed in section High Power Conclusions In terms of high current operation, operating temperature is a concern for the retention of the Flash MOS-HFET with increased temperature decreasing the retention of the device. Considering high voltage operation, threshold voltage is more stable over time and at high drain bias for charge trap storage than for floating gate charge storage. For an optimal

113 99 Figure 5.21 Retention is improved by increasing the thickness of the tunnel and blocking dielectrics as well as by increasing the thickness of the Al 2 O 3 portion of the blocking dielectric power device design CT type storage layers can better handle the high voltage at the gate edge inherent in power devices. 5.6 Retention Improvement of the Flash MOS-HFET The Flash MOS-HFET is dependent on the charge written to the storage layer to maintain enhancement mode operation. If charge is lost over time the device will have to be written again to maintain the desired normally off operation. In an ideal case the Flash MOS- HFET could be written a single time and would never be required to be written again for the lifetime of the device. Retention times of greater than years are commonly achieved for highly scaled Si devices [87] and it is thus reasonable to expect that with further development the Flash MOS-HFET on GaN could have comparable retention times.

114 100 Toward achieving this goal, several gate stack parameters can be changed to improve the charge retention of the device. The most direct way to increase retention of the device is to increase the thickness of the blocking dielectric and the tunnel dielectric. Thicker dielectrics will provide a stronger barrier to charge loss and improve retention. Changing the gate stack material will also affect the retention of the device. Improving material quality or improving the field distribution across the gate stack can result in better retention characteristics. Figure 5.21 shows the retention characteristics for Flash MOS-HFETs with different gate stacks. Threshold voltage is decreased the most over time for the case of the thinnest blocking and tunnel dielectrics. In this case the tunnel dielectric is 7 nm of SiO 2 and the blocking dielectric is composed of HfO 2 6 nm/ Al 2 O 3 6 nm/ HfO 2 6 nm. Increasing the tunnel dielectric thickness from 7 nm to 9nm and increasing the thickness of large band gap Al 2 O 3 (E G =6.7 ev) increases threshold stability over time. Further improvement is seen by increasing the tunnel dielectric thickness from 7 nm to 14 nm and increasing the blocking dielectric thickness to 6nm HfO 2 /18 nm Al2O3/6nm HfO 2. In the case of the thickest blocking and tunnel dielectric only 2 % of charge is lost over 2x10 5 s. While all of the reported devices see some charge loss over time, it is not necessary to provide only a single charging pulse to maintain threshold voltage indefinitely. During operation of the Flash MOS-HFET, the device could be reprogrammed when the device threshold voltage falls below a certain level. In the case of the thickest gate stack seen in figure 5.21 the device could be recharged once every two days and would maintain a change in charge concentration of only 2%. By appropriately recharging the Flash MOS-HFET or

115 101 with further development of the Flash MOS-HFET gate stack, enhancement mode GaN power devices with high performance can be realized.

116 102 6 CIRCUIT CONTROL OF THE FLASH MOS-HFET 6.1 Introduction to Chapter The Flash MOS-HFET approach has been demonstrated to achieve high V T enhancement mode operation for GaN MOS-HFET devices without degradation of device performance (g m, mobility, etc.)[88].while this approach is promising for normally-off GaN devices, there is a key challenge with this device design. If significant charge is lost from the charge storage layer, the threshold voltage will shift in the negative direction. If too much charge is lost over time, the device will be rendered depletion mode requiring another gate pulse to recharge the charge storage layer. This loss of charge over time has been reported under static conditions (V G =0, V D =0, V S =0) in chapter 5 and is accelerated at increased operation temperature. Several design changes can be considered to reduce or eliminate charge loss over time including increasing the thickness of the gate stack or optimization of dielectric thicknesses and annealing temperature. While these methods provide paths to improvement of charge retention for Flash MOS-HFET devices, it is important to consider the application of this novel device when considering threshold voltage stability. Flash MOS- HFET devices will be employed as a switching device in power electronic circuits with a gate driver continuously applying pulses to control current flow. In the simplest case of a boost converter, the power transistor gate would be controlled by a driver supplying a square wave at around 1 MHz and an amplitude of 1V -10 V depending on the threshold voltage [7], [8]. Previous Flash MOS-HFET reports of charge loss under static conditions do not consider the effect of the gate driver pulse on charge retention. This gate driver pulse has potential to

117 103 contribute small portions of charge to the charge storage layer during device operation under certain conditions. With proper gate driver operation, charge loss from the storage layer can be balanced by charging during the operation of the device. This chapter will characterize the Flash MOS-HFET under several gate driver conditions and demonstrate increased threshold voltage and drain current stability relative to previously reported static testing conditions. 6.2 Flash MOS-HFET Retention Conditions Retention measurements will be reported in two conditions. In the static condition the device is charged by an initial gate pulse and then the source, gate and drain are held at 0 bias. Periodically, the threshold voltage of the device will be measured by performing a quick I D -V D measurement. The voltage extents of this measurement are considered such that no charging of the storage layer occurs during measurement. All retention measurements presented in chapter 5 are in the static condition. In the active condition, the device will be charged by an initial gate pulse (the same pulse as the static condition) and then the source and drain will be held at 0 bias while the gate receives a pulse stream similar to what it would see in a power device circuit. Drain current will be monitored during this time by sampling the drain current at V D =2 V every 10s during the active condition. Again I D -V D measurements will be performed periodically to measure threshold voltage.

118 104 Figure 6.1 Change in threshold voltage for the active and passive conditions. In the passive condition 1V of threshold voltage is lost after approximately 2.5 hrs. In the active case, threshold voltage does not decrease with stable threshold voltage for the duration of the measurement. Figure 6.1 shows retention characteristics for a device under active and passive conditions. In the active condition a 1 MHz 50 % duty cycle, 7.5V peak to peak gate pulse is used. Threshold voltage characteristics as a function of time are markedly changed in the active condition relative to the passive condition. In the passive condition as previously reported in chapter five, the threshold voltage decreases with time resulting in a threshold voltage reduction of 1 V in 2.5 hrs. In the active condition, there is no threshold voltage reduction for the duration of the measurement. This threshold voltage stability achieved for the Flash MOS-HFET in active conditions suggests that the device may be used in circuits requiring enhancement mode operation without requiring the device to be recharged during operation. The Flash MOS- HFET could thus be charged once and then applied to a power converter circuit as a

119 105 traditional enhancement mode device without requiring gate driver changes. Simply applying the Flash MOS-HFET device to a circuit with a gate driver, results in threshold voltage stability. In this situation the circuit external to the Flash MOS-HFET is providing some feedback which regulates the threshold voltage and results in long-term stability. 6.3 Flash MOS-HFET Stability by Field Driven Feedback The threshold voltage stability observed for the Flash MOS-HFET in the active case results from two concurrent conditions: (1) charge is lost from the storage layer by leakage and (2) operating voltage is applied to the gate. The progression of events which results in threshold voltage stability is illustrated in figure 6.2. Figure 6.2 (a) shows the Flash MOS- Figure 6.2 Simulated band diagram for the Flash MOS-HFET gate stack with decreasing levels of stored charge with positive 15V V G applied. As the charge concentration is decreased, the effective field across the tunnel dielectric increases eventually allowing for charge to tunnel to the charge storage layer resulting in a charge increase. This charge increase then lowers the field across the tunnel oxide

120 106 HFET gate stack band diagram of a charged device with an operation gate bias applied (15 V for the purpose of this simulation). In this situation, electrons are prevented from moving to the charge storage layer from the AlGaN layer by the tunnel oxide. In figure 6.2 (b) some charge has been lost from the storage layer resulting in an increase in the field across the tunnel dielectric. While the field across the tunnel dielectric has increased, it is not sufficient to allow for additional charge to tunnel to the charge storage layer. Figure 6.2(c) shows the band diagram with even more charge loss from the charge storage layer. In this case the tunnel oxide field becomes large enough that some of the charge at the AlGaN/dielectric interface will be able to tunnel to the charge storage layer via Fowler Nordheim tunneling. When this charge is trapped in the storage layer, the tunnel oxide field correspondingly decreases resulting in the band diagram seen in figure 6.2 (a). In this way the electric field across the tunnel oxide seen during normal operation of the Flash MOS-HFET device provides a feedback mechanism which stabilizes the threshold voltage of the device. This stability by field driven feedback (SFDF) enables the Flash MOS-HFET to tolerate some charge loss from the storage layer by balancing the loss with addition of new charge facilitated by the gate bias. Furthermore SFDF enables the Flash MOS-HFET to be treated as an enhancement mode device without the limitations observed by passive retention characteristics.

121 107 Figure 6.3 Threshold voltage stability for increasing overdrive voltage (V OD =V G -V T ). The minimum overdrive voltage for threshold voltage stability is 7.5V. SFDF inherently is dependent on the field seen by the Flash MOS-HFET gate stack. It can therefore be expected that for a given charge concentration, corresponding to the desired device threshold voltage, there will be a minimum field required to be supplied by the operating pulse to obtain stability with minimal charge loss before the feedback mechanism starts. Active retention as a function of overdrive voltage V OD =V G -V T is seen in figure 6.3. For overdrive voltage less than 7.5V threshold voltage decreases with time. When an overdrive voltage of 7.5 V is applied, stability is achieved. Stability is taken as minimal reduction in threshold voltage for the duration of the measurement. For cases of lower V OD, stability can be achieved on a longer time frame as more charge leaks from the floating gate progressively increasing the field until FN tunneling is possible. The effective field seen by the gate stack is roughly (V G -V T )/EOT. In the case of V OD of 7.5 V an effective field of 3 MV/cm is applied to the gate stack. This field is the minimum electric field required to obtain SFDF within a reasonable time frame for this gate stack. The minimum gate driver voltage

122 108 Figure 6.4 Circuit model of constructed boost converter circuit with component values matching those of the actual converter for a Flash MOS-HFET with SFDF is thus selected by taking the desired V T written to the device plus 7.5 V for a resulting effective field of 3 MV/cm. 6.4 Boost Converter Circuit with E-mode Flash MOS-HFET Retention measurements in the active condition simulate the operating conditions of the Flash MOS-HFET for a power switching application. To further demonstrate the SFDF concept a boost converter circuit was designed for operation with Flash MOS-HFET devices. Figure 6.4 displays the circuit schematic for the boost converter circuit. The circuit is a 7.5 V to 14 V, 1 MHz boost converter which allows for on-chip probing of Flash MOS-HFET devices. The circuit is designed to allow a Flash MOS-HFET to be automatically placed in and removed from the boost converter for operating and testing purposes respectively. The simulated output of this circuit is observed in figure 6.5. This circuit allows for low power, flexible testing of the Flash MOS-HFET but has limited efficiency because of its operating parameters and the external connections necessary for automated on-chip testing. During

123 109 Figure 6.5 Simulated output voltage for constructed boost converter with an input voltage of 7.5 V operation of the boost converter the Flash MOS-HFET will periodically be removed from the boost circuit in order to measure threshold voltage of the device. This allows threshold voltage as well as output characteristics to be monitored as a function of time. The measured boost converter output with a Flash MOS-HFET device is shown in figure 6.6. The Flash MOS-HFET was charged with a single 100 ms voltage pulse of 21 V above V T to set the threshold voltage of 5.1 V. The bias applied to the device is 14.1 V yielding V OD =9V. The output voltage for this converter remains stable over the 2.5 day measurement time period as seen in figure 6.6. Output voltage has a maximum variation of 250 mv during this time frame which is significantly less than the designed output ripple of the converter of 700 mv (1.4V peak-to-peak). Efficiency also remains constant for the

124 110 Figure 6.6 Boost converter input and output as a function of time. The boost converter output is stable for the duration of the measurement (2 days). At an elevated temperature of 85 C, the output continues to remain stable. Additionally, efficiency P IN /P OUT has negligible variation duration of the measurement. Increasing the operational temperature to 85 C has negligible impact on the output stability. Threshold voltage for the Flash MOS-HFET device during operation of the boost converter circuit is shown in figure 6.7. Threshold voltage remains constant for the duration of the more than 2 day measurement. At elevated temperatures 85 C and 125 C threshold voltage also remains stable for the duration of the measurement. Elevated temperature measurements starkly contrast the retention seen under passive conditions where at 125 C threshold voltage shifted -1.1V in 5000s. SFDF thus enables high temperature operation of the Flash MOS-HFET. By extrapolating from this measurement, it can be expected that a Flash MOS-HFET will maintain a constant, enhancement mode threshold voltage for the lifetime of the circuit even at elevated temperature.

125 111 Figure 6.7 Threshold voltage remains stable for the duration of the measurement in the boost converter circuit even at elevated temperature 6.5 Alternative Charging Methods In the cases described previously, the charge storage layer of the Flash MOS-HFET is written by applying a single pulse of a given time and voltage. This standard method of charging the Flash MOS-HFET device will result in a controllable threshold voltage shift, but is not the only method of charging the device. The Flash MOS-HFET may also be charged by applying the desired gate driver pulse at a given voltage and frequency or by modifying the frequency of the gate bias with a fixed voltage. These additional charging methods allow for increased application flexibility with the Flash MOS-HFET

126 112 Figure 6.8 An uncharged Flash MOS-HFET can be charged by applying gate bias at the operating voltage and frequency Fixed Frequency and Voltage Charging In a situation in which only one frequency and voltage can be applied by a gate driver, the Flash MOS-HFET can be charged. Figure 6.8 shows the Flash MOS-HFET in this charging condition. Source and drain are held at zero bias while a pulse stream of fixed voltage (8V) and frequency (1MHz) is applied to the gate of the device. Threshold voltage as a function of time with this applied gate pulse is shown in the plot of figure 6.8. Over time, the Flash MOS-HFET which was originally depletion mode with a V T of -4.7V is slowly charged. After 2000s the device becomes enhancement mode with threshold voltage saturating for longer times. Charging is relatively slow for this method requiring a start-up time for enhancement mode operation of more than 30 minutes. This method enables charging in the most rigid condition of fixed V G and f.

127 113 Figure 6.9 Charging is accomplished by first applying a low frequency pulse (1-100Hz) followed by the operating pulse (1MHz for the data presented) Fixed Voltage Variable Frequency Charging If the gate driver conditions in figure 6.8 are slightly loosened such that only the gate driver voltage remains fixed, the Flash MOS-HFET may be charged quickly by variation in the frequency of the gate pulse. Figure 6.9 demonstrates charging by this method. In this case a pulse stream which initially is low frequency is applied to the device followed by the operating frequency of the gate driver. In the displayed plot of figure 6.9, 10 Hz is applied for a total time of two seconds followed by a continuous pulse at 1MHz. As seen in the plot of figure 6.9, threshold voltage is set during the low frequency portion of the pulse stream and stability is achieved by the operational pulse of the device. This charging method allows for quick start up of an enhancement mode circuit with a fixed gate bias. 6.6 Flash MOS-HFET SFDF Conclusions In previous consideration of the Flash MOS-HFET device [88]-[90], charge loss during passive retention has been a limiting concern for applying the Flash MOS-HFET in

128 114 power circuits. These reports cite optimization of the gate stack and storage layer as well as material improvement as possible routes to achieving permanent charge storage in the passive mode. By subjecting the Flash MOS-HFET to active conditions threshold voltage stability extrapolated for the lifetime of the device has been demonstrated in an actual power device circuit. This demonstration supports the viability of the Flash MOS-HFET for power circuit operation with high V T and performance. Furthermore, SFDF allows for a Flash MOS-HFET circuit to be operational even with a non-optimal gate stack. In an ideal case, the gate stack would be developed such that no charge is lost even in the passive state, but as a transitional stage to support gate stack development, the Flash MOS-HFET can operate in a stable power circuit even with a non-optimal gate stack.

129 115 Figure 7.1 SEM image of fabricated MOS-HFET. Gate length is 150 nm. Gate to drain spacing is 820 nm and gate to source spacing is 750 nm. 7 SCALING AND SCALABILITY FOR POWER MOS-HFETS 7.1 MOS-HFET Scaling by Electron Beam Lithography Reducing the total area by minimizing unused active area in a GaN MOS-HFET will reduce on-resistance. All MOS-HFET and Flash MOS-HFET devices described in earlier chapters of this work were fabricated using contact lithography with a practical minimum feature size of 3 μm and an alignment tolerance of 1.5μ. The resulting MOS-HFETs were thus subjected to unutilized active area because of this feature size and tolerance. To improve device on resistance, electron beam lithography was utilized to fabricate MOS-HFETs with reduced gate to source spacing and with reduced gate length down to 150 nm.

130 Electron Beam Lithography Experimental Azzuro GaN-on-Si substrates were utilized for MOS-HFET fabrication. Contact formation and device isolation was performed as previously described in chapter 4. Following gate dielectric deposition, electron beam lithography is used to pattern gate Figure 7.2 I D -V G characteristics for a 150 nm L G MOS-HFET and HFET. The MOS-HFET device has an I ON /I OFF ratio improved by 3 orders of magnitude relative to the HFET case Figure 7.3 I D -V D characteristics for MOS-HFET and HFET devices with a gate length of 150 nm. The MOS-HFET device shows a substantially higher maximum drain current of 1103 ma/mm. Max I D is measured at a gate voltage of 5V and drain bias of 10 V.

131 117 features. PMGI SF 9 resist was first spun on and baked followed by PMMA 950 C2. Gate electrodes were patterned in an Elionix ELS-7500 EX electron beam lithography system with a beam current of 200 na. TaN/W gate metal was deposited by RF sputtering and subsequently lifted off. PMGI SF 9 aids the lift-off by increasing resist thickness and improving the resist profile Low Voltage Devices Devices designed for high current density but low breakdown with a gate to drain spacing of 820 nm, a source to gate spacing of 750 nm, and a gate length of 150 nm are seen in figure 7.1. Devices were fabricated with a 7 nm SiO 2 gate dielectric and compared with an HFET device. I D V G characteristics for these devices are seen in figure 7.2. The MOS-HFET device has a good I ON /I OFF ratio of 8 orders of magnitude as compared with the HFET case having I ON /I OFF of Figure 7.3 displays the I D -V D characteristics for both devices. The MOS-HFET shows a maximum current of 1103 ma/mm. The HFET device shows substantially lower drain current with a maximum of 500 ma/mm. The reduced gate leakage provided by the MOS-HFET allows for the device to have a larger range of V G, enabling the higher performance. MOS-HFET devices have an on-resistance of.082 mω-cm 2 enabled by the electron beam lithography process, but are not suitable for high voltage operation because L GD is too short.

132 118 Figure 7.4 SEM image of a 1A MOS-HFET device High Voltage MOS-HFET Devices by Electron Beam Lithography MOS-HFET devices with longer L GD were also fabricated to enable higher breakdown voltage. Figure 7.4 shows a MOS-HFET device with a gate to drain spacing of 14 μm, a gate length of 500 nm and a source to gate spacing of 500nm. The maximum current for this device is 1 A with electron beam lithography facilitating a total active area reduction of 25% over the contact lithography case. While this device does achieve 1A operation, thicker source and drain metallization are needed to reduce on-resistance to an acceptable level. On-resistance for test devices as a function of gate to drain spacing is seen in figure 7.5 for a gate length of 350 nm. As expected, reducing L GD reduces the on-resistance of the device. Electron beam lithography can provide for ultra-low feature sizes but its application is limited by device considerations which will be discussed in the next section.