ECE 465, Fall 2013 Homework 3

Transcription

1 ECE 465, Fall 2013 Homework 3 1) Prob. 5.2(b) (PLA design) from the text. For this PLA design, you need design a primarily hardwarecost minimal design using the multi-function QM method using a PI cost of 1 to share as many product terms as possible between the three functions, thereby minimizing the cost (number of AND lines) of the implementation. Use only Rule 7 here, but without the sweep-up phase. 50 Solution: 5.2(b)

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5 Prob. 2 ECE 465, HW 3, F 13, S. Dutt f1 f2 Cost PIs Flag PI1 1 X X X X 2.2 PI2 2 X X X X 2.2 PI3 1 X X X X 2.2 PI4 1,2 X X X X 2.2 PI5 1,2 X X X X 2.2 PI6 1,3 X X X X 2.2 PI7 1 X X 2.2 PI8 2,3 X X X X 2.2 PI9 1,3 X X X X 2.2 PI10 1,3 X X X X 2.2 PI11 1,2 X X 2.2 PI12 1,2,3 X X X

6 Prob. 2 (contd.) C C f1 f2 C Cost PIs Flag Repr *1.2 PI1 1 A B X X X X 2.2+2*1.2 PI2 2 B C X X X X *1.2 PI3 1 B D X X X X *1.2 PI4 1,2 A B C X X X X *1.2 PI5 1,2 B C D X X X X A,B,C PI6 1,3 A B C X X X X 2.2+2*1.2 PI7 1 A CD X X PI8 2,3 AB C X X X X A,A,C,C 1 B *1.2 PI9 1,3 B CD X X X X 1 2 f2 A,B,D 1 A,B,C *1.2 PI10 1,3 AB D X X X X PI11 1,2 A BCD X X *1.2 PI12 1,2,3 AB C D X X X 6(CC) 5(CC) 3 3 4(CC) The good coverings shown above are applied even though the the covering PI does not have delay cost <= w*kmax (kmax = 2 at this stage), since the covered PI has the same delay cost.

7 f1 A,B,D 1 A,D,C 2 B ->3 f1,f2 Prob. 2 (contd.) f1 f2 Cost PIs Flag Repr *1.2 PI1 1 A B X X X 2.2+5*1.2 PI2 2 B C X X *1.2 PI3 1 B D X X X *1.2 PI4 1,2 A B C X X PI6 1,3 A B C X X A,B,C 1 f *1.2 PI7 1 A CD X X PI8 2,3 AB C X A,A,C,C 1 B 2 f *1.2 PI9 1,3 B CD X X X *1.2 PI10 1,3 AB D X X X PI11 1,2 A BCD X A,B,D 1 A,B,C 2 f1 A,B 1 D, D 2 A, B, C 3 B 1 A, D 2 A, C, D 3 B f1, f2 C, B 1 A, D 2 C, D 3 A 4 B f2 C, B 1 A, D 2 C, D 3 A 4 B 5 (no change as PI8 had been selected earlier for ) f2 6 3 All covers (e.g., PI1 C PI6) are bad coverings (bc s). No PI has delay cost <= w*kmax (kmax =2) There are 4 PIs (PI1, PI3, PI9, PI10) covering the max # 3 of MTs, all of the same delay cost of w*(kmax + 1). We break the tie by choosing PI3 as it has the fewest literal (1) driving kmax = 2 AND lines After this (see 1 #ed deletions), kmax=3, andthere are no good coverings. However, there are bc s (PI7 C PI11, PI 7 C PI6) in which the covering PI PI7 has delay cost <= w*kmax. So we apply these coverings. This results in a sequence of equal delay-cost coverings (as in the PIT in the prev. slide), and a pseudo-epi till # 8 inclusion deletion of PI4. kamx at this point = 5. After this we are left w/ PI2 and PI8 (this was selected earlier for, as indicated), and thus has a delay cost frozen at 1.2 and 0 h/w cost. It good covers PI2 and satisfies delay cost being < w*kmax. So PI8 is inclusion deleted and PI2 is excl. deleted. Final Solution: f1 = PI3 + PI4 + PI7 = B D + A B C + A CD f2 = PI4 + PI8 + PI11 = A B C + AB C + A BCD = PI6 + PI8 + PI10 = A B C + AB C + AB D AND line cost = 7 kmax = 5 (B drives 5 AND lines)

8 Solution: Note: The solution is shown for n=8, instead of n=16, to keep the final detailed schematic contained on a single page without being illegible. The design principle is given, and using it, the design is easily extended to higher values of n. One level of the D&C breakup of the (n, k) shifter problem An (n,k) shifter shifts n bits (of some input X) by the shift value m encoded in k bits lsb-half(k): the LS k/2 bits of m msb-half(k): the MS k/2 bits of m An (n, 2 i (k)) shifter shifts n bits (of some input X) by the shift value 2 i m, where m is encoded in k bits

9 A leaf component of the D&C tree: A (n, (2(1)) shifter High level schematic of a (n, 3) shifter resulting from the D&C breakup

10 4) Extra problem for study (not in the actual HW) (a) Design a 3-bit ripple-carry adder using an appropriate PLA with feedback (using a schematic of the type shown in Fig. 5.14). Specify the PLA size in terms of inputs, total outputs, outputs that feedback to the AND-plane of the PLA, and product lines needed for the design. Obtain the design without using multi-function QM. 50 (b) Give clearly stated rationale on whether it is bene_cial or not to use multi-function QM for this particular design (Hint: Think of how much product term sharing is possible). 30 Solution:

11 (b) By inspecting the expressions of each S i and C i, it is clear that there are no common MTs between S i and C j, when i j. Further inspecting the PIs of each S i, C i, we see that there are common MTs only between the PI A i B i C i-1 of S i and each of the 3 PIs of C i (the other PIs of S i have a complement in at least one of the variables present in each PI of C i, and hence there cannot be an intersection between the MT sets of these PIs of S i and the PIs of C i ). However, to share implicants between these PIs of S i and C i, algebraically speaking, we need to decompose each PI of C i into two, one of each will be A i B i C i-1. For example, the PI A i B i of C i will need to be decomposed into its two implicants as follows: A i B i = A i B i (C i-1 + C i-1 ) = A i B i C i-1 + A i B i C i-1. Of these 2 implicants, A i B i C i-1 can be shared with the PI A i B i C i-1 of S i. However, the 2 nd implicant from the above decomposition, A i B i C i-1 has no common MT with any PI of S i (again, due to a similar reason as explained earlier for the lack of common MTs between the first 3 PIs of S i and all the PIs of C i ; the similar reason now applies to the remaining decomposed implicant A i B i C i-1 and all PIs of S i ). Thus A i B i C i-1 has to be a non-shared implicant of C i. Thus from one nonshared PI A i B i, we can obtain two constituent implicants, one of which can be shared with a PI of S i and another which cannot be. So there is no reduction in the total # of PIs by forcing this sharing. The same argument applies to the rest of the PIs of C i. Thus there is no point in applying multi-function QM to this set of functions (it will give the same solution as above, i.e., the one obtained by minimizing each function separately).