EE 435. Lecture 18. Two-Stage Op Amp with LHP Zero Loop Gain - Breaking the Loop
|
|
- Marylou Leonard
- 5 years ago
- Views:
Transcription
1 EE 435 Lecture 8 Two-Stae Op Amp with LHP Zero Loop Gain - Breakin the Loop
2 Review from last lecture Nyquist and Gain-Phase Plots Nyquist and Gain-Phase Plots convey identical information but ain-phase plots often easier to work with Ma ω = Im Ma Phase ω Re ω -+j0 ω = - ω = ω Phase Note: The two plots do not correspond to the same system in this slide
3 Anle in derees Manitude in db Review from last lecture Gain and Phase Marin Examples β T(s) ω 58 s s ω -50 Phase Marin
4 Review from last lecture Relationship between pole Q and phase marin In eneral, the relationship between the phase marin and the pole Q is dependent upon the order of the transfer function and on the location of the zeros In the special case that the open loop amplifier is second-order lowpass, a closed form analytical relationship between pole Q and phase marin exists and this is independent of A 0 and β.. Q cos(φ sin(φ M M ) ) φ M cos 4Q 4 Q The reion of interest is invariable only for < Q < 0.7 larer Q introduces unacceptable rinin and settlin smaller Q slows the amplifier down too much
5 Review from last lecture Phase Marin vs Q Second-order low-pass Amplifier Pole Q Phase Marin
6 Review from last lecture Phase Marin vs Q Second-order low-pass Amplifier Pole Q Phase Marin
7 Review from last lecture Manitude Response of nd -order Lowpass Function Q MAX for no peakin =. 707 Q From Laker-Sansen Text
8 Review from last lecture Step Response of nd -order Lowpass Function Q Q MAX for no overshoot = / From Laker-Sansen Text
9 Review from last lecture ompensation Summary Gain and phase marin performance often stronly dependent upon architecture Relationship between overshoot and rinin and phase marin were developed only for nd -order lowpass ain characteristics and differ dramatically for hiher-order structures Absolute ain and phase marin criteria are not robust to chanes in architecture or order It is often difficult to correctly break the loop to determine the loop ain Aβ with the correct loadin on the loop (will discuss this more later)
10 Desin of Two-Stae Op Amps ompensation is critical in two-stae op amps General approach to desinin two-stae op amps is common even thouh sinificant differences in performance for different architectures Will consider initially the most basic two-stae op amp with internal compensation
11 Natural Parameter Space for the Two-Stae Amplifier Desin DD M 3 M 4 M 5 OUT IN M M IN L I T B M 7 B3 M 6 SS S NATURAL = {W, L, W 3, L 3, W 5, L 5, W 6, L 6, W 7, L 7, I T, I D6, c }
12 Desin Derees of Freedom Total independent variables: 3 Derees of Freedom: 3 If phase marin is considered a constraint 3 independent variables constraint derees of freedom
13 Observation: W,L appear as W/L ratio in almost all characterizin equations Implication: Derees of Freedom are Reduced S NATURAL-REDUED = {(W/L),(W/L) 3,(W/L) 5,(W/L) 6,(W/L) 7,I D6,I T, } With phase marin constraint, Derees of freedom: 7
14 ommon Performance Parameters of Operational Amplifiers Parameter Description Ao Open-loop D Gain GB Gain-Bandwidth Product Φm(or Q) Phase Marin (or pole Q) SR Slew Rate T SETTLE Settlin Time A T Total Area A A Total Active Area P Power Dissipation OS Standard Deviation of Input Referred Offset oltae (often termed the input offset voltae) MRR ommon Mode Rejection Ratio PSRR Power Supply Rejection Ratio imax Maximum ommon Mode Input oltae imin Minimum ommon Mode Output oltae omax Maximum Output oltae Swin omin Minimum Output oltae Swin noise Input Referred RMS Noise oltae Sv Input Referred Noise Spectral Density
15 Performance Parameters Total: 7
16 Performance parameters: 7 Derees of freedom: 7 System is Generally Hihly Over onstrained!
17 Typical Parameter Space for a Two-Stae Amplifier + OUT - d md d Od mo OO L Small sinal model of the two-stae operational amplifier Small sinal desin parameters: S SMALL SIGNAL = { oo, od, mo, md,, o, o4, o5, o6 }
18 Sinal Swin of Two-Stae Op Amp DD M 3 M 4 M 5 OUT IN M M IN L I T B SS M7 B3 M 6 M6: M5: M: i OUT OUT DD SS DD EB6 EB5 T T3 EB3 M: M7: i ic DD T T5 EB5 T EB EB 7 SS S swin/bias Related = {, EBQ, EB3Q, EB5Q, EB6Q, EB7Q, I T }
19 Sinal Swin of Two-Stae Op Amp OUT DD EB5 T EB EB7 max{( ( EB3 EB5 T3 T5 T T ), )} SS DD ic OUT DD EB5 OUT SS EB6 EB6 SS ic T EB EB 7 SS i DD T T3 EB3 i DD T T5 EB5
20 Sinal Swin of Two-Stae Op Amp OUT DD EB5 T EB EB7 max{( ( EB3 EB5 T3 T5 T T ), )} SS DD ic EB6 SS
21 Typical Parameter Space for a Two-Stae Amplifier DD M 3 M 4 M 5 OUT IN M M IN L I T B M7 B3 M 6 SS + OUT - d md d Od mo OO L Aumented set of desin parameters: S AUGMENTED = { oo, od, mo, md,, EBQ, EB3Q, EB5Q, EB6Q, EB7Q, I T, o, o4, o5, o6 } Parameters in this set are hihly inter-related
22 ommon Expressions for the Performance Parameters A O GB SR md oo I md T mo od
23 ommon Expressions for the Performance Parameters (cont) OMAX OMIN DD SS EB5 EB6 inmin T EB EB 7 SS max{( inmax DD EB3 T3 T EB5 T5 T ),( )}
24 Parameter Inter-dependence A O md GB oo mo od md I T affects SR I T W md OX T μ I L
25 A Set of Independent Desin Parameters is Needed onsider the Natural Reduced Parameter Set W W3 W5 W6 W 7,,,,,I T, θ L L3 L L 5 6 L7 A A = O I θ= O D6Q OX I T md oo μμ n p mo od WW LL WL n p IT WL 7 6 λ +λ
26 md GB n p p n L L W β L L L W W W W L L L W W W L Q β n OX T μ W I L GB For a iven pole Q and a feedback factor, it can be shown that:
27 inmin T EB EB7 SS I L I L T T 7 imin T SS μnox W μnox W7 Expressions for sinal swins are particularly complicated!
28 Observation Even the most elementary performance parameters require very complicated expressions when the natural desin parameter space is used Stron simultaneous dependence on multiple natural desin parameters Interdependence and notational complexity obscures insiht into performance and optimization
29 Practical Set of Desin Parameters S PRATIAL = {P, θ, EB, EB3, EB5, EB6, EB7 } 7 derees of freedom! P : total power dissipation q = IDQ5/I T, current split factor EBK=GSQK-TK, excess bias voltae for the k th transistor Phase marin constraint assumed (so not shown in DoF)
30 Basic Two-Stae Op Amp DD M 3 M 4 M 5 OUT IN M M IN L I T B M 7 B3 M 6 SS 7 Derees of Freedom {P, θ, EB, EB3, EB5, EB6, EB7 } W W3 W5 W6 W 7,,,,,I T, θ L L3 L L 5 6 L7
31 Relationship Between the Practical Parameters and the Natural Desin Parameters {P, θ, EB, EB3, EB5, EB6, EB7 } W W3 W5 W6 W 7,,,,,I T, θ L L3 L L 5 6 L7 I T P +θ DD I I I,,θI T DQi T T W I DQi L i μ i OX EBi
32 Relationship Between the Practical Desin Parameters and the Performance Parameters (Assumin Q ) A O 4 λ λ n P Pθ EB β EB5 GB θ 4 θβ θ p EB EB5 DD EB L DD EB EB5 Pθ EB β EB5 SR EBGB 4 L θβ DD θ EB EB5 c 4 θβ L EB EB5 θ β EB EB5
33 Relationship Between the Proposed Desin Parameters and the Performance Parameters OMAX OMIN DD SS EB5 EB6 inmin T EB EB 7 SS max{( inmax DD EB3 T3 T EB5 T5 T ),( )}
34 haracteristics of the Practical Desin Parameter Space Minimum set of independent parameters Results in major simplification of the key performance parameters Provides valuable insiht which makes performance optimization more practical
35 Desin Assumptions Assume the followin system parameters: DD = 3.3 L = pf Typical 0.35um MOS process Simulation corner: typ/55/3.3
36 Example for Desin Procedure Given specifications: A 0 : 66dB GB: 5MHz OMIN = OMAX =3. INMIN =. INMAX =3 P=0.7mw = Assume: TN = 0.6, TP = 0.7, n =0.04, p =0.8 7 constraints (in addition to φ m ) and 7 derees of freedom
37 Example for Desin Procedure. hoose channel lenth. EB3, EB5, EB6 {P, θ, EB, EB3, EB5, EB6, EB7 } 3. EB imax = DD + EB3 + T + T3 omax = DD + EB5 omin = EB6 A = 4. EB7 imin=eb + EB7 + T O 4 λ +λ n p EB EB5 {P, θ, EB, EB3, EB5, EB6, EB7 } {P, θ, EB, EB3, EB5, EB6, EB7 } 5. hoose P to satisfy power constraint {P, q, EB, EB3, EB5, EB6, EB7 } I T P +θ DD
38 Example for Desin Procedure 6. hoose q to meet GB constraint GB 7. ompensation capacitance c DD 4 L q EB EB 5 q EB 8. alculate all transistor sizes I = T P +θ DD EB 5 EB5 q P P q EB q EB 4LqDD EB EB5 Wk L k I μ Dk OXEBk {P, q, EB, EB3, EB5, EB6, EB7 } 9. Implement structure, simulate, and make modifications if necessary uided by where deviations may occur Note: It may be necessary or preferable to make some constraints an inequality Note: Specifications may be over-constrained or have no solution k (Assumin Q )
39 Example for Desin Procedure Desin results: M, W/L M 3,4 W/L M 5 W/L M 6 W/L M 7 W/L P θ 3/ 4.5/ 54/ 7.4/ 7.4/ 0.7mW pF Simulation results: A0 GB P Phase marin 65dB 5.MHz.7mW 45.4 derees
40 Spreadsheet for Desin Space Exploration Settlin haracteristics of Two-Stae Operational Amplifier Process Parameters 0.0 Power 0.0 ln 9E-05 uoxn E- T 0. lp 5E-05 uoxp 4 dd tn tp Dev ice Sizin Output Rane Input Rane Performance haracteristics Desin Parameters W/L5 W/L W/L max min max min ISS(mA) GB Ao EB7 EB6 EB5 EB EB E E E E E E E E E E E E ERR.67 ERR E E E E ERR.67 ERR E E E E E E ERR.67 ERR 39 W/L7 W/L6 W/L Dev ice Sizin W/L7 W/L6 W/L5 W/L
41 Summary. Determination of Desin Space and Derees of Freedom Often Useful for Understandin the Desin Problem. Analytical Expressions for Key Performance Parameters ive onsiderable Insiht Into Desin Potential 3. Natural Desin Parameters Often Not Most Useful for Providin Insiht or Facilitatin Optimization 4. oncepts Readily Extend to other Widely Used Structures
42 Basic Two-Stae Op Amp DD M 3 M 4 M 5 OUT IN M M IN L I T B M 7 B3 M 6 A FB (s) SS s L s md m0 sc mo β md β mdmo Riht Half-Plane Zero Limits Performance Why does the RHP zero limit performance? an anythin be done about this problem?
43 Why does the RHP zero limit performance? Gain Manitude in db β All Pole RHP Zero Phase in Derees 0.00E E E E E E+0 -.0E E E E E+0 RHP Zero All Pole p =, p =000, z x ={none,50} In this example: accumulate phase shift and slow ain drop with RHP zeros effects are dramatic
44 Why does the RHP zero limit performance? Gain Manitude in db β All Pole LHP and RHP Zero Phase in Derees 0.00E E E E E E+0 -.0E E E E E+0 RHP Zero LHP Zero All Pole p =, p =000, z x ={none,50,-50} In this example: accumulate phase shift and slow ain drop with RHP zeros loose phase shift and slow ain drop with RHP zeros effects are dramatic
45 Two-stae amplifier (with RHP Zero ompensation) What causes the Miller compensation capacitor to create a RHP zero? DD M 3 M 4 M 5 s+p s+p A = A p p 0 OUT IN M M IN L with Miller ompensation I T B SS M7 B3 + - d=in-in M 6 A = A 0 pp -s+z z s+p s+p At low frequencies, OUT / d is neative but at hih frequencies it becomes positive Alternately, provides a feed-forward noninvertin sinal from the output of the first stae to the output of the second stae
46 Two-stae amplifier (with RHP Zero ompensation) What can be done to remove the RHP zero? DD M 3 M 4 M 5 s+p s+p A = A p p 0 IN M M IN L OUT with Miller ompensation B I T M7 B3 M 6 A = A 0 pp -s+z z s+p s+p SS + - d=in-in Alternately, provides a feed-forward noninvertin sinal from the output of the first stae to the output of the second stae Break the feed-forward path from the output of the first stae to the output of the second stae at hih frequencies
47 Two-stae amplifier with LHP Zero ompensation DD DD M 3 M 4 M 5 M 3 M 4 M 5 IN M M IN L OUT A B R OUT I T IN M M IN L B M7 B3 M 6 SS B M 7 B M 6 Riht Half-Plane Zero Limits Performance Zero can be moved to Left Half-Plane R realized with sinle triode reion device
48 Two-stae amplifier with LHP Zero ompensation DD IN M 3 M 4 M 5 A B R M M IN OUT L A(s) md s m5 m5 sc c L s m5 oo od B M 7 B M 6 z m5 m5 z location can be prorammed by R If c > m5, z in RHP and if c < m5, z in LHP R has almost no effect on p and p
49 Two-stae amplifier with LHP Zero ompensation o m o o p od oo m L c m c m md s s s A(s) m m z L m p 5 p p X X z where should z be placed?
50 Two-stae amplifier with LHP Zero ompensation where should z be placed? X X p p X X p p X X p p z z z z p Would make situation worse (because m5 m5 o 05 o5 m5 m5 p ratio between two dominant poles would be reduced! L o6 X X z p p X X p z p
51 Two-stae amplifier with LHP Zero ompensation where should z be placed? Would make situation worse (because ratio between two dominant poles would be reduced! X X p p z Other parasitic poles, at hiher frequencies are present and not too much larer than p! X X X X p 4 p 3 p p z
52 Two-stae amplifier with LHP Zero ompensation X X z p p z m5 m5 z often used to cancel p an reduce size of required compensation capacitor a) eliminates RHP zero b) increases spread between p and p 3 Improves phase marin Desin formulations easily extend to this structure
53 Two-stae amplifier with LHP Zero ompensation X p 3 X X p p z z m5 m5 Analytical formulation for compensation requirements not easy to obtain (must consider at least 3 rd order poles and both T(s) and poles not mathematically tractable) often chosen to meet phase marin (or settlin/overshoot) requirements after all other derees of freedom used with computer simulation from manitude and phase plots
54 Basic Two-Stae Op Amp with LHP zero DD M 3 M 4 M 5 A B R OUT IN M M IN L B M 7 B M 6 8 Derees of Freedom with zero cancellation of p {P, θ, EB, EB3, EB5, EB6, EB7,R, } constraint (phase marin) 7 Derees of Freedom {P, θ, EB, EB3, EB5, EB6, EB7,R, } constraints (phase marin), z = p = - m5 m5 -
55 Basic Two-Stae Op Amp with LHP zero DD M 3 M 4 M 5 with zero cancellation of p IN A B M M R IN OUT L 7 Derees of Freedom B M 7 B M 6 {P, θ, EB, EB3, EB5, EB6, EB7,R, } - constraints (phase marin), z m5 = p = m5 - Desin Flow:. Inore R and desin as if RHP zero is present. Pick R to cancel p 3. Adjust p (i.e. chane/reduce ) to achieve desired phase marin
56 Basic Two-Stae Op Amp with LHP zero DD M 3 M 4 M 5 A B R OUT IN M M IN L B M 7 B M 6 XX Realization of R R = μ OX L W EB R OR YY Transistors in triode reion ery little current will flow throuh transistors (and no dc current) DD or GND often used for XX or YY BQ well-established since it determines I Q5 Usin an actual resistor not a ood idea (will not track m5 over process and temp)
57 Two-Stae Amplifiers Practical onsiderations Loop Gain Loadin of A and β networks Breakin the Loop (with appropriate terminations) Biasin of Loop Simulation of Loop Gain Open-loop ain simulations Systematic Offset Embeddin in closed loop
58 End of Lecture 8
EE 435. Lecture 16. Compensation Systematic Two-Stage Op Amp Design
EE 435 Lecture 6 Compensation Systematic Two-Stage Op Amp Design Review from last lecture Review of Basic Concepts Pole Locations and Stability Theorem: A system is stable iff all closed-loop poles lie
More informationEE 435 Lecture 13. Cascaded Amplifiers. -- Two-Stage Op Amp Design
EE 435 Lecture 13 ascaded Amplifiers -- Two-Stae Op Amp Desin Review from Last Time Routh-Hurwitz Stability riteria: A third-order polynomial s 3 +a 2 s 2 +a 1 s+a 0 has all poles in the LHP iff all coefficients
More informationEE 435. Lecture 15. Compensation of Cascaded Amplifier Structures
EE 435 Lecture 15 ompensation of ascaded Amplifier Structures . Review from last lecture. Basic Two-Stae Op Amp V DD M 3 M 4 M 5 V OUT V IN M 1 M V IN L I T V B M 7 V B3 M 6 By inspection A o m1 o p 1
More informationEE 435. Lecture 16. Compensation of Feedback Amplifiers
EE 435 Lecture 16 ompensation of Feedback Amplifiers . Review from last lecture. Basic Two-Stae Miller ompensated Op Amp DD M 3 M 4 M 5 OUT IN M 1 M IN L I T B M 7 B3 M 6 By inspection SS A o m1 o p 1
More informationEE 435. Lecture 10: Current Mirror Op Amps
EE 435 ecture 0: urrent Mirror Op mps Review from last lecture: Folded ascode mplifier DD DD B3 B3 B B3 B2 B2 B3 DD DD B B B4 I T QURTER IRUIT Op mp 2 Review from last lecture: Folded ascode Op mp DD M
More informationEE 435. Lecture 14. Compensation of Cascaded Amplifier Structures
EE 435 Lecture 4 ompensation of ascaded Amplifier Structures . Review from last lecture. Basic Two-Stae Op Amp By inspection A o m o + p o o4 + 05 o5 m5 + o6 o5 m5 + o6 p GB m5 L m . Review from last lecture.
More informationEE 435 Lecture 13. Two-Stage Op Amp Design
EE 435 Lecture 13 Two-Stae Op Amp Desin Review ascades of three or more amplifier staes are seldom used to build a feedback amplifier because of challenes associated with compensatin the amplifier for
More informationV DD. M 1 M 2 V i2. V o2 R 1 R 2 C C
UNVERSTY OF CALFORNA Collee of Enineerin Department of Electrical Enineerin and Computer Sciences E. Alon Homework #3 Solutions EECS 40 P. Nuzzo Use the EECS40 90nm CMOS process in all home works and projects
More informationAnalysis and Design of Analog Integrated Circuits Lecture 7. Differential Amplifiers
Analysis and Desin of Analo Interated Circuits ecture 7 Differential Amplifiers Michael H. Perrott February 1, 01 Copyriht 01 by Michael H. Perrott All rihts reserved. Review Proposed Thevenin CMOS Transistor
More informationECEN 326 Electronic Circuits
ECEN 326 Electronic Circuits Stability Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering Ideal Configuration V i Σ V ε a(s) V o V fb f a(s) = V o V ε (s)
More informationEE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps
EE 435 ecture 2: Basic Op mp Design - Single Stage ow Gain Op mps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op mp mplifier mplifier used in open-loop applications
More informationEE 435. Lecture 2: Basic Op Amp Design. - Single Stage Low Gain Op Amps
EE 435 ecture 2: Basic Op Amp Design - Single Stage ow Gain Op Amps 1 Review from last lecture: How does an amplifier differ from an operational amplifier?? Op Amp Amplifier Amplifier used in open-loop
More informationLectures on STABILITY
University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science νin ( ) Effect of Feedback on Frequency Response a SB Robert W. Brodersen EECS40 Analog
More informationSample-and-Holds David Johns and Ken Martin University of Toronto
Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters
More informationCh 14: Feedback Control systems
Ch 4: Feedback Control systems Part IV A is concerned with sinle loop control The followin topics are covered in chapter 4: The concept of feedback control Block diaram development Classical feedback controllers
More informationEE 505. Lecture 27. ADC Design Pipeline
EE 505 Lecture 7 AD Design Pipeline Review Sampling Noise V n5 R S5 dv REF V n4 R S4 V ns V ns β= + If the ON impedance of the switches is small and it is assumed that = =, it can be shown that Vˆ IN-RMS
More informationLecture 25 ANNOUNCEMENTS. Reminder: Prof. Liu s office hour is cancelled on Tuesday 12/4 OUTLINE. General considerations Benefits of negative feedback
Lecture 25 ANNOUNCEMENTS eminder: Prof. Liu s office hour is cancelled on Tuesday 2/4 Feedback OUTLINE General considerations Benefits of neative feedback Sense andreturn techniques Voltae voltae feedback
More informationPolytech Montpellier MEA M2 EEA Systèmes Microélectroniques. Analog IC Design
ours I - 03/04 - Séane 6 8/03/04 Polyteh Montpellier ME M EE Systèmes Miroéletroniques nalo I Desin hapter VII OP stability and ompensation Pasal Nouet / 03-04 nouet@lirmm.r http://www.lirmm.r/~nouet/homepae/leture_ressoures.html
More informationStability and Frequency Compensation
類比電路設計 (3349) - 2004 Stability and Frequency ompensation hing-yuan Yang National hung-hsing University Department of Electrical Engineering Overview Reading B Razavi hapter 0 Introduction In this lecture,
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First
More informationAdvanced Current Mirrors and Opamps
Advanced Current Mirrors and Opamps David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 26 Wide-Swing Current Mirrors I bias I V I in out out = I in V W L bias ------------
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 Lecture 3 Spring 2016 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationI D based Two-Stage Amplifier Design
m D based Two-Stae Amplifier Desin honli ai 9/0/04 Motivation d/(w/l) VS VG is sensitive to Vbs Motivation m/d vs VG is also sensitive to Vbs Motivation But m/d vs D/(W/L) has fixed shape With a ertain
More informationEE 330. Lecture 35. Parasitic Capacitances in MOS Devices
EE 330 Lecture 35 Parasitic Capacitances in MOS Devices Exam 2 Wed Oct 24 Exam 3 Friday Nov 16 Review from Last Lecture Cascode Configuration Discuss V CC gm1 gm1 I B VCC V OUT g02 g01 A - β β VXX Q 2
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
More informationEE 330 Lecture 33. Basic amplifier architectures Common Emitter/Source Common Collector/Drain Common Base/Gate. Basic Amplifiers
33 Lecture 33 asic aplifier architectures oon itter/source oon ollector/drain oon ase/gate asic plifiers nalysis, Operation, and Desin xa 3 Friday pril 3 eview Previous Lecture Two-Port quivalents of Interconnected
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationOPERATIONAL AMPLIFIER APPLICATIONS
OPERATIONAL AMPLIFIER APPLICATIONS 2.1 The Ideal Op Amp (Chapter 2.1) Amplifier Applications 2.2 The Inverting Configuration (Chapter 2.2) 2.3 The Non-inverting Configuration (Chapter 2.3) 2.4 Difference
More informationECE 546 Lecture 11 MOS Amplifiers
ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase
More informationAdvanced Analog Integrated Circuits. Operational Transconductance Amplifier II Multi-Stage Designs
Advanced Analog Integrated Circuits Operational Transconductance Amplifier II Multi-Stage Designs Bernhard E. Boser University of California, Berkeley boser@eecs.berkeley.edu Copyright 2016 by Bernhard
More informationLECTURE 130 COMPENSATION OF OP AMPS-II (READING: GHLM , AH )
Lecture 30 Compensation of Op AmpsII (/26/04) Page 30 LECTURE 30 COMPENSATION OF OP AMPSII (READING: GHLM 638652, AH 260269) INTRODUCTION The objective of this presentation is to continue the ideas of
More informationRadivoje Đurić, 2015, Analogna Integrisana Kola 1
OVA & OTA 1 OVA VA-Operational Voltage Amplifier Ideally a voltage-controlled voltage source Typically contains an output stage that can drive arbitrary loads, including small resistances Predominantly
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 ecture 3 Spring 2019 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationECEG 351 Electronics II Spring 2017
G 351 lectronics Sprin 2017 Review Topics for xa #1 Please review the xa Policies section of the xas pae at the course web site. Please especially note the followin: 1. You will be allowed to use a non-wireless
More informationBandwidth of op amps. R 1 R 2 1 k! 250 k!
Bandwidth of op amps An experiment - connect a simple non-inverting op amp and measure the frequency response. From the ideal op amp model, we expect the amp to work at any frequency. Is that what happens?
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam
More informationPolytech Montpellier MEA4 M2 EEA Systèmes Microélectroniques. Analog IC Design
Analo C Desin - Academic year 05/06 - Session 3 04/0/5 Polytech Montellier MEA4 M EEA Systèmes Microélectroniques Analo C Desin From transistor in to current sources Pascal Nouet 05/06 - nouet@lirmm.fr
More informationDesign of CMOS Analog Integrated Circuits. Basic Building Block
Desin of CMOS Analo Inteated Cicuits Fanco Malobeti Basic Buildin Block F. Malobeti : Desin of CMOS Analo Inteated Cicuits - Basic Buildin Block INERTER WITH ACTIE LOAD The simplest fom of ain stae, the
More information6.2 INTRODUCTION TO OP AMPS
Introduction to Op Amps (7/17/00) Page 1 6.2 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is: 1.) Characterize the operational amplifier 2.) Illustrate the analysis
More informationEE 434 Lecture 16. Small signal model Small signal applications in amplifier analysis and design
EE 434 Lecture 16 Sall sinal odel Sall sinal applications in aplifier analysis and desin Quiz 13 The of an n-channel OS transistor that has a quiescent current of 5A was easured to be 10A/. If the lenth
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 3: Sample and Hold Circuits Switched Capacitor Circuits Circuits and Systems Sampling Signal Processing Sample and Hold Analogue Circuits Switched Capacitor
More informationLecture 310 Open-Loop Comparators (3/28/10) Page 310-1
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop
More informationEE 508 Lecture 22. Sensitivity Functions - Comparison of Circuits - Predistortion and Calibration
EE 58 Lecture Sensitivity Functions - Comparison of Circuits - Predistortion and Calibration Review from last time Sensitivity Comparisons Consider 5 second-order lowpass filters (all can realize same
More informationCommon Drain Stage (Source Follower) Claudio Talarico, Gonzaga University
Common Drain Stage (Source Follower) Claudio Talarico, Gonzaga University Common Drain Stage v gs v i - v o V DD v bs - v o R S Vv IN i v i G C gd C+C gd gb B&D v s vv OUT o + V S I B R L C L v gs - C
More informationSystematic Design of Operational Amplifiers
Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of
More informationANALYSIS OF POWER EFFICIENCY FOR FOUR-PHASE POSITIVE CHARGE PUMPS
ANALYSS OF POWER EFFCENCY FOR FOUR-PHASE POSTVE CHARGE PUMPS Chien-pin Hsu and Honchin Lin Department of Electrical Enineerin National Chun-Hsin University, Taichun, Taiwan e-mail:hclin@draon.nchu.edu.tw
More informationLecture 6, ATIK. Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters
Lecture 6, ATIK Switched-capacitor circuits 2 S/H, Some nonideal effects Continuous-time filters What did we do last time? Switched capacitor circuits The basics Charge-redistribution analysis Nonidealties
More informationPI3CH400 4-Bit Bus Switch, Enable Low 1.8V/2.5V/3.3V, High-Bandwidth, Hot Plug
1.8V/2.5V/3.3V, Hih-Bandwidth, Hot Plu Features Near-Zero propaation delay 5-ohm switches connect inputs to outputs Hih sinal passin bandwidth (500 MHz) Beyond Rail-to-Rail switchin - 0 to 5V switchin
More information2N5545/46/47/JANTX/JANTXV
N//7/JANTX/JANTXV Monolithic N-Channel JFET Duals Product Summary Part Number V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv) N. to.. N. to.. N7. to.. Features Benefits Applications
More informationInput and Output Impedances with Feedback
EE 3 Lecture Basic Feedback Configurations Generalized Feedback Schemes Integrators Differentiators First-order active filters Second-order active filters Review from Last Time Input and Output Impedances
More informationEE 435. Lecture 23. Common Mode Feedback Data Converters
EE 435 Lecture 3 Common Mode Feedback Data Converters Review from last lecture Offset Voltage Distribution Pdf of zero-mean Gaussian distribution f(x) -kσ kσ x Percent between: ±σ 68.3% ±σ 95.5% ±3σ 99.73%
More informationEE 508 Lecture 29. Integrator Design. Metrics for comparing integrators Current-Mode Integrators
EE 508 Lecture 29 Integrator Design Metrics for comparing integrators urrent-mode Integrators eview from last time nti-aliasing filter often required to limit frequency content at input to S filters ontinuous-time
More informationSWITCHED CAPACITOR AMPLIFIERS
SWITCHED CAPACITOR AMPLIFIERS AO 0V 4. AO 0V 4.2 i Q AO 0V 4.3 Q AO 0V 4.4 Q i AO 0V 4.5 AO 0V 4.6 i Q AO 0V 4.7 Q AO 0V 4.8 i Q AO 0V 4.9 Simple amplifier First approach: A 0 = infinite. C : V C = V s
More informationEE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods
EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1
More informationEE 230 Lecture 25. Waveform Generators. - Sinusoidal Oscillators The Wein-Bridge Structure
EE 230 Lecture 25 Waveform Generators - Sinusoidal Oscillators The Wein-Bridge Structure Quiz 9 The circuit shown has been proposed as a sinusoidal oscillator. Determine the oscillation criteria and the
More informationChapter 10 Feedback. PART C: Stability and Compensation
1 Chapter 10 Feedback PART C: Stability and Compensation Example: Non-inverting Amplifier We are analyzing the two circuits (nmos diff pair or pmos diff pair) to realize this symbol: either of the circuits
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationDifferential Amplifiers (Ch. 10)
Differential Amplifiers (h. 0) 김영석 충북대학교전자정보대학 0.9. Email: kimys@cbu.ac.kr 0- ontents 0. General onsiderations 0. Bipolar Differential Pair 0.3 MOS Differential Pair 0.4 ascode Differential Amplifiers
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationLecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
More informationEE 435. Lecture 22. Offset Voltages
EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output
More informationIntroduction: the common and the differential mode components of two voltages. differential mode component: v d = v 1 - v 2 common mode component:
EECTONCS-1 CHPTE 3 DFFEENT MPFES ntroduction: the common and the differential mode components of two voltaes v d v c differential mode component: v d = v 1 - v common mode component: v1 v v c = v 1 v vd
More informationClosed-loop system 2/1/2016. Generally MIMO case. Two-degrees-of-freedom (2 DOF) control structure. (2 DOF structure) The closed loop equations become
Closed-loop system enerally MIMO case Two-degrees-of-freedom (2 DOF) control structure (2 DOF structure) 2 The closed loop equations become solving for z gives where is the closed loop transfer function
More informationAn Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes
n Improved Loical Effort Model and Framework pplied to Optimal Sizin of Circuits Operatin in Multiple Supply Voltae Reimes Xue Lin, Yanzhi Wan, Shahin Nazarian, Massoud Pedram Department of Electrical
More informationECEN 610 Mixed-Signal Interfaces
ECEN 610 Mixed-Signal Interfaces Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 014 S. Hoyos-ECEN-610 1 Sample-and-Hold Spring 014 S. Hoyos-ECEN-610 ZOH vs. Track-and-Hold V(t)
More informationESE319 Introduction to Microelectronics. Feedback Basics
Feedback Basics Stability Feedback concept Feedback in emitter follower One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability
More informationHomework Assignment 08
Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance
More informationCMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators
IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater
More informationEE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationExample: High-frequency response of a follower
Example: Hih-requency response o a ollower o When body eects are cluded, db actually appears between dra and round. ce both termals o db are rounded, it does not aect the circuit. o d is also between the
More informationLecture 120 Compensation of Op Amps-I (1/30/02) Page ECE Analog Integrated Circuit Design - II P.E. Allen
Lecture 20 Compensation of Op AmpsI (/30/02) Page 20 LECTURE 20 COMPENSATION OF OP AMPS I (READING: GHLM 425434 and 624638, AH 249260) INTRODUCTION The objective of this presentation is to present the
More informationAn Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor. ΔΣ Modulator. Electronic Design Automation Laboratory
Electronic Design Automation Laboratory National Central University Department of Electrical Engineering, Taiwan ( R.O.C) An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor
More informationCHAPTER 6 CMOS OPERATIONAL AMPLIFIERS
Chapter 6 Introduction (6/24/06) Page 6.0 CHAPTER 6 CMOS OPERATIONAL AMPLIFIERS INTRODUCTION Chapter Outline 6. CMOS Op Amps 6.2 Compensation of Op Amps 6.3 TwoStage Operational Amplifier Design 6.4 Cascode
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More information388 Facta Universitatis ser.: Elec. and Energ. vol. 14, No. 3, Dec A 0. The input-referred op. amp. offset voltage V os introduces an output off
FACTA UNIVERSITATIS (NI»S) Series: Electronics and Energetics vol. 14, No. 3, December 2001, 387-397 A COMPARATIVE STUDY OF TWO SECOND-ORDER SWITCHED-CAPACITOR BALANCED ALL-PASS NETWORKS WITH DIFFERENT
More informationESE319 Introduction to Microelectronics. Feedback Basics
Feedback Basics Feedback concept Feedback in emitter follower Stability One-pole feedback and root locus Frequency dependent feedback and root locus Gain and phase margins Conditions for closed loop stability
More informationLinearized optimal power flow
Linearized optimal power flow. Some introductory comments The advantae of the economic dispatch formulation to obtain minimum cost allocation of demand to the eneration units is that it is computationally
More informationCE/CS Amplifier Response at High Frequencies
.. CE/CS Amplifier Response at High Frequencies INEL 4202 - Manuel Toledo August 20, 2012 INEL 4202 - Manuel Toledo CE/CS High Frequency Analysis 1/ 24 Outline.1 High Frequency Models.2 Simplified Method.3
More informationPipelined multi step A/D converters
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India 04 Nov 2006 Motivation for multi step A/D conversion Flash converters: Area and power consumption increase
More informationMonolithic N-Channel JFET Dual
N9 Monolithic N-Channel JFET Dual V GS(off) (V) V (BR)GSS Min (V) g fs Min (ms) I G Max (pa) V GS V GS Max (mv). to. Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: pa Low Noise:
More informationFeedback Control G 1+FG A
Introduction to Operational Amplifiers Circuit Functionality So far, only passive circuits (C, L and LC) have been analyzed in terms of the time-domain operator T and the frequency-domain operator A(ω),
More informationMaxim Integrated Products 1
19-4187; Rev 4; 7/1 μ μ PART AMPS PER PACKAGE PIN- PACKAGE + * TOP MARK MAX965AZK+ 1 5 SOT3 ADSI MAX965AZK/V+ 1 5 SOT3 ADSK MAX965AUA+ 1 8 μmax-ep* AABI MAX965ATA+ 1 8 TDFN-EP* BKX MAX9651AUA+ 8 μmax-ep*
More informationModeling of High Voltage AlGaN/GaN HEMT. Copyright 2008 Crosslight Software Inc.
Modelin of Hih Voltae AlGaN/GaN HEMT Copyriht 2008 Crossliht Software Inc. www.crossliht.com 1 Introduction 2 AlGaN/GaN HEMTs - potential to be operated at hih power and hih breakdown voltae not possible
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationLecture 46 Bode Plots of Transfer Functions:II A. Low Q Approximation for Two Poles w o
Lecture 46 Bode Plots of Transfer Functions:II A. Low Q Approximation for Two Poles w o ----------- ----------- w L =Q - w o πf o w h =Qw o w L ~ RC w h w L f(l) w h f(c) B. Construction from T(s) Asymptotes
More informationLecture 7, ATIK. Continuous-time filters 2 Discrete-time filters
Lecture 7, ATIK Continuous-time filters 2 Discrete-time filters What did we do last time? Switched capacitor circuits with nonideal effects in mind What should we look out for? What is the impact on system
More informationAnalog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras
Analog Integrated Circuit Design Prof. Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Lecture No - 42 Fully Differential Single Stage Opamp Hello and welcome
More informationEE 508 Lecture 24. Sensitivity Functions - Predistortion and Calibration
EE 508 Lecture 24 Sensitivity Functions - Predistortion and Calibration Review from last time Sensitivity Comparisons Consider 5 second-order lowpass filters (all can realize same T(s) within a gain factor)
More informationControl System Design
ELEC ENG 4CL4: Control System Design Notes for Lecture #22 Dr. Ian C. Bruce Room: CRL-229 Phone ext.: 26984 Email: ibruce@mail.ece.mcmaster.ca Friday, March 5, 24 More General Effects of Open Loop Poles
More informationEE 3CL4: Introduction to Control Systems Lab 4: Lead Compensation
EE 3CL4: Introduction to Control Systems Lab 4: Lead Compensation Tim Davidson Ext. 27352 davidson@mcmaster.ca Objective To use the root locus technique to design a lead compensator for a marginally-stable
More informationLecture 7: Transistors and Amplifiers
Lecture 7: Transistors and Amplifiers Hybrid Transistor Model for small AC : The previous model for a transistor used one parameter (β, the current gain) to describe the transistor. doesn't explain many
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationCDS 101/110a: Lecture 8-1 Frequency Domain Design
CDS 11/11a: Lecture 8-1 Frequency Domain Design Richard M. Murray 17 November 28 Goals: Describe canonical control design problem and standard performance measures Show how to use loop shaping to achieve
More informationEE 435. Lecture 22. Offset Voltages Common Mode Feedback
EE 435 Lecture Offset Voltages Common Mode Feedback Review from last lecture Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ Definition: The output offset
More informationV in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More information6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers
6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,
More information