PHYSICS BASED RELIABILITY QUALIFICATION

Transcription

1 PYSICS BASD RLIABILIY QUALIFICAIO Joseph B. Bernstein, Jin Qin Reliability ngineering University of Maryland, College Park, MD mail: Abstract We studied the effects of temperature and voltage acceleration on the reliability of semiconductor devices with multiple intrinsic failure mechanisms including: electromigration (M), hot carrier injection (CI), time dependent dielectric breakdown (DDB) and negative bias temperature instability (BI). Simulation shows that system activation energy and voltage acceleration parameters depend on stress temperature and voltage. raditional high temperature, high voltage qualification test tends to accelerate DDB much more than other failure mechanisms. As devices are further scaled down, not only DDB but other failure mechanisms should be constrained. o qualify advanced semiconductor device in multiple failure mechanisms era, a dominant-failure-mechanism based qualification plan is proposed in which specific test conditions are designed to screen target failure mechanism. I. IRODUCIO Microelectronics integration density is limited by the reliability of the manufactured product at a desired circuit density. Design rules, operating voltage and maximum switching speeds are chosen to insure functional operation over the intended lifetime of the product. In order to determine the ultimate performance for a given set of design constraints, the reliability must be modeled for its specific operating condition. hus, Reliability modeling for the purpose of lifetime prediction is the ultimate task of a failure physics evaluation. Unfortunately, all the industrial approaches to reliability evaluation fall short of predicting failure rates or wear-out lifetime of semiconductor products. his is attributed mainly to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods rely on the acceleration of one, dominant, failure mechanism. Over the past several decades, our knowledge about the root cause and physical behavior of the critical failure mechanisms in microelectronic devices has grown significantly. Confidence in the reliability models have lead to more aggressive design rules that have been successfully applied to the latest VLSI technology. One result of improved reliability modeling has been accelerated performance, beyond the expectation of Moore s Law. A consequence of more aggressive design rules has been a reduction in the weight of a single failure mechanism. ence in modern devices, there is no single failure mode that is more likely to occur than any other as guaranteed by the integration of modern failure physics and modern simulation tools in the design process. he consequence of more advanced reliability modeling tools is a new phenomenon of device failures resulting from a combination of several competing failure mechanism. oday, reliability device simulators have become an integral part of the design process. hese simulators successfully model the most significant physical failure mechanisms in modern electronic devices, such as ime Dependent Dielectric Breakdown (DDB), egative Bias emperature Instability (BI), lectromigration (M) and ot Carrier Injection (CI). hese mechanisms are modeled throughout the circuit design process so that the system will operate for a minimum expected useful life. Modern chips are composed of tens or hundreds of millions of transistors. ence, chip level reliability prediction methods are mostly statistical. Reliability prediction tools, now model the failure probability of chips at the end of life by analyzing only the single dominant wearout mechanism. Modern prediction tools do not predict the random, post burn-in, failure rate that would be seen in the field. Chip and packaged system reliability is still measured by failure rate in FI. he FI is a unit, defined as one failure per billion part hours. he semiconductor industry provides an expected FI for every product that is sold based on operation within the specified conditions of voltage, frequency, heat dissipation and etc. ence, a system reliability model is a prediction of the expected mean time between failures (MBF) for an entire system as the reciprocal of the sum of the FI rates for every component. Failure rate of component can be defined in terms of an acceleration factor, AF, as: λ = umber of failures umber of tested hours AF 09 F I () where umber of failures and umber of tested are the number of actual failures that occurred as a fraction of the total number of units subjected to an accelerated test. he acceleration factor, AF, must be supplied by the manufacturer since

2 2 only they know the failure mechanisms that are being accelerated in the igh emperature Operating Life (OL) and it is generally based on a company proprietary variant of the MIL-DBK-27 approach for accelerated life testing. he true task of reliability modeling, therefore, is to choose an appropriate value for AF based on the physics of the dominant failure mechanisms that would occur in the field for the device. he OL qualification test is usually performed as the final qualification step of a semiconductor manufacturing process. he test consists of stressing some number of parts, usually about 00, for an extended time, usually 000 hours, at an accelerated voltage and temperature. wo features shed doubt on the accuracy of this procedure. One feature is lack of sufficient statistical data and the second is that companies generally present zero-failure results for their qualification tests. Parts are stressed at relatively low levels to guarantee zero failures during qualification testing in accordance with their guidelines. Zero failures results in zero real data and the true statistical confidence is mathematically imaginary. he assumption, then, is that no more than one failure occurred during the accelerated test and substitute 2 failure to circumvent this imaginary confidence dillema. his results, based on our example parameters, in a reported F I = 5000/AF, which can be almost any value from less than FI to more than 500 FI, depending on the conditions and model used for the voltage and temperature acceleration. he accepted approach for measuring FI would, in theory, be reasonably appropriate if there is only a single dominant failure mechanism that is excited equally by either voltage or temperature. For example, M is known to follow Black s equation (described later) and is accelerated by increased stress current in a wire or by increased temperature of the device. If, however, multiple failure mechanisms are responsible for device failures, each failure mechanism should be modeled as an individual element in the system and the component survival is modelled as the survival probability of all the elements as a function of time. If multiple failure mechanisms, instead of a single mechanism, are assumed to be time-independent and independent of each other, FI (constant failure rate approximation) should be a reasonable approximation for realistic field failures. Under the assumption of multiple failure mechanisms, each will be accelerated differently depending on the physics that is responsible for each mechanism. If, however, an OL test is performed at an arbitrary voltage and temperature for acceleration based only on a single failure mechanism, then only that mechanism will be accelerated. In that instance, which is generally true for most devices, the reported FI (especially one based on zero failures) will be meaningless with respect to other failure mechanisms. II. IDIVIDUAL FAILUR MCAISM LIFIM MODL Relentless scaling for better performance keeps generating new reliability challenges to every aspects of the process technology. M, the main reliability concern of interconnects, needs to be handled carefully because feature size decreasing and temperature increasing pose dual threats towards new interconnect technology. o meet the performance and reliability requirement, copper interconnects have gradually take the place of Al(Cu) metallization in the past few years, due to its low resistivity and high resistance towards electromigration. Copper interconnects have different M characteristics compared with aluminum. It is interface dominated [] and has larger activation energies [2]. DDB has always received much attention because device scaling keeps driving the oxide thickness down but the supply voltage scaling doesn t keep pace. he direct impact of this non-ideal voltage scaling is the increase of gate leakage and tunneling current which decreases the oxide lifetime. An empirical observation is that if gate oxide thickness reduces by ox (in nm) by scaling, the leakage current will increase by 0 ox 0.22 [3], and DDB lifetime will reduce by the same factor. Oxide breakdown related failures are often reported in device burn-in test of deep submicron technologies [4], [5]. Device scaling also increases susceptibility to another failure mechanism: BI, which occurs primarily in p-channel MOSFs with negative gate voltage bias. he interface-trap density generated by BI has an inverse proportionality to oxide thickness ( ox ) which means BI becomes more severe for ultrathin oxides [6], while the BI generated fixed charge has no thickness dependence. Like BI for PMOS, CI induces interface states and causes degradation of MOS. Although well contained by channel engineering, it still shows up in real applications [7]. o model system reliability, all these intrinsic failure mechanisms should be considered since any one of them may cause system failure. Various lifetime models have been proposed for each failure mechsnism. As our goal is to show the unique characteristics of system lifetime and voltage and temperature acceleration, we will adapt the generally accepted models. Failure rate model and acceleration factors for M, CI, DDB and BI are listed below. ) M From the well known Black s equation [8] and Arrhenius model, failure rate of M can be expressed as: λ M (J) n exp[ am ] (2) k

3 3 where J is the current density in the interconnect, k is Boltzmann s constant, is absolute temperature in Kelvin, am is the activation energy, and n is a constant. Both am and n depend on the interconnect metal. owadays copper/low-k dielectric material has been rapidly replacing aluminum alloy/sio2-based interconnect. For copper, n has been reported with values between and 2 [] and am varies between 0.7eV and.ev [9]. In q. (2), current density J can be replaced with a voltage function [0]: J = C V D W f p (3) where C, W and are the capacitance, width and thickness of the interconnect, respectively. f is the frequency, p is the toggling probability. So λ M is also a function of voltage: λ M (V D ) n exp[ am ] (4) k 2) CI Based on the empirical CI voltage lifetime model proposed by akeda [] and the Arrhenius relationship, CI failure rate λ CI can be modeled as: λ CI exp[ γ CI V D ] exp[ aci ] (5) k where γ CI is a technology related constant, aci is the activation energy, varies between 0.eV 0.2eV [2]. he negative activation energy means CI becomes worse at low temperature. 3) DDB he exponential law for DDB failure rate voltage dependence has been widely used in gate oxide reliability characterization and extrapolation. Combining with the Arrhenius relationship for temperature dependence, DDB failure rate is λ DDB exp[γ DDB V G ] exp[ a DDB ] (6) k where γ DDB is a device related constant and a DDB is the activation energy. a DDB normally falls in the range of 0.6eV 0.9eV [2]. 4) BI Like DDB, BI voltage dependence can also be modeled by the exponential law [3], considering the temperature dependence together, BI failure rate is λ B I exp[γ B I V G ] exp[ ab I ] (7) k where γ B I is a constant and ab I is the activation energy which has been reported to vary from 0.eV to 0.84eV [4], [5]. III. SYSM VOLAG AD MPRAUR ACCLRAIO Assuming there is no interaction among failure mechanisms, system s failure rate can be obtained by sum-of-failure-rate since all failure mechanisms contribute to system failures. System acceleration factor can be expressed as: AF S = λv A, A S λ V O, O S λ S = λ M + λ CI + λ DDB + λ B I (8) = λv A, A M λ V O, O M + λv A, A CI + λv O, O CI + λ V A, A DDB + λv A, A B I + λ V O, O DDB + λv O, O B I Given the models of individual failure mechanisms, system acceleration factor (9) can be further expressed as: AF S = P V O, O AF M + P V O, O AF CI + P V O, O (9) AF DDB + P V O, O AF B I (0) where P V O, O, P V O, O, P V O, O and P V O, O are failure percentages of M, CI, DDB and BI at stress conditions (V O, O ), respectively. he advantage of using these failure percentages here is to simplify the derivation process without the need to find out the absolute failure rate for each failure mechanism. For property issue, original microelectronic device lifetime data is rarely reported in literature. In order to reveal the characteristics of temperature and voltage acceleration at system level, we do lifetime simulation by using the models given above. System is assumed to be made with 0.3µm technology and the oxide thickness is 3.2nm. ominal operating conditions are V O =.3V, O = 75 C. CI, DDB and BI are assumed to contribute equally to system failures at nominal conditions. All the acceleration parameters are extracted from published result related to 0.3µm technology (CI [6], DDB [7] and BI [8])and listed in able I.he simulation parameters are listed in able I below. We assume V O =.3V, O = 75 C.

4 4 ABL I SIMULAIO PARAMRS FOR M, CI, DDB AD BI Voltage acceleration Activation energy Failure parameter (ev) percentage M % CI % DDB % BI % A. on-arrhenius emperature Acceleration Designate Vi,i asy S as the activation energy estimated from accelerated tests at (V i, i ) and (V i, A ). If the Arrhenius relationship still holds at system level, Vi,i asy S should be the same for all i and V i. System temperature acceleration factor AFS can be calculated as: AFS = P Vi,i AFM + P Vi,i AFCI + P Vi,i AF DDB + P Vi,i AFB I () where P Vi,i, P Vi,i, P Vi,i and P Vi,i are the percentages of M, CI,DDB and BI failure at (V i, i ), respectively. Using the parameters given in able I and set A =25 C, we did asy S estimation at various i under three voltages:.7v,.30v and.43v and show the result in Fig.. he simulation result clearly shows that asy S is not a constant. It depends.2..7v.3v.43v 0.9 a (ev) i ( C) Fig.. System activation energies estimated from simulated failure rate at (V i, i ) and (V i, A ). V i =.7V,.30V and.43v. At given V i, A =25 C and i varies from 25 C to 24 C. on the stress voltage V i and the stress temperature i. At given V i, Vi,i asy S is an increasing function of i. he reason is that failure mechanism with larger activation energy will increase its failure percentage at high temperature at given stress voltage. For illustration, if A i is considerably small, system activation energy can be approximated by: Vi,i asy S = P Vi,i M am + P Vi,i CI aci + P Vi,i DDB a DDB + P Vi,i B I ab I (2) From q. (2), we can find that at given am, aci, a DDB and ab I, Vi,i Vi,i asy S depends on P, P Vi,i, P Vi,i and P Vi,i. Failure mechanism with largest activation energy will be accelerated the most as temperature increase and its failure percentage will increase accordingly. As asy S is generally estimated from high temperature acceleration test, using that activation energy tends to give an optimistic projection at low temperature. For an example, if the acceleration tests were done at (.43V, 25 C) and (.43V, 5 C), the estimated asy S is.0ev. Using this activation energy to extrapolate system failure rate at (.43V, 50 C) will get an optimistic estimation which is /4 of the real rate because the true asy S is 0.60eV. B. Stress-Dependent Voltage Acceleration Factor o show the characteristic of voltage acceleration, we assume AF V S AF V S follows exponential law. = exp[γ Vi,i SY S (V A V i )] (3)

5 5 where γ Vi,i SY S is the voltage acceleration parameter. AF V S AF V S = P Vi,i AF V M + P Vi,i is shown below. AF V CI + P Vi,i AF V DDB + P Vi,i AF V B I (4) where P Vi,i, P Vi,i, P Vi,i and P Vi,i have the same meaning as in q. (). Simulation was done with parameters given in able I and the estimated γ SY S is shown in Fig. 2. Result shows that γ SY S varies according to V i and i. For approximation, 0 25 C 75 C 25 C 9 8 γ SYS V i (V) Fig. 2. stimated γ SY S from failure rates at accelerated conditions (V i, i ) and (V A, i ). i =25 C, 75 C and 25 C. For each i, V A =.56V, V i varies from.04v to.55v. if the difference between V A and V i is reasonably small, γ Vi,i SY S b Vi,i SY S = P Vi,i n + P Vi,i V i γci V 2 i can be approximated by: + P Vi,i γ DDB + P Vi,i γ B I (5) Like Vi,i asy S, γvi,i SY S also depends on the failure percentages and the voltage acceleration parameters. As shown in Fig.2, at 25 C, γ asy S is larger at higher stress voltage because DDB together with BI dominate here and the higher voltage accelerates them more than M and CI. Using γ SY S estimated at (25 C,.55V )to extrapolate system failure rate at low voltage will give an optimistic estimation. At 25 Cand V i =.55V, γ SY S is estimated to be 0.0, while we will get 7.0 if V i =.30V. here is about 5X difference in failure rate extrapolation. C. Combined Voltage and emperature Acceleration Factor he effect of voltage and temperature acceleration together on system acceleration is further complicated by the interplay between the factors, as shown above. Since there is no universal asy S and γ SY S if multiple failure mechanisms are involved, using AF with one activation energy and AF V with one voltage acceleration parameter for reliability extrapolation is not appropriate. ake the simulation above as an example, we find out that failure rate estimation using the multiplication model gives an optimistic result. he real system failure rate at (50 C,.30V) is 20X of the estimated failure rate using the multiplication model with asy S and γ SY S from high temperature, high voltage acceleration test at (25 C,.55V). IV. QUALIFICAIO BASD O FAILUR MCAISM It is a matter of great complexity to build a system lifetime model to fit all temperatures and voltages if there are multiple failure mechanisms involved. he conventional extrapolation method using one asy S and γ SY S tends to give an optimistic estimation. For reliability qualification considering multiple failure mechanisms, acceleration tests should be designed to accelerate the target failure mechanism with specific stress conditions. his is workable because each failure mechanism has its unique activation energy and voltage acceleration parameter. Among these failure mechanisms, only CI has negative activation energy while others are positive. his means lowering stress temperature will accelerate CI while decelerate other three failure mechanisms. CI also has a comparable large γ. So at low temperature and reasonable high voltage, CI failure will dominate. For M, since copper interconnect has a larger activation energy and small γ ( 2), acceleration test should be designed with high temperature and low voltage. raditional acceleration test with high temperature and voltage can be applied to accelerate DDB and BI since both have large voltage acceleration parameter and activation energy. Failure percentage of each failure mechanism at various accelerated conditions are shown in Fig. 3.

6 emperature( C) Voltage (V) (a) M failure percentage emperature( C) 25. Voltage (V).0 (b) CI failure percentage Voltage (V) emperature( C) (c) DDB failure percentage emperature( C) Voltage (V) (d) BI failure percentage Fig. 3. Failure percentages of M, CI, DDB and BI at different accelerated conditions. V. COCLUSIO For semiconductor device, reliability modeling at system level is complicated by the involvement of multiple failure mechanisms which have the same stress factors-voltage and temperature. he Arrhenius relationship with one activation energy for all temperature is showed to be not valid at system level if these failure mechanisms don t have the same activation energy. he same happens to the modeling of voltage dependence. Using exponential law with only one constant coefficient is a good option for individual failure mechanism but not for system. We propose a failure mechanism based qualification method which quantify each failure mechanism thorough acceleration test with specifically designed stress conditions. RFRCS [] C. K. u and R. Rosenberg, Scaling effect on electromigration in on-chip cu wiring, in IIC, pp , 999. [2] C.-K. u, L. Gignac, and R. Rosenberg, lectromigration of cu/low dielectric constant interconnects, Microelectronics and Reliability, vol. 46, no. 2-4, pp , [3] J.. Stathis, Reliability limits for the gate insulator in cmos technology, IBM Journal of Research and Development, vol. 46, no. 2/3, pp , [4]. J. Anderson and J. M. Carulli Jr., Modeling and monitoring of product DPPM with multiple fail modes, in IRPS, pp , [5] Y.. Lee,. Mielke, M. Agostinelli, S. Gupta, R. Lu, and W. McMahon, Prediction of logic product failure due to thin-gate oxide breakdown, in IRPS, pp. 8 28, [6] S. Ogawa and. Shiono, Generalized diffusion-reaction model for the low-field charge-buildup instability at the si-sio2 interface, Physical Review B, vol. 5, no. 7, pp , 995. [7] W. Bornstein, R. Dunn, and. Spielberg, Field degradation of memory components due to hot carriers, in IRPS, pp , [8] J. R. Black, Mass transport of aluminum by momentum exchange with conducting electron, in Proc. Sixth Ann. Reliability Physics Symp, pp , 967. [9] J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, he case for lifetime reliability-aware microprocessor, in I Proceedings of 3 st Annual International Symposium on Computer Architecture, [0] A. Dasgupta and R. Karri, lectromigration reliability enhancement via bus activity distribution, in 33rd Design Automation Conference, (Las Vegas, V, USA), 996. []. akeda and. Suzuki, An empirical model for device degradation due to hot-carrier injection, I lectron Device Letters, vol. DL-4, pp. 3, 983. [2] JDC, Failure Mechanisms and Models for Semiconductor Devices. JDC Solid State echnology Association, [3] S. Chakravarthi, A.. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, A comprehensive framework for predictive modeling of negative bias temperature instability, in 42nd IRPS, pp , I, [4] P. Chaparala, J. Shibley, and P. Lim, hreshold voltage drift in PMOSFS due to BI and CI, in IRW, pp , I, [5] S. Mahapatra, P. B. Kumar, and M. A. Alam, Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-mosfs, I ransactions on lectron Devices, vol. 5, no. 9, pp , [6] J.-C. Lin, S.-Y. Chen,.-W. Chen, Z.-W. Jhou,.-C. Lin, S. Chou, J. Ko,.-F. Lei, and.-s. aung, Investigation of dc hot-carrier degradation at elevated temperatures for n-channel metal-oxide-semiconductor field-effect-transistor of 0.3µm technology, Japanese Journal of Applied Physics,Part : Regular Papers and Short otes and Review Papers, vol. 45, pp , Apr [7]. Wu and J. Sune, Power-law voltage acceleration: A key element for ultrathin gate oxide reliability, Microelectronics Reliability, [8] D. K. Schroder and J. A. Babcock, egative bias temperature instability: Road to cross in deep submicron semiconductor manufacturing, Journal of Applied Physics, vol. 94, pp. 8, 2003.