74F573 Octal transparent latch (3-State) 74F574 Octal transparent latch (3-State)

Transcription

1 INTGRAT CIRCUITS 74F573 Octal traparent latch (3-State) 74F574 Octal traparent latch (3-State) 989 Oct IC ata andbook

2 atch/flip-flop 74F573 Octal Traparent atch (3-State) 74F574 Octal Flip-Flop (3-State) FATURS 74F573 is broadside pinout version of 74F373 74F574 is broadside pinout version of 74F374 Inputs and Outputs on opposite side of package allow easy interface to Microprocessors Useful as an Input or Output port for Microprocessors 3-State Outputs for Bus interfacing Common Output nable 74F563 and 74F564 are inverting version of 74F573 and 74F574 respectively 3-State Outputs glitch free during power-up and power-down These are igh-speed replacements for N8TS805 and N8TS806 The 74F574 is functionally identical to the 74F374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocesors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sectio of the device are controlled independently by the clock () and Output nable (O) control gates. The register is fully edge-triggered. The state of each input, one setup time before the ow-to-igh clock traition is traferred to the corresponding flip-flop s output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active ow Output nable (O) controls all eight 3-State buffers independently of the latch operation. When O is ow, the latched or traparent data appears at the outputs. When O is igh, the outputs are in high impedance off state, which mea they will neither drive nor load the bus. SCRIPTION The 74F573 is an octal traparent latch coupled to eight 3-State output buffers. The two sectio of the device are controlled independently by nable () and Output nable (O) control gates. The 74F573 is functionally identical to the 74F373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the inputs is traferred to the latch outputs when the nable () input is igh. The latch remai traparent to the data input while is igh and stores the data that is present one setup time before the igh-to-ow enable traition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active ow Output nable (O) controls all eight 3-State buffers independent to the latch operation. When O is ow, the latched or traparent data appears at the outputs. When O is igh, the outputs are in high impedance off state, which mea they will neither drive nor load the bus. TYP TYPICA PROPAGATION AY TYPICA SUPPY CURRNT (TOTA) 74F mA TYP TYPICA f MAX CURRNT TYPICA SUPPY (TOTA) 74F574 0Mz 50mA ORRING INFORMATION SCRIPTION COMMRCIA RANG V CC = 5V ±0%, T amb = 0 C to +70 C PKG WG # 20-Pin Plastic IP N74F573N, N74F574N SOT6-20-Pin Plastic SO N74F573, N74F574 SOT3-20-Pin Plastic SSOP N74F573B SOT339- INPUT AN OUTPUT OAING AN FAN-OUT TAB PINS SCRIPTION 74F (U..) IG/OW OA VAU IG/OW 0-7 ata inputs / 20µA/0.6mA (74F573) atch nable input (active falling edge) / 20µA/0.6mA O Output nable input (active ow) / 20µA/0.6mA (74F574) Clock Pulse input (active rising edge) / 20µA/0.6mA State outputs 0/40 ma/24ma NOT: One () FAST Unit oad is defined as: 20µA in the igh state and 0.6mA in the ow state. 989 Oct

3 atch/flip-flop PIN CONFIGURATION 74F573 PIN CONFIGURATION 74F574 O 20 V CC O 20 V CC GN 0 GN 0 SF0073 SF0074 OGIC SYMBO 74F573 OGIC SYMBO 74F O O V CC =Pin 20 GN=Pin 0 SF0075 V CC =Pin 20 GN=Pin 0 SF0076 OGIC SYMBO (I/IC) 74F573 OGIC SYMBO (I/IC) 74F574 N N2 N C SF0077 SF Oct 3

4 atch/flip-flop OGIC IAGRAM 74F O V CC =Pin 20 GN=Pin SF0079 FUNCTION TAB 74F573 INPUTS INTRNA OUTPUTS O n RGISTR 0 7 OPRATING MOS oad and read register l h atch and read register X NC NC old X NC Z n n Z isable outputs = igh voltage level h = igh voltage level one setup time prior to the igh-to-ow traition = ow voltage level l = ow voltage level one setup time prior to the igh-to-ow traition NC= No change X = on t care Z = igh impedance off state = igh-to-ow traition OGIC IAGRAM 74F O V CC =Pin 20 GN=Pin SF Oct 4

5 atch/flip-flop FUNCTION TAB 74F574 INPUTS INTRNA OUTPUTS O n RGISTR 0 7 OPRATING MOS l h oad and read register X NC NC old n n Z isable outputs = igh voltage level h = igh voltage level one setup time prior to the ow-to-igh clock traition = ow voltage level l = ow voltage level one setup time prior to the ow-to-igh clock traition NC= No change X = on t care Z = igh impedance off state = ow-to-igh clock traition = Not a ow-to-igh clock traition ABSOUT MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBO PARAMTR RATING UNIT V CC Supply voltage 0.5 to +7.0 V V IN Input voltage 0.5 to +7.0 V I IN Input current 30 to +5.0 ma V OUT Voltage applied to output in igh output state 0.5 to +V CC V I OUT Current applied to output in ow output state 48 ma T amb Operating free-air temperature range 0 to +70 C T stg Storage temperature 65 to +0 C RCOMMN OPRATING CONITIONS SYMBO PARAMTR IMITS MIN NOM MAX V CC Supply voltage V V I igh-level input voltage 2.0 V V I ow-level input voltage 0.8 V I IK Input clamp current ma I O igh-level output current 3 ma I O ow-level output current 24 ma T amb Operating free-air temperature range 0 70 C UNIT 989 Oct 5

6 atch/flip-flop C CTRICA CARACTRISTICS (Over recommended operating free-air temperature range unless otherwise noted.) IMITS SYMBO PARAMTR TST CONITIONS MIN TYP MAX UNIT V O V O igh-level output voltage ow-level output voltage V CC = MIN, V I = MAX, ±0%V CC 2.4 V V I = MIN, I O = MAX ±5%V CC V V CC = MIN, V I = MAX, ±0%V CC V V I = MIN, I O = MAX ±5%V CC V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at maximum input voltage V CC = MAX, V I = 7.0V 00 µa I I igh-level input current V CC = MAX, V I = 2.7V 20 µa I I ow-level input current V CC = MAX, V I = 0.5V 0.6 ma I OZ I OZ Off-state output current, igh-level voltage applied Off-state output current, ow-level voltage applied V CC = MAX, V O = 2.7V 50 µa V CC = MAX, V O = 0.5V 50 µa I OS Short-circuit output current V CC = MAX 60 0 ma I CC I CC ma I CC 74F573 V CC = MAX ma Supply I CCZ ma current (total) I CC ma I CC 74F574 V CC = MAX ma I CCZ ma NOTS:. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a igh output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 989 Oct 6

7 atch/flip-flop AC CTRICA CARACTRISTICS SYMBO t P t P t P t P t PZ t PZ t PZ t PZ f MAX t P t P t PZ t PZ t PZ t PZ Propagation delay n to n Propagation delay to n PARAMTR Output nable time to igh or ow level Output isable time from igh or ow level Maximum Clock frequency Propagation delay to n Output nable time to igh or ow level Output isable time from igh or ow level 74F573 74F574 TST CONITIONS T amb = +25 C V CC = +5V C = 50pF, R = 500Ω IMITS T amb = 0 C to +70 C V CC = +5V ± 0% C = 50pF, R = 500Ω MIN TYP MAX MIN MAX UNIT Mz AC STUP RUIRMNTS SYMBO t s () t s () t h () t h () t w () t s () t s () t h () t h () t w () t w () Setup time, n to old time, n to pulse width, igh Setup time, n to old time, n to Pulse width, igh or ow PARAMTR TST CONITIONS 4 74F F574 T amb = +25 C V CC = +5V C = 50pF, R = 500Ω IMITS T amb = 0 C to +70 C V CC = +5.0V ± 0% C = 50pF, R = 500Ω MIN TYP MAX MIN MAX UNIT 989 Oct 7

8 atch/flip-flop AC WAVFORMS For all waveforms, =.5V The shaded areas indicate when the input is permitted to change for predictable output performance. /f MAX, n t W () t W () t P t P t P t P n n SF008. Propagation elay, Clock and nable Inputs to Output, nable, Clock Pulse Widths, and Maximum Clock Frequency SF Propagation elay for ata to Outputs n n t s () t h () t s () t h () t s () t h () t s () t h () SF009 SF ata Setup and old Times 4. ata Setup and old Times O O t PZ t PZ V O -0.3V t PZ t PZ n 0V n V O +0.3V SF00343 SF State Output nable Time to igh evel and Output isable Time from igh evel 6. 3-State Output nable Time to ow evel and Output isable Time from ow evel 989 Oct 8

9 atch/flip-flop TST CIRCUIT AN WAVFORM PUS GNRATOR V IN V CC.U.T. V OUT R 7.0V NGATIV PUS 90% 0% t T ( t f ) t w t T ( t r ) 0% 90% AMP (V) 0V R T C R Test Circuit for 3-State Outputs SWITC POSITION TST SWITC t PZ closed t PZ closed All other open POSITIV PUS 0% t T ( t r ) t T ( t f ) 90% 90% t w Input Pulse efinition 0% AMP (V) 0V FINITIONS: R = oad resistor; see AC electrical characteristics for value. C = oad capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F INPUT PUS RUIRMNTS amplitude rep. rate t w t T t T V.5V Mz 500 SF Oct 9

10 atch/flip-flop 74F573, 74F574 IP20: plastic dual in-line package; 20 leads (300 mil) SOT6-989 Oct 0

11 atch/flip-flop 74F573, 74F574 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT3-989 Oct

12 atch/flip-flop 74F573, 74F574 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT Oct

13 atch/flip-flop 74F573, 74F574 NOTS 989 Oct

14 atch/flip-flop 74F573, 74F574 ata sheet status ata sheet status Product status efinition [] Objective specification Preliminary specification Product specification evelopment ualification Production This data sheet contai the design target or goal specificatio for product development. Specification may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contai final specificatio. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [] Please coult the most recently issued datasheet before initiating or completing a design. efinitio Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. imiting values definition imiting values given are in accordance with the Absolute Maximum Rating System (IC 4). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditio above those given in the Characteristics sectio of the specification is not implied. xposure to limiting values for extended periods may affect device reliability. Application information Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. isclaimers ife support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 8 ast Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips lectronics North America Corporation 998 All rights reserved. Printed in U.S.A. print code ate of release: 0-98 ocument order number: yyyy mmm dd

15 Mouser lectronics Authorized istributor Click to View Pricing, Inventory, elivery & ifecycle Information: Nexperia: N74F573,602 N74F574N,602 NXP: N74F573 N74F573-T N74F573B N74F573B-T N74F573N N74F574 N74F574N N74F573B, N74F573B, N74F573N,602 N74F574,602