8-bit shift register with 2:1 mux-in, latched B inputs, and serial out N74F835N FEATURES PIN CONFIGURATION

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1 FATURS Specifically designed for Video applicatio Combines the 74F373, two 74F57s, and the 74F66 functio in one package Interleaved loading with : mux ual 8-bit parallel inputs Traparent latch on all B inputs Guaranteed serial shift frequency to 00MHz xpandable to 6-bits or more with serial input SCRIPTION The is a high speed 8-bit parallel/serial-in, serial-out shift register whose parallel inputs have been connected to an internal octal two-to-one multiplexer with all the B inputs connected to an octal latch. This 4-pin part is specifically designed for video bit shifting, where interleaved loading is desired and parts count is critical. It is useful in any design where a : mux input with a traparent latch is needed. TYP TYPICAL f MAX SUPPLY CURRNT TYPICAL (TOTAL) 50MHz 45mA PIN CONFIGURATION P 4A 4B 5A 5B 6A 6B 7A 7B 7 GN ORRING INFORMATION SCRIPTION 4-pin plastic Slim IP (300 mil) V CC 3B 3A B A B A 0B 0A S L COMMRCIAL RANG V CC = 5V ±0%, T amb = 0 C to +70 C NN SF0355 PACKAG RAWING NUMBR SOT- 4-pin plastic SOL N SOT37- INPUT AN OUTPUT LOAING AN FAN-OUT TABL PINS SCRIPTION 74F (U.L.) HIGH/LOW LOA VALU HIGH/LOW 0A 7A Parallel data inputs / 0µA/0.6mA 0B 7B Latched Parallel data inputs / 0µA/0.6mA S Serial data input / 0µA/0.6mA Shift Register Clock input (active rising edge) / 0µA/0.6mA Mux Select / 0µA/0.6mA L Latch nable input (for B inputs) / 0µA/0.6mA P Parallel nable input / 0µA/0.6mA 7 Output 50/33 ma/0ma NOT: One () FAST unit load is defined as: 0µA in the High state and 0.6mA in the Low state. 990 Jan

2 LOGIC SYMBOL IC/I SYMBOL S 0B B 0A A A B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 3 SRG 8 C MUX M4 N3 G 3 P L V CC = PIN 4 GN = PIN 7 SF ,4,, 3, 4,, 3, 4 SF0357 TYPICAL TIMING IAGRAM P LOA A UNLOA B LATCH SHIFT A SHIFT B LOA B LATCH L ÉÉÉÉ ÉÉÉÉ 0A ST B ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉ 7A 0B 7B q7a q6a qa q0a q7b q6b q5b q0b 7 SF Jan 08

3 LOGIC IAGRAM L 3 0B 0A 7 6 B A 9 8 B A 0 3B 3A 3 4B 4A 4 3 5B 5A 6 5 6B 6A 8 7 7B 7A 0 9 P S 5 7 V CC = PIN 4 GN = PIN SF0358 FUNCTION TABL OPRATING MO Parallel load A data INPUTS P L na nb S L X L Latch B data X X L X Parallel load B data (from Latch) Parallel load B data (Traparent Mode) L L H L H H Serial Shift H X X INTRNAL OUTPUT B SRIAL RGISTR LATCH h X X X H H H l X X X L L L X h X H X X X X l X L X X X X X X h H H H X X X l L L L X h X h H H H X l X l L L L X X h X H qn q6 X X l X L qn q6 H = High voltage level L = Low voltage level h = High voltage level one setup time prior to the Low-to-High clock traition l = Low voltage level one setup time prior to the Low-to-High clock traition X = on t care qn = Lower case letters indicate the state of the referenced flop cell one cycle prior to the Low-to-High clock traition = Low-to-High clock traition 990 Jan 08 3

4 ABSOLUT MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMTR RATING V CC Supply voltage 0.5 to + V V IN Input voltage 0.5 to + V I IN Input current 30 to +5 ma V OUT Voltage applied to output in High output state 0.5 to V CC V I OUT Current applied to output in Low output state 40 ma T amb Operating free-air temperature range 0 to +70 C T stg Storage temperature range 65 to +50 C RCOMMN OPRATING CONITIONS SYMBOL PARAMTR MIN NOM MAX V CC Supply voltage 5.5 V V IH High-level input voltage.0 V V IL Low-level input voltage 0.8 V I IK Input clamp current 8 ma I OH High-level output current ma I OL Low-level output current 0 ma T amb Operating free-air temperature range C C LCTRICAL CHARACTRISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMTR TST CONITIONS MIN TYP MAX V OH V OL High-level output voltage Low-level output voltage V CC = MIN, V IL = MAX ±0% V CC.5 V V IH = MIN, I OH = MAX ±5% V CC V V CC = MIN, V IL = MAX ±0% V CC V V IH = MIN, I OH L= MAX ±5% V CC V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at maximum input voltage V CC = MAX, V I = V 00 µa I IH High-level input current V CC = MAX, V I =.7V 0 µa I IL Low-level input current V CC = MAX, V I = 0.5V 0.6 ma I OS Short circuit output current 3 V CC = MAX ma I CC Supply current (total) V CC = MAX ma NOTS:. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type.. All typical values are at V CC = 5V. T amb = 5 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other tests. In any sequence of parameter tests, I OS tests should be performed last. 990 Jan 08 4

5 AC LCTRICAL CHARACTRISTICS SYMBOL PARAMTR TST CONITION T amb = +5 C V CC = +V T amb = 0 C to +70 C V CC = +V ± 0% MIN TYP MAX MIN MAX f MAX Maximum clock frequency Waveform MHz t PLH t PHL t PLH t PHL Propagation delay to 7 (Load) Propagation delay to 7 (Shift) Waveform Waveform AC STUP RUIRMNTS SYMBOL t w (H) t w (L) t w (H) PARAMTR na or nb to na or nb to S to S to P to P to nb to L nb to L to to clock pulse width, High or Low Latch nable pulse width, High TST CONITION Waveform T amb = +5 C V CC = +V T amb = 0 C to +70 C V CC = +V ± 0% MIN TYP MAX MIN MAX Waveform 990 Jan 08 5

6 AC WAVFORMS For all waveforms, =.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. /f MAX S, P t W (H) t W (L) na, nb t PHL t PLH 7, L SF0087 Waveform. Propagation elay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency. SF0360 ata and Select Setup and Hold Times TST CIRCUIT AN WAVFORMS PULS GNRATOR V IN V CC.U.T. V OUT NGATIV PULS 0% t THL ( t f ) t w t TLH ( t r ) 0% AMP (V) 0V R T C L R L Test Circuit for Totem-Pole Outputs POSITIV PULS 0% t TLH ( t r ) t w t THL ( t f ) 0% AMP (V) 0V FINITIONS: R L = Load resistor; see AC LCTRICAL CHARACTRISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC LCTRICAL CHARACTRISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F Input Pulse efinition INPUT PULS RUIRMNTS amplitude rep. rate t w t TLH t THL 3.0V.5V MHz SF Jan 08 6

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook

INTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook INTEGRATED CIRCUITS Triple 3-Input AND gate 1991 Feb 08 IC05 Data Handbook TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 5.5ns 1.3mA PIN CONFIGURATION 1A 1 1B 2 14 13 V CC 1C ORDERING INFORMATION