INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRATED IRUITS DATA SHEET For a complete data sheet, please also download: The I06 74H/HT/HU/HMOS Logic Family Specificatio The I06 74H/HT/HU/HMOS Logic Package Information The I06 74H/HT/HU/HMOS Logic Package Outlines 74H/HT109 Supersedes data of December 90 File under Integrated ircuits, I06 97 Nov 2

2 74H/HT109 FEATURES J, K inputs for easy D-type flip-flop Toggle flip-flop or do nothing mode Output capability: standard I category: flip-flops GENERAL DESRIPTION The 74H/HT109 are high-speed Si-gate MOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDE standard no. 7A. The 74H/HT109 are dual ed, JK flip-flops with individual J, K inputs, clock (P) inputs, set (S D ) and reset (R D ) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock traition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUIK REFERENE DATA GND = 0 V; T amb = 2 ; t r = t f = 6 TYPIAL SYMBOL PARAMETER ONDITIONS H HT UNIT / np to nq, nq 1 17 L = 1 pf; ns D to nq, nq 12 V = V nr D to nq, nq 12 1 f max maximum clock frequency 7 61 MHz I input capacitance pf PD power dissipation 22 pf notes 1 and 2 capacitance per flip-flop Notes 1. PD is used to determine the dynamic power dissipation (P D in µw): P D = PD V 2 f i + ( L V 2 f o ) where: f i = input frequency in MHz f o = output frequency in MHz ( L V 2 f o ) = sum of outputs L = output load capacitance in pf V = supply voltage in V 2. For H the condition is V I = GND to V For HT the condition is V I = GND to V 1. V. ORDERING INFORMATION See 74H/HT/HU/HMOS Logic Package Information. 97 Nov 2 2

3 74H/HT109 PIN DESRIPTION PIN NO. SYMBOL NAME AND FUNTION 1, 1 1R D, 2R D asynchronous reset-direct input (active LOW) 2,, 3, 13 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2 4, 12 1P, 2P clock input (LOW-to-HIGH, edge-triggered), 11 1S D, 2S D asynchronous set-direct input (active LOW) 6, 10 1Q, 2Q true flip-flop outputs 7, 9 1Q, 2Q complement flip-flop outputs 8 GND ground (0 V) 16 V positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IE logic symbol. 97 Nov 2 3

4 74H/HT109 FUNTION TABLE OPERATING INPUTS OUTPUTS MODE S D R D P J K Q Q asynchronous set L H X X X H L asynchronous reset H L X X X L H undetermined L L X X X H H toggle H H h l q q load 0 (reset) H H l l L H load 1 (set) H H h h H L hold no change H H l h q q Fig.4 Functional diagram. Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH P traition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH P traition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH P traition X = don t care = LOW-to-HIGH P traition handbook, full pagewidth Q K Q J S R P MBK217 Fig. Logic diagram (one flip-flop). PAKAGE OUTLINES See 74H/HT/HU/HMOS Logic Package Outlines. 97 Nov 2 4

5 74H/HT109 D HARATERISTIS FOR 74H For the D characteristics see 74H/HT/HU/HMOS Logic Family Specificatio. Output capability: standard I category: flip-flops A HARATERISTIS FOR 74H GND = 0 V; t r = t f = 6 ; L = 0 pf T amb ( ) TEST ONDITIONS SYMBOL PARAMETER 74H to to +12 min. typ. max. min. max. min. max. UNIT V (V) WAVEFORMS / np to nq, nq ns D to nq ns D to nq nr D to nq nr D to nq t THL / t TLH output traition time clock pulse width HIGH or LOW set or reset pulse width HIGH or LOW t rem removal time ns D,nR D to np t su set-up time nj, nk to np t h hold time nj, nk to np f max maximum clock pulse frequency MHz 97 Nov 2

6 74H/HT109 D HARATERISTIS FOR 74HT For the D characteristics see 74H/HT/HU/HMOS Logic Family Specificatio. Output capability: standard I category: flip-flops A HARATERISTIS FOR 74HT GND = 0 V; t r = t f = 6 ; L = 0 pf T amb ( ) TEST ONDITIONS SYMBOL PARAMETER 74HT to to +12 min. typ. max. min. max. min. max. / np to nq, nq ns D to nq ns D to nq nr D to nq nr D to nq t THL / t TLH output traition time clock pulse width HIGH or LOW set or reset pulse width HIGH or LOW 16 8 t rem removal time ns D, nr D to np 16 8 t su set-up time nj, nk to np t h hold time nj, nk to np f max maximum clock pulse frequency MHz UNIT V (V) WAVEFORMS 97 Nov 2 6

7 74H/HT109 A WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. Waveforms showing the clock (np) to output (nq, nq) s, the clock pulse width, the nj, nk to np set-up, the np to nj, nk hold times, the output traition times and the maximum clock pulse frequency. handbook, full pagewidth np INPUT t rem ns D INPUT t rem nr D INPUT nq OUTPUT nq OUTPUT H: = 0%; V I = GND to V. HT: = 1.3 V; V I = GND to 3 V. MBK216 Waveforms showing the set (ns D ) and reset (nr D ) input to output (nq, nq) s, the set and reset pulse widths and the nr D, ns D to np removal time. 97 Nov 2 7

8 74H/HT109 SOLDERING Introduction There is no soldering method that is ideal for all I packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted Is, or for printed-circuits with high population deities. In these situatio reflow soldering is often used. This text gives a very brief iight to a complex technology. A more in-depth account of soldering Is can be found in our I Package Databook (order code ). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 ; solder at this temperature must not be in contact with the joint for more than seconds. The total contact time of successive solder waves must not exceed seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max ). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400, contact may be up to seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspeion of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispeing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 0 and 300 seconds depending on heating method. Typical reflow temperatures range from 21 to. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 4 minutes at 4. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditio must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the dowtream end. Even with these conditio: Only coider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP (SOT266-1). Do not coider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP6 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin trafer or syringe dispeing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 10 within 6 seconds. Typical dwell time is 4 seconds at. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applicatio. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than V) applied to the flat part of the lead. ontact time must be limited to 10 seconds at up to 300. When using a dedicated tool, all other leads can be soldered in one operation within 2 to seconds between 270 and Nov 2 8

9 74H/HT109 DEFINITIONS Data sheet status Objective specification This data sheet contai target or goal specificatio for product development. Preliminary specification This data sheet contai preliminary data; supplementary data may be published later. This data sheet contai final product specificatio. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IE 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditio above those given in the haracteristics sectio of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLIATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applicatio do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 97 Nov 2 9

INTEGRATED CIRCUITS. For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

INTEGRATED CIRCUITS. For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications Dual D-type flip-flop with set and reset; Supersedes data of September