74HC74; 74HCT General description. 2. Features and benefits. 3. Ordering information
|
|
- Julia Page
- 6 years ago
- Views:
Transcription
1 Rev ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74H74 and 74HT74 are dual positive edge triggered D-type flip-flop. They have individual data (nd), clock (np), set (nsd) and reset (nrd) inputs, and complementary nq and nq outputs. Data at the nd-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nq output. Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of V. Input levels: For 74H74: MOS level For 74HT74: TTL level Symmetrical output impedance Low power dissipation High noise immunity Balanced propagation delays Specified in compliance with JEDE standard no. 7 ESD protection: HBM JESD22-114F exceeds 2000 V MM JESD exceeds 200 V Multiple package options Specified from 40 to+85 and from 40 to+125 Table 1. Ordering information Type number Package Temperature range Name Description Version 74H74N 40 to +125 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT HT74N 74H74D 40 to +125 SO14 plastic small outline package; 14 leads; body width SOT HT74D 74H74DB 74HT74DB 40 to +125 SSOP mm plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
2 Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74H74PW 74HT74PW 40 to +125 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74H74BQ 40 to +125 DHVQFN14 plastic dual in-line compatible thermal enhanced very 74HT74BQ thin quad flat package; no leads; 14 terminals; body mm 4. Functional diagram SOT402-1 SOT SD SD 2SD SD 1D Q 1Q D 2D 2Q 1P P 2P FF 1Q Q 2Q RD 1RD 2RD mna S 1 1D R S 1 1D R mna D 2 1P 3 1 1RD 10 2SD 12 2D 11 2P 13 2RD SD D P FF RD SD D P FF RD Q 1Q 5 1Q Q 6 Q 2Q 9 2Q Q 8 mna420 Fig 1. Logic symbol Fig 2. IE logic symbol Fig 3. Functional diagram Q D Q RD SD mna421 P Fig 4. Logic diagram for one flip-flop Product data sheet Rev ugust of 21
3 5. Pinning information 5.1 Pinning (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration for DIP14, SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVQFN Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1P 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 output 2SD 10 asynchronous set-direct input (active LOW) 2P 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) V 14 supply voltage Product data sheet Rev ugust of 21
4 6. Functional description Table 3. Function table [1] Input Output nsd nrd np nd nq nq L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don t care. Table 4. Function table [1] Input Output nsd nrd np nd nq n+1 nq n+1 H H L L H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Q n+1 = state after the next LOW-to-HIGH P transition; X = don t care. 7. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IE 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Max Unit V supply voltage V I IK input clamping current V I < 0.5 V or V I >V +0.5 V - 20 m I OK output clamping current V O < 0.5 V or V O >V +0.5V - 20 m I O output current V O = 0.5 V to (V +0.5V) - 25 m I supply current m I GND ground current m T stg storage temperature P tot total power dissipation DIP14 package [1] mw SO14, (T)SSOP14 and DHVQFN14 packages [1] mw [1] For DIP14 package: P tot derates linearly with 12 mw/k above 70. For SO14 package: P tot derates linearly with 8 mw/k above 70. For (T)SSOP14 packages: P tot derates linearly with 5.5 mw/k above 60. For DHVQFN14 packages: P tot derates linearly with 4.5 mw/k above 60. Product data sheet Rev ugust of 21
5 8. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter onditions 74H74 74HT74 Unit Min Typ Max Min Typ Max V supply voltage V V I input voltage 0 - V 0 - V V V O output voltage 0 - V 0 - V V T amb ambient temperature t/v input transition rise and fall rate V = 2.0 V ns/v V = 4.5 V ns/v V = 6.0 V ns/v 9. Static characteristics Table 7. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions T amb = 40 to +85 T amb = 40 to +125 Unit Min Typ [1] Max Min Max 74H74 V IH HIGH-level V = 2.0 V V input voltage V = 4.5 V V V = 6.0 V V V IL LOW-level V = 2.0 V V input voltage V = 4.5 V V V = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 4.0 m; V = 4.5 V V I O = 5.2 m; V = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =4.0m; V = 4.5 V V I O =5.2m; V = 6.0 V V I I input leakage V I =V or GND; current V =6.0V I supply current V I =V or GND; I O =0; V =6.0V I input 3.5 pf capacitance 74HT74 V IH HIGH-level V = 4.5 V to 5.5 V V input voltage V IL LOW-level input voltage V = 4.5 V to 5.5 V V Product data sheet Rev ugust of 21
6 Table 7. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions T amb = 40 to +85 T amb = 40 to +125 Unit Min Typ [1] Max Min Max V OH HIGH-level V I =V IH or V IL ; V =4.5V output voltage I O = 4 m V V OL LOW-level V I =V IH or V IL ; V =4.5V output voltage I O = 4.0 m V I I input leakage V I =V or GND; current V =5.5V I supply current V I =V or GND; I O =0; V =5.5V I I additional supply current input capacitance V I =V 2.1 V; other inputs at V or GND; V = 4.5 V to 5.5 V; I O =0 per input pin; nd, nrd inputs per input pin; nsd, np input [1] ll typical values are measured at T amb = pf Product data sheet Rev ugust of 21
7 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); L = 50 pf unless otherwise specified; for test circuit see Figure 9. Symbol Parameter onditions T amb = 40 to +85 T amb = 40 to +125 Unit Min Typ [1] Max Min Max 74H74 t pd t t propagation delay transition time np to nq, nq; see [2] Figure 7 V = 2.0 V ns V = 4.5 V ns V =5V; L =15pF ns V = 6.0 V ns nsd to nq, nq; see [2] Figure 8 V = 2.0 V ns V = 4.5 V ns V =5V; L =15pF ns V = 6.0 V ns nrd to nq, nq; see [2] Figure 8 V = 2.0 V ns V = 4.5 V ns V =5V; L =15pF ns V = 6.0 V ns nq, nq; see Figure 7 [3] V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns t W pulse width np HIGH or LOW; see Figure 7 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns nsd, nrd LOW; see Figure 8 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns t rec recovery nsd, nrd; see Figure 8 time V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns Product data sheet Rev ugust of 21
8 Table 8. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); L = 50 pf unless otherwise specified; for test circuit see Figure 9. Symbol Parameter onditions T amb = 40 to +85 T amb = 40 to +125 Unit Min Typ [1] Max Min Max t su set-up time nd to np; see Figure 7 t h hold time nd to np; see Figure 7 f max maximum frequency PD power dissipation capacitance 74HT74 t pd propagation delay t t transition time V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns np; see Figure 7 V = 2.0 V MHz V = 4.5 V MHz V =5V; L =15pF MHz V = 6.0 V MHz L =50pF;f=1 MHz; [4] pf V I =GNDtoV np to nq, nq; see [2] Figure 7 V = 4.5 V ns V =5V; L =15pF ns nsd to nq, nq; see [2] Figure 8 V = 4.5 V ns V =5V; L =15pF ns nrd to nq, nq; see [2] Figure 8 V = 4.5 V ns V =5V; L =15pF ns nq, nq; see Figure 7 [3] V = 4.5 V ns t W pulse width np HIGH or LOW; see Figure 7 V = 4.5 V ns nsd, nrd LOW; see Figure 8 V = 4.5 V ns t rec recovery nsd, nrd; see Figure 8 time V = 4.5 V ns t su set-up time nd to np; see Figure 7 V = 4.5 V ns Product data sheet Rev ugust of 21
9 Table 8. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); L = 50 pf unless otherwise specified; for test circuit see Figure 9. Symbol Parameter onditions T amb = 40 to +85 T amb = 40 to +125 Unit Min Typ [1] Max Min Max t h hold time nd to np; see Figure 7 V = 4.5 V ns f max maximum np; see Figure 7 frequency V = 4.5 V MHz V =5V; L =15pF MHz PD power dissipation capacitance L =50pF;f=1 MHz; V I =GNDtoV V [4] pf [1] ll typical values are measured at T amb =25. [2] t pd is the same as t PLH and t PHL. [3] t t is the same as t THL and t TLH. [4] PD is used to determine the dynamic power dissipation (P D in W). P D = PD V 2 f i N+( L V 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; L = output load capacitance in pf; V = supply voltage in V; N = number of inputs switching; ( L V 2 f o ) = sum of outputs. Product data sheet Rev ugust of 21
10 11. Waveforms Fig 7. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delay, output transition time, clock input pulse width and maximum frequency Product data sheet Rev ugust of 21
11 V I np input GND t rec V I nsd input GND V I t W t W nrd input GND t PLH t PHL V OH nq output V OL V OH nq output V OL t PHL t PLH mna423 Fig 8. Measurement points are given in Table 9. V OL and V OH are typical voltage output levels that occur with the output load. Set and reset propogation delays, pulse widths and recovery time Table 9. Measurement points Type Input Output 74H74 0.5V 0.5V 74HT V 1.3 V Product data sheet Rev ugust of 21
12 V I 90 % negative pulse GND 10 % t f t W t r V I positive pulse 10 % GND t r 90 % t W t f V G VI DUT VO RT L 001aah768 Fig 9. Test data is given in Table 10. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Test circuit for measuring switching times Table 10. Test data Type Input Load Test V I t r, t f L R L 74H74 V 6ns 15pF, 50 pf 1k t PLH, t PHL 74HT74 3V 6ns 15pF, 50 pf 1k t PLH, t PHL Product data sheet Rev ugust of 21
13 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT G04 MO-001 S Fig 10. Package outline SOT27-1 (DIP14) Product data sheet Rev ugust of 21
14 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT E06 MS Fig 11. Package outline SOT108-1 (SO14) Product data sheet Rev ugust of 21
15 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 detail X L p L θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT337-1 MO Fig 12. Package outline SOT337-1 (SSOP14) Product data sheet Rev ugust of 21
16 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT SOT402-1 MO-153 EUROPEN PROJETION ISSUE DTE Fig 13. Package outline SOT402-1 (TSSOP14) Product data sheet Rev ugust of 21
17 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 6 v M w M B y 1 y L 1 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) Eh e e1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT SOT MO EUROPEN PROJETION ISSUE DTE Fig 14. Package outline SOT762-1 (DHVQFN14) Product data sheet Rev ugust of 21
18 13. bbreviations Table 11. cronym MOS ESD HBM MM TTL bbreviations Description omplementary Metal Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status hange notice Supersedes 74H_HT74 v Product data sheet - 74H_HT74 v.3 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. 74H_HT74 v Product data sheet - 74H_HT74_NV v.2 74H_HT74_NV v Product specification - - Product data sheet Rev ugust of 21
19 15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. ustomers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). ustomers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). ustomer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IE 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the haracteristics sections of this document is not warranted. onstant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev ugust of 21
20 Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. ontact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Product data sheet Rev ugust of 21
21 17. ontents 1 General description Features and benefits Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks ontact information ontents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V ll rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 27 ugust 2012 Document identifier: 74H_HT74
74LV General description. 2. Features and benefits. 3. Ordering information. Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 3 9 September 2013 Product data sheet 1. General description The is a dual positive edge triggered, D-type flip-flop. It has individual data (nd) inputs, clock (np) inputs, set (nsd) and (nrd) inputs,
More informationTemperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;
Rev. 06 4 June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD)
More information74AHC74-Q100; 74AHCT74-Q100
74H74-Q100; 74HT74-Q100 Rev. 2 21 pril 2015 Product data sheet 1. General description The is a high-speed Si-gate MOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in
More information74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More informationThe 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
More informationThe 74LV32 provides a quad 2-input OR function.
Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
More information74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter
Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
More information74HC30-Q100; 74HCT30-Q100
Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More informationThe 74LV08 provides a quad 2-input AND function.
Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
More information74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
More information74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.
Rev. 1 20 March 2013 Product data sheet 1. General description The is a triple 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators
More information74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables
More informationDual JK flip-flop with set and reset; positive-edge trigger. The 74LVC109A is a dual positive edge triggered JK flip-flop featuring:
Rev. 5 29 November 2012 Product data sheet 1. General description The is a dual positive edge triggered JK flip-flop featuring: individual J and K inputs clock (P) inputs set (SD) and reset (RD) inputs
More information7-stage binary ripple counter
Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
More informationDual JK flip-flop with reset; negative-edge trigger
Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
More information74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.
Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
More information74HC08-Q100; 74HCT08-Q100
Rev. 1 16 July 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC08-Q100; 7 4HCT08-Q100 is a quad 2-input ND gate. Inputs include clamp diodes. This
More information74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.
Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage
More information74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
More information74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate
Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC109-Q100; 74HCT109-Q100
Rev. 1 28 September 2016 Product data sheet 1. General description The is a dual positive edge triggered JK flip-flop featuring individual nj and nk inputs. It has clock (ncp) inputs, set (nsd) and reset
More information2-input EXCLUSIVE-OR gate
Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
More information74HC32-Q100; 74HCT32-Q100
Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages
More informationTemperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
More informationHEF40175B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Quad D-type flip-flop
Rev. 8 2 November 20 Product data sheet. General description 2. Features and benefits 3. pplications The is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),
More information74LVC74A. 1. General description. 2. Features and benefits. Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 7 20 November 2012 Product data sheet 1. General description The is a dual edge triggered D-type flip-flop with individual data (nd) inputs, clock (np) inputs, set (nsd) and (nrd) inputs, and complementary
More information74HC2G08-Q100; 74HCT2G08-Q100
Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
More information74HC151-Q100; 74HCT151-Q100
Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0
More information74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger
Rev. 4 12 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
More information74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate
Quad 2-input ND gate Rev. 4 6 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input ND gate. Inputs include clamp diodes. This
More information3-to-8 line decoder, demultiplexer with address latches
Rev. 6 3 ugust 0 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard
More information74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate
Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current
More information74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
More information74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate
Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
More information74HC74-Q100; 74HCT74-Q100
Rev. 3 4 December 2015 Product data sheet 1. General description The are dual positive edge triggered D-type flip-flop with individual data (nd), clock (ncp), set (nsd) and reset (nrd) inputs, and complementary
More information2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.
74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
More information74HC1G32-Q100; 74HCT1G32-Q100
Rev. 1 8 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G32-Q100 and 74HCT1G32-Q100 are high-speed Si-gate CMOS devices. They provide a 2-input
More information74HC1G02-Q100; 74HCT1G02-Q100
Rev. 1 7 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information 74HC1G02-Q100 and 74HCT1G02-Q100 are high speed Si-gate CMOS devices. They provide a 2-input
More information74HC03-Q100; 74HCT03-Q100
Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
More information74HC153-Q100; 74HCT153-Q100
Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
More information74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More information74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter
Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting
More information74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate
Rev. 5 14 March 2018 Product data sheet 1 General description 2 Features 3 Ordering information Table 1. Ordering information Type number 74HC1G08GW 74HCT1G08GW 74HC1G08GV 74HCT1G08GV The is a single.
More informationXC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger
Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
More information74HC280; 74HCT bit odd/even parity generator/checker
Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.
More information74AHC30-Q100; 74AHCT30-Q100
Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
More information74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
More informationThe 74LVC10A provides three 3-input NAND functions.
Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
More information4-bit magnitude comparator
Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than
More informationThe 74LVC1G02 provides the single 2-input NOR function.
Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
More information74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate
Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
More information74AHC1G00; 74AHCT1G00
74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input
More information74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.
Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
More information74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer
Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
More information74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.
Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
More information74HC107-Q100; 74HCT107-Q100
Rev. 2 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
More information74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.
Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
More informationDual buffer/line driver; 3-state
Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
More information74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
More information74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
More informationHex inverter with open-drain outputs
Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
More information74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting
Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
More informationNXP 74HC_HCT1G00 2-input NAND gate datasheet
NXP 74HC_HCT1G00 datasheet http://www.manuallib.com/nxp/74hc-hct1g00-2-input-nand-gate-datasheet.html The is a single. Inputs include clamp diodes that enable the use of current limiting resistors to interface
More informationHEF4024B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. 7-stage binary counter
Rev. 7 18 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master
More information74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger
Rev. 4 8 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
More information74LVC07A-Q100. Hex buffer with open-drain outputs
Rev. October 202 Product data sheet. General description The provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
More information74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger
Rev. 4 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
More informationSingle D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.
Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
More information74HC126; 74HCT126. Quad buffer/line driver; 3-state
Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable
More information74LV General description. 2. Features. 8-bit addressable latch
Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed
More information74AHC14-Q100; 74AHCT14-Q100
Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
More information74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.
Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
More information74LVC74A-Q General description. 2. Features and benefits. Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 2 5 pril 2013 Product data sheet 1. General description The is a dual edge triggered D-type flip-flop. It has individual data (nd) inputs, clock (np) inputs, set (nsd) and (nrd) inputs, and complementary
More informationDual buffer/line driver; 3-state
Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
More information74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.
Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
More information74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting
Rev. 3 9 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable
More information74HC390; 74HCT General description. 2. Features and benefits. Dual decade ripple counter
Rev. 3 16 August 2016 Product data sheet 1. General description The is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two
More information8-bit parallel-in/serial-out shift register
Rev. 7 9 March 2016 Product data sheet 1. General description The is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (Q7 and Q7) available from the last stage. When
More information74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.
Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More informationThe 74LVC00A provides four 2-input NAND gates.
74LVC00 Quad 2-input NND gate Rev. 7 25 pril 202 Product data sheet. General description The 74LVC00 provides four 2-input NND gates. Schmitt trigger action at all inputs makes the circuit tolerant of
More informationThe 74AXP1G04 is a single inverting buffer.
Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This
More information74AHC14; 74AHCT14. Hex inverting Schmitt trigger
Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
More information74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter
Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
More information74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer
Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
More informationThe 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
74BT25 Rev. 6 3 November 20 Product data sheet. General description The 74BT25 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The
More information74HC164; 74HCT bit serial-in, parallel-out shift register
Rev. 8 19 November 2015 Product data sheet 1. General description The is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs
More information74HC541; 74HCT541. Octal buffer/line driver; 3-state
Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1
More information74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter
Rev. 3 5 October 207 Product data sheet General description 2 Features and benefits 3 Ordering information Table. Ordering information Type number Package The is a high-performance, low-power, low-voltage,
More information74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter
Rev. 5 26 November 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC3G04DP 74HCT3G04DP 74HC3G04DC 74HCT3G04DC
More information8-bit serial-in/parallel-out shift register
Rev. 4 9 December 2015 Product data sheet 1. General description The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164. The is an 8-bit edge-triggered
More information74LVC32A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad 2-input OR gate
Rev. 6 2 September 20 Product data sheet. General description 2. Features and benefits 3. Ordering information Table. Ordering information Type number Package The provides four 2-input OR gates. Inputs
More information74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger
Rev. 13 5 December 2016 Product data sheet 1. General description The is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs,
More information74HC132-Q100; 74HCT132-Q100
Rev. 3 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate
Rev. 6 26 July 2018 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package 74HC2G02DP 74HCT2G02DP 74HC2G02DC 74HCT2G02DC
More information74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 7 pril 203 Product data sheet. General description The consists of four non-inverting buffers/line drivers with 3-state outputs (ny) that are controlled by the output enable input (noe). HIGH at noe
More informationLow-power dual Schmitt trigger inverter
Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output
More information74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting
Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs
More information74LVC273-Q100. Octal D-type flip-flop with reset; positive-edge trigger
Rev. 1 16 September 2013 Product data sheet 1. General description The has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR)
More information74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger
Rev. 4 1 December 2015 Product data sheet 1. General description The is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors
More information