NEW MEXICO STATE UNIVERSITY THE KLIPSCH SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING Ph.D. QUALIFYING EXAMINATION

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1 Write your four digit code here... NEW MEXICO STATE UNIVERSITY THE KLIPSCH SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING Ph.D. QUALIFYING EXAMINATION Exam Instructions: August 16, :00 AM - 1:00 PM CLOSED BOOK a. Write the last four digits of your Banner ID number on the top of every page. b. Work six (6) problems from the three (3) areas of specialization selected at the time of registration. Do not work more than two (2) problems in any one area. A Circuits and Electronics B Communications C Computers D Control Systems E Digital Signal Processing F Electric Energy Systems G Electromagnetics H Photonics c. Check the boxes below indicating which six (6) problems you want graded. (You must work two problems from each of the three areas you specified at the time of registration.) A Circuits and Electronics. B Communications.. C Computers D Control Systems.... E Digital Signal Processing F Electric Energy Systems. G Electromagnetics... H Photonics... a b c d e f

2 A (a) Circuits and Electronics Design a fully-differential telescopic operational amplifier for a minimum gainbandwidth product GB=100MHz and a load capacitance C L =10pF. Assume following 0.18um CMOS technology parameters: kn n =170μA/V 2, Vth n =0.45V, kn p =25uA/V 2, Vth p =0.45V, λ n =λ p =0.1V -1, C ox =4.2fF/μm 2 and a capacitive load C L =10pF (kn=μc ox ). Determine all transistor sizes including those in the biasing branch. Assume a single supply voltage Vdd=1.8V The design requires to determine bias currents and W/L sizes for all transistors. Estimate for your design: a) location of the dominant pole and second (high frequency) pole taking into account only gate-source (C gs ) parasitic capacitances (do not take into account C gd, C bd and C sb parasitic capacitances) the open loop gain and the slew rate of the op-amp.

3 A (b) Circuits and Electronics Design a single-ended two stage operational amplifier for a minimum gain-bandwidth product GB=10MHz and a load capacitance C L =50pF. Assume following 0.18um CMOS technology parameters: kn n =170μA/V 2, Vth n =0.45V, kn p =25uA/V 2, Vth p =0.45V, λ n =λ p =0.1V -1, C ox =4.2fF/μm 2 (kn=μc ox ). Determine all transistor sizes including those in the biasing branch. Assume a single supply voltage Vdd=1.8V The design requires to determine bias currents, W/L size all transistors, and to determine the value of the compensation capacitance. Estimate for your design: a) location of the dominant pole and second (high frequency) pole taking into account only gate-source (C gs ) parasitic capacitances (do not take into account C gd, C bd and C sb parasitic capacitances) the open loop gain and the slew rate of the op-amp.

4 A (c) Circuits and Electronics 1) Explain what are the main design constraints faced by analog designers in modern deep submicrometer (fine line) CMOS technology 2) a) Explain the three types of random mismatch errors in analog circuits. b) What layout techniques are used to minimize the effect of each type of mismatch error? Justify your answers

5 B (a) Communications Consider the two random variables X 1 and X 2 with joint pdf { 1 f X1,X 2 (x 1, x 2 ) = 16 for x 1 < 4, 2 < x 2 < 4, 0 otherwise. Determine whether X 1 and X 2 are independent and/or orthogonal.

6 B (b) Communications Consider the following moving average process Y n = 1/2 (X n +X n 1 ) where X n is a wide sense stationary (WSS) random process (n = 0, 1, 2,... ). (a) Determine whether Y n is a WSS random process. (b) Sketch the autocorrelation sequence of Y n and determine the power spectral density S Y Y (e jω ).

7 B (c) Communications Let the lifetime of a device be an exponential random variable with a mean of 24 hours. Suppose that 20 devices are tested and their lifetimes are measured, where the measurements are assumed to be independent of each other. Determine an estimate of the probability that the sum of the lifetimes is less than 500 hours by using the Central Limit Theorem. Hint: For an exponential random variable X with pdf { λe f X (x) = λx, x 0, 0, x < 0. and parameter λ, we have E(X) = 1/λ and Var(X) = 1/λ 2. A Q-function table is attached.

9 C (a) Computers The throughputs of two networking systems are measured 7 times. The mean (m) and standard deviation (s) of the sample throughput differences are 1.05, 1.62, respectively. Can we say with 99% confidence that one system is better that the other (the confidence interval does not include zero)? t [0.995, 6] =3.707.

10 C (b) Computers Suppose we use an M/M/1 queue to model a restaurant. Customers come to a restaurant at an average rate of 4 per hour. Each customer spends an average of half an hour eating the meal (excluding waiting time). What is the average number of customers in the restaurant? What is the probability that there are more than 10 customers in the restaurant?

11 C (c) Computers Two random variables, x, y, are measured in an experiment, and their means and variances are E[x]=2, Var[x]=4, and E[y]=3, Var[y]=4, respectively. Suppose the linear regression model turns out to be: y = 0.5 x + 2. What is the covariance between the two random variables? What is the coefficient of determination (R 2 ) of the regression model?

12 C (d) Computers You are building a system around a processor with in-order execution that runs at 2.0 GHz and has a CPI of 0.7 excluding memory accesses. The only instructions that read or write data from memory are loads (20% of all instructions) and stores (5% of all instructions). The memory system for this computer is composed of a split L1 cache that imposes no penalty on hits. Both the I-cache and D-cache are direct-mapped and hold 32KB each. The I-cache has a 3% miss rate and 32-byte blocks; the D-cache is write through with a 5% miss rate and 16-byte blocks. There is a write buffer on the D-cache that eliminates stalls for 95% of all writes. The 512KB write-back, unified L2 cache has 64-byte blocks and an access time of 15ns. It is connected to the L1 cache by a 128-bit data bus that runs at 266MHz and can transfer one 128-bit word per bus cycle. Of all memory references sent to the L2 cache in this system, 82% are satisfied without going to main memory. Also, 50% of all blocks replaced are dirty. The 128-bit-wide main memory has an access latency of 60ns, after which any number of bus words may be transferred at the rate of one per cycle on the 128-bit-wide 166MHz main memory bus. a. What is the average memory access time for instruction accesses? b. What is the average memory access time for data writes? c. What is the overall CPI, including memory accesses?

13 C (e) Computers Consider a dynamically scheduled, speculative, microprocessor with one load/store unit, one floating-point add unit, one integer add unit, and one floating-point multiplication unit. Assume that the arithmetic units are pipelined and that each functional unit has two reservation stations. Further assume that the instruction buffer (issue queue) holds at most eight instructions and that eight instructions can be fetched and issued simultaneously. If you feel that you must assume instruction execution latencies, state your assumptions. a. Give an instruction sequence that causes a stall due to a full instruction buffer. Briefly explain why your scenario causes this type of stall. b. Give an instruction sequence that causes a functional unit to stall, i.e., that causes a functional unit (at least one segment of its pipeline) to be idle. c. Assume that a branch is mispredicted. Explain when this is noticed and what happens as a result of this situation.

14 C (f) Computers Consider caches. a. Do ALL caches require that each cache line have a dirty bit? Why or why not? b. Do ALL caches require that on a write miss the missed cache line be fetched from the next level of the memory hierarchy? Why or why not? c. Does enlarging the cache ALWAYS give an application a better hit rate? Why or why not?

15 D (a) Control Systems If (A,C) is detectable, and there exists P > 0 such that A T P + PA PBB T P + C T C + 3P = 0 show that the matrix A + BK, K = B T P has eigenvalues with real parts less than 1.

16 D (b) Control Systems For the discrete-time system xt+1 ( )= x u, x()= find a control sequence, ut (), t = 0,1,2,..., to drive the state from the initial state to the final state x()= and then maintain that state for all t 2.

17 D (c) Control Systems Given the scalar system x Ý = 2x u + w, y = 2x with a disturbance given by wt ()= M + N cos( 2t +12 )u s t 7 ( ) where M, N are unknown values with M [.5,5],N [ 2,3]. It is desired that the system track the sinusoid rt ( ) = 1+ 2sin( 2t) and settle within 1 second. Design an output-feedback controller to make this happen.

18 E (a) Digital Signal Processing Consider a digital filter whose transfer function has a single pole at z = 1/2, a single pole at z = 0, and two zeros at z = 1. The transfer function includes a scale factor so that the DC response is 0 db. (a) Sketch the pole-zero pattern of the filter. (b) Determine the transfer function H(z). factor. Be sure to include (and determine) the scale (c) Assume the filter is stable and determine the impulse response h[n]. (d) Sketch the magnitude response of the filter H(e jω ) vs. ω for 0 ω π.

19 E (b) Digital Signal Processing (a) Assume that a binary word represents the amplitude of a signal. For a signed integer binary word length of b + 1 bits (one sign bit and b magnitude bits), determine the dynamic range in decibels (db) defined by ( ) largest possible word value dynamic range db = 20 log 10. smallest possible word value Your expression should only be a function of b. (b) Show that your expression in (a) can be approximated as dynamic range db 20 log 10 ( 2 b ) 6.02 b (db) (c) Use the simplified result in (b) to explain why a 16 bit analog-to-digital (A/D) converter might be preferred over 8 bit A/D converter for high-fidelity audio.

20 E (c) Digital Signal Processing PROBLEM DSP: Linear Phase filters a) (3 pts) Define the frequency response of a generic linear phase filter. Why is linear phase an important property to have in a filter? Can infinite impulse response filters ever be linear phase under any circumstances? Explain. b) (3 pts) To achieve linear phase, a filter must have either a symmetric or antisymmetric impulse response. Assume that the impulse response of the filter is given by h[n] where 0! n! N. Write the symmetry and anti-symmetry equations in terms of h[n] for a generic linear phase system. c) (2 pts) Derive the z-transform domain relation that must be satisfied for any linear phase system. d) (2 pts) Given that h[n] is real and linear phase and that the corresponding z-transform H(z) has zeros at and (1.25 j2). What other zeros must H(z) have? Note: this answer can be calculated from the relation of c) if you have not memorized it.

21 F (a) Electric Energy Systems X 1 2 Generator Transformer 1 MVA 2 MVA 60 Hz, 4160 V 4160 Delta 480 Yg Wye grounded Xo=X1=X2=0.1pu Xd =0.2, X2=0.18,Xo=.1pu Sketch the sequence Thevenin networks as seen from bus 2 Tell me how these networks would be connected for the following faults Three phase Single line to ground Line-line-ground through fault impedance For a single line-ground fault at X Find the line currents and line to ground voltages at the terminals of the generator

22 F (b) Electric Energy Systems Figure 1 shows a single-line diagram of a three-phase, 60-Hz synchronous generator, connected through a transformer and parallel transmission lines to an infinite bus. All reactances are given in per-unit on a common system base. a. If the infinite bus receives 1 per unit real power at 0.9 p.f. lagging, determine the equation for the electrical power delivered by the generator versus its power angle δ. b. The generator is initially operating in the stead-state condition when a permanent threephase-to-ground bolted short circuit fault occurs at point F. The fault is then cleared by opening circuit breakers B13 and B22 in 5 cycles. These circuit breakers then remain open. Is the system stable with respect to the fault? 1 2 G Xtr=0.2 B12 X12=0.2 3 B21 Xd =0.2 B11 F X13=0.2 X23=0.2 B13 B22 Figure 1: Single-line diagram for transient stability analysis Vbus=1.0

23 F (c) Electric Energy Systems A 440 V, 500 kw, constant impedance, three-phase, Wye-Grounded, balanced load has a rated power factor of 0.8 lagging, and is being fed by a four-wire system. The system line voltages are as follows: V AB 0 = V, V = BC 0 V Find out the line currents in all three lines and the current flowing through the neutral. Clearly mention any assumption you have to make to solve this problem.

24 G (a) Electromagnetics

25 G (b) Electromagnetics

26 G (c) Electromagnetics

27 H (a) Photonics The figure below shows a hemispherical receiving surface of radius r. A small planar Lambertian source of area A and radiance L is placed as shown (at the center of the sphere that contains the hemisphere). The angle θ z shown in the figure is known as the zenith angle. Receiver θ z r Source Area A Radiance L (a) What is the irradiance at a point on the receiver that is straight up from the source (where θ z = 0)? (b) At what zenith angle will the irradiance at the receiver be half that for a zenith angle of 0 degrees? (c) What is the total flux (power) that is received by the hemisphere?

28 H (b) Photonics A simple imaging system is observing an object (obj) at a distance of 100 mm from a lens. In addition to the object, there is background radiation (bkg) as shown below. The lens has a focal length of 50 mm and a radius of 6 mm. L bkg = 0.1 mw/cm 2 -sr 100 mm L obj = 1 mw/cm 2 -sr A obj = 1 cm 2 6 mm f = 50 mm Detector 1 mm x 1 mm (a) At what distance from the lens is the image formed? The detector will be placed at this position. (b) What is the working F/# (F-number) of the system (coming into the detector)? (c) What is the angular field-of-view of the system? (d) What is the irradiance at the detector due to the background? What is the flux at the detector due to the background? (e) What is the irradiance at the detector due to the object? What is the flux at the detector due to the object?

29 H (c) Photonics In terms of the following functions: U g (x,y) = ideal geometric optics coherent image field I g (x,y) = ideal geometric optics incoherent image intensity h(x,y) = coherent impulse response of the imaging system Write an expression for each of the following: a) the coherent image b) the incoherent image c) the coherent (amplitude) transfer function d) the incoherent transfer function e) the spatial frequency spectrum of the coherent image f) the spatial frequency spectrum of the incoherent image

30 H (d) Photonics An ideal (smooth) square object (side length 2w) of uniform reflectance is illuminated by a unit amplitude coherent optical beam. At a distance s from the object center is a tiny reflector. The reflector is also illuminated by the beam so the reflected light acts like it came from a point source. 2w Point source s (a) Write an expression that describes the object and point source as shown in the figure. Place the point source at the axis of an x-y coordinate system. (b) Derive an expression for the Fraunhofer field for the light that reflects from the combined object and point source. (c) Derive an expression for the Fraunhofer intensity of the object and point source.

31 H (e) Photonics Consider the ring optical cavity shown in the following diagram. (a) Find the formula for the minimum spot size for a Gaussian beam and identify the location in the cavity where the beam has minimum spot size. (b) Find the stability condition of this ring cavity (c) Compute the spot size at the lens if d=10cm, f=20cm, and λ 0 =6328Å.

32 H (f) Photonics An optical system that alters the polarization of a plane wave can be described by the Jones matrix. The wave retarders are represented by the following matrix, 1 0 2π ΔnL T wave retarder =, where Γ =. 0 exp( ) jγ λ Ax Find the Jones vectors, J = Ay (a) (b) y Input 45 0 x Output Half Wave Retarder

NEW MEXICO STATE UNIVERSITY THE KLIPSCH SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING Ph.D. QUALIFYING EXAMINATION

Write your four digit code here... NEW MEXICO STATE UNIVERSITY THE KLIPSCH SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING Ph.D. QUALIFYING EXAMINATION Exam Instructions: January 10, 011 9:00 AM - 1:00 PM