Energy-Efficient Signal Processing via Algorithmic Noise-Tolerance

Transcription

1 Energy-Efficient Signal Prcessing via Algrithmic Nise-Tlerance Rajamhana Hegde and Naresh R. Shanbhag ECE epartment/crdinated Science Labratry University f Illinis, Urbana, IL [rhegde, shanbhag]@uivlsi.csl.uiuc.edu Abstract In this paper, we prpse a framewrk fr lw-energy digital signal prcessing (SP) where the supply vltage is scaled beynd the critical vltage required t match the critical path delay t the thrughput. This deliberate intrductin f input-dependent errrs leads t degradatin in the algrithmic perfrmance, which is cmpensated fr via algrithmic nise-tlerance (ANT) schemes. The resulting setup that cmprises f the SP architecture perating at sub-critical vltage and the errr cntrl scheme is referred t as sft SP. It is shwn that technlgy scaling renders the prpsed scheme mre effective as the delay penalty suffered due t vltage scaling reduces due t shrt channel effects. The effectiveness f the prpsed scheme is als enhanced when arithmetic units with a higher delay-imbalance are emplyed. A predictin based errr-cntrl scheme is prpsed t enhance the perfrmance f the filtering algrithm in presence f errrs due t sft cmputatins. Fr a frequency selective filter, it is shwn that the prpsed scheme prvides 6%,81% reductin in energy dissipatin fr filter bandwidths up t :5 (where 2 crrespnds t the sampling frequency f s) ver that achieved via cnventinal vltage scaling, with a maximum f :5dB degradatin in the utput signal-t-nise rati (SNR ). It is als shwn that the prpsed algrithmic nise-tlerance schemes can be used t imprve the perfrmance f SP algrithms in presence f bit-errr rates f upt 1,3 due t deep submicrn (SM) nise. 1 Intrductin Energy-efficient VLSI circuit design is f great interest given the prliferatin f mbile cmputing devices, the need t reduce packaging cst, the desire t imprve reliability, and extend peratinal life f VLSI systems. Scaling f CMOS technlgy has made pssible substantial reductin in energy dissipatin and hence has lead t the prliferatin f lw cst VLSI systems with increasingly high levels f integratin. At a given technlgy, reductin in energy dissipatin has als been made pssible due t energy-efficient design techniques at all pssible levels f design hierarchy. Schemes at the lwer levels f the design prcess such as the lgic [1] and circuit levels [2] are usually applicatin independent. At the algrithmic and architectural levels, features that are specific t a class f applicatins are explited t develp applicatin specific energy reductin techniques [3, 4]. Vltage scaling [3] is an effective means f achieving reductin in energy dissipatin as a reductin in supply vltage by a factr K, reduces the dminant capacitive This wrk was supprted by NSF CAREER award MIP cmpnent f energy dissipatin by a factr K 2 [5]. Hwever, the extent f vltage scaling [5] is limited by the critical path delay f the architecture and the thrughput requirements f the applicatin. A typical SP system is designed in such a way that the critical path delay [1] T cp (defined as the wrst case delay ver all pssible input patterns), shuld be less than r equal t the sample perid T s, i.e., T cp T s. Hence, given T s, the SP system is designed such that, at the rated supply vltage V dd,thedelay cnditin, T cp T s, is satisfied. The relatinship between V dd and circuit delay d is given by [1], C LV dd d = (V dd, V ; (1) t) where C L is the lad capacitance, is the velcity saturatin index, is the gate transcnductance, and V t is the device threshld vltage. We refer t the vltage at which T cp = T s as the critical supply vltage V dd,crit f a given architecture. Nte that vilating the delay cnditin by reducing V dd beynd V dd,crit, i.e. setting V dd = K vv dd,crit ; (2) where < K v < 1, leads t errneus utput when the critical path is excited. In cnventinal vltage scaling, V dd,crit is seen as a lwer bund n the supply vltage fr a given architecture and thrughput. Reductin in V dd (withut vilating the delay cnditin) can be achieved by reducing the critical path delay f the VLSI implementatin via architectural transfrmatins such as pipelining and parallel prcessing [5]. We prpse perating the SP architecture at vltages lwer than V dd,crit. Such peratin leads t errrs in the system utput when the critical paths and ther lnger paths are excited. Hence, the resulting cmputatins are referred t as sft cmputatins. We prpse algrithmic nise-tlerance (ANT) t cmpensate fr degradatin in the system utput due t errrs frm sft cmputatins. ANT refers t algrithmic errr-cntrl schemes derived frm the knwledge f the system transfer functin, input and utput signal statistics. The resulting framewrk is illustrated in Figure 1. The setup that cmprises f the SP architecture perating at a sub-critical supply vltage (lwer than V dd,crit ) Sft Cmputatins System errrs SM Nise Algrithmic Nise- Tlerance (ANT) Nise-Tlerant Sft SP SP Figure 1: The prpsed sft and nise tlerant SP framewrk.

2 and the lw-cmplexity errr-cntrl scheme is referred t as sft SP. The gal f sft SP is t achieve substantial energy-savings while meeting the algrithmic perfrmance specificatins. Nte that the effectiveness f the prpsed scheme depends n the errr frequency. We shw that the phenmenn f velcity saturatin in shrt-channel devices (feature size is less than :5m) favurs lw-pwer peratin via sft SP. It is als shwn that the ANT schemes can be emplyed t restre degradatin in algrithmic perfrmance due t deep submicrn nise (SM) nise [7] induced errrs. Wereferttheresultingsetupas nise-tlerant SP as shwn in Figure 1. The rest f this paper is rganized as fllws. In sectin 2, the prpsed ntin f sft SP is intrduced with a mtivatinal example. In sectin 3, a lw cmplexity predictin-based algrithm is develped t detect and mitigate the effect f sft errrs n the perfrmance f the digital filtering algrithm. In sectin 4, we study the energy savings due t the prpsed apprach in the cntext f frequency selective filtering. We als study the perfrmance f algrithmic nise-tlerance schemes in presence f randm errrs in the system utput due t SM nise. Finally, in sectins 5 cnclusins and scpe fr future wrk n this tpic are presented. 2 Energy Savings via Sft SP In this sectin, we illustrate the relatinship between energy savings due t the prpsed apprach and the resulting degradatin in perfrmance due t errrs in the system utput. It is shwn that errr frequency due t sft cmputatins is a functin f the path delay distributin f the SP blck architecture and a new multiplyaccumulate (MAC) architecture that imprves the effectiveness f the prpsed scheme fr the filtering algrithm is presented. 2.1 Mtivatinal Example Cnsider the 5-bit adder shwn in Figure 2(a), where the input perands are 11 and 111. Assuming that T FA =3ns, the critical path delay f this adder is 15ns. Nte that the time taken t cmpute the utput crrespnding t the tw perands is als 15ns. LetT s =15ns. If the supply vltage is nw reduced such that T FA = 5ns, the adder utput at the end f the sample perid will be 1 as shwn in Figure 2(a). Hence, the numerical value f the adder utput will be 8 instead f 16. If the inputs d nt excite the lnger paths (e.g. 1 and 1), then the adder prvides crrect utputs. In the absence f errrs, the algrithmic perfrmance f a filter transfer functin H(z) (shwn in Figure 2(b)) is measured in terms f the utput SNR given by SNR = 2 lg( s= w); (3) (a) crrect /p: 1 with reduced vltage: 1 H(z) H(z) with reduced vltage (b) y(n) = s(n) + w(n) y(n) = s(n) + w(n) + err(n) Figure 2: Effect f errrs n perfrmance f SP algrithms errrs frm t sft cmputatins ccur in the mst significant bits (MSBs) due t lnger path delays. This leads us t cnclude that the errr-cntrl schemes shuld be effective in capturing MSB errrs in rder t result in substantial energy savings with marginal perfrmance degradatin. 2.2 Path elay istributin f Adders In this subsectin, we study the frequency f excitatin f critical paths in the cntext f a ripple-carry adder. Fr an N-bit ripplecarry adder, the ttal number f pssible input cmbinatins is 2 N 2 N =4 N :Of these, sme cmbinatins such as x = 1111 and y = 1111 (N is assumed t be 8) areevaluatedinjust T FA time units. Other cmbinatins such as x = , y = 1, andx = , y = excite the critical path requiring 8T FA time units. The path delay histgram f an 8-bit tw s cmplement ripple-carry adder where the input perands x and y are generated randmly with Gaussian distributin(shwn in Figures 3(i) and (ii)), is shwn in Figure 3(iii). Als shwn in Figure 3(iii), is the histgram f path delays fr an unsigned 8-bit adder fr the same perands. A bias f +128 is added t bth the perands t make them unsigned psitive numbers. It can be seen that, fr unsigned numbers, the fractin f inputs that excite the critical paths is significantly less. In this paper, we prpse a new MAC architecture, that emplys an unsigned array multiplier t imprve the effectiveness f the prpsed sft SP scheme. ANT-based system. 2.3 MAC Architecture fr sft SP The utput y(n) f an N-tap filter is given by y(n) = N,1 X k= h(k)x(n, k); (7) where h(k) dentes the k th cefficient f the filter, x(n, k) dentes the input at n, k th instant, and N is the rder f the filter. where 2 s and 2 w are the signal and nise variance, respectively. The utput in this case can be expressed as y(n) =s(n)+w(n); (4) where s(n) is the desired signal and w(n) is the signal nise. The filter utput in presence f errrs due t sft cmputatins can be expressed as ^y(n) =y(n)+err(n); (5) where err(n) is the errr intrduced in the utput sample at the n th instant. The utput SNR using sft cmputatins is given by x1% f input samples x1% f input samples (i): x quantized t 8 bits x1% f input samples s cmplement unsigned ^ SNR = 2 lg( s= w+c); (6) (ii): x quantized t 8 bits (iii): path delay in multiples f T FA where w+c is the ttal nise pwer. Hence, errrs in the system utput lead t degradatin in perfrmance in terms f SNR.The Figure 3: Path delay histgrams f 8-bit ripple carry adder

3 x(n-k) h(k) µ (k) 2 (N h + N x - 1) Figure 4: prpsed MAC architecture Σ µ (k) 2 (N h + N x - 1) Typically, tw s cmplement representatin is used in representing the filter cefficients and the signal. Hwever, as shwn earlier, unsigned magnitude representatin ffers the advantage that a smaller fractin f inputs excite the critical path. Nte that signedmagnitude representatin has been emplyed in the past [3, 12], t reduce transitin activity in crrelatrs fr wireless applicatins. The prpsed MAC structure (refered t as the sign-magnitude architecture (SMA)), shwn in Figure 4, emplys signed magnitude representatin and unsigned multiplier and adders. In this structure, the magnitude and sign f the prduct h(k)x(n, k) are cmputed separately. If the prduct is negative, a bias term is added t make it psitive befre it is applied t the adder. Hence, we get N,1 X, y (N (n) = h(k)x(n, k) +(k)2 h +N x,1) (8) k= where, (k) = if h(k)x(n, k) is +ve, = 1 if h(k)x(n, k) is -ve, and N h and N x are the number f bits in the representatin f h(k) and. An additinal adder (perating at sample rate) is emplyed t subtract the bias term PN,1 k= (k)2(n h +Nx,1) frm y (n) t btain y(n). Nte that the multiplier in the SMA is smaller than that in the traditinal structure due t signed magnitude representatin. This leads t additinal reductin in energy dissipatin f the verall structure that cmpensates fr the verhead f the additinal adder. 3 Algrithmic Nise-Tlerance fr igital Filtering In this sectin, we present an algrithmic errr-cntrl scheme fr digital filtering in rder t reduce the impact f errrs n the algrithmic perfrmance. The prpsed scheme is shwn in Figure 5, where the filter utput is fed t an errr-cntrl blck that detects errrs in the filter utput and reduces their effect n system perfrmance. The utput f the errr cntrl blck is dented by y (n), and the gal f this apprach is t btain y (n) y(n), where y(n) dentes the filter utput in absence f errrs. The term nisy filter represents a sft implementatin f the digital filter r in presence f ther nise inducing phenmena such as deep submicrn nise. We assume that the errr-cntrl blck has been designed Nise-tlerant Filter Nisy Filter y(n) errr cntrl Figure 5: The prpsed algrithmic nise-tlerant digital filtering scheme t be errr-free. Fr sft SP, as it will be shwn later, this assumptin hlds as the critical path delay f the errr-cntrl blck will be small cmpared t that f the filter. Similarly, in case f SM nise, a nise eliminatin design strategy [7] can be adpted t btain an errr-free errr cntrl blck. As the cmplexity f the errr-cntrl blck is much lesser than that f the filter, the design verhead will be significantly smaller. 3.1 A ierence-based Errr-Cntrl Scheme In this subsectin, we present a simple errr-cntrl scheme suitable fr lwpass digital filters with a relatively narrw passband. This scheme can be shwn t be a special case f the mre general predictive errr-cntrl scheme presented in sectin 3:2. Lety(n) dente the filter utput when the filter errr-free and is given by (7). The difference in cnsecutive samples f the filter utput is given by, y d (n) =y(n),y(n,1): (9) Let ^y(n) dente the filter utput when the filter is perating under reduced vltage, with ^y(n) =y(n)+y err(n); (1) where y err(n) dentes the the errr in the filter utput due t sft cmputatins. Nte that y err(n) is nn-zer nly when the input pattern is such that lnger paths in the filter implementatin are excited. Assuming that the past input is niseless, i.e, y err(n, 1) =, wehave, ^y d (n) =y d (n)+y err(n); (11) where ^y d (n) is the difference in the filter utput in presence f errrs. Frm Schwartz inequality and (11), it can be easily shwn that, j ^y d (n)j jy err(n)j,jy d (n)j: (12) Assuming that jy d (n)j < E th fr all n, wheree th is a suitably chsen difference threshld as described later, the fllwing differencebased errr-cntrl scheme (shwn in Figure 6) is derived frm (12): cmpute ^y d (n) =^y(n),^y(n,1) (frm (9)). Errr detectin: if j ^y d (n)j E th ; an errr is declared. Errr crrectin: if an errr is declared, y (n) =^y(n,1): else y (n) =^y(n): If an errr is detected, the past utput sample is taken t be the estimate fr the current utput sample. The perfrmance f the abve algrithm is based n the chice f E th, the relative magnitudes f y d (n) and y err(n), and the frequency with which errrs ccur. The value f E th is chsen such that j^y(n)j <E th when y err(n) = Nise-tlerant Filter Nisy Filter y(n) ^ ECISION BLOCK errr cntrl Figure 6: ifference-based ANT scheme fr LPF.

4 NOISY FILTER decisin blck y(n) ^ y(n) ^p h (1) p NOISE-TOLERANT FILTER h p (N p ) PREICTOR Figure 7: Predictin-based algrithmic nise-tlerance. (in absence f errr) and j^y(n)j >E th when y err(n) 6= (in presence f errr). In this paper, we have chsen E th =5 d,where 2 d is the variance f y d (n). As the variance in y d (n) increases with bandwidth, the effectiveness f the abve apprach in perfrming errr detectin deterirates. Hence fr larger bandwidths, a mre sphisticated predictin-based scheme presented in sectin 3.2 is emplyed. 3.2 Predictin-based Errr-Cntrl A general predictin-based scheme that can handle different input crrelatin structures is shwn in Figure 7. In this scheme, a lw cmplexity linear frward predictr is emplyed t get an estimate f the current sample f the filter utput based n its past samples. In the absence f errrs in the filter utput, the predictin errr is usually small. A large errr in the filter utput due t excessive vltage reductin leads t an increase in the magnitude f predictin errr and this phenmenn is emplyed t detect errrs in the filter utput. Let y p(n) dente the utput f an N p-tap predictr when the filter is niseless, i.e., y p(n) = N X p k=1 h p(k)y(n, k); (13) where h p(k) dentes the ptimum predictr cefficients [13] that minimize the mean squared value (MSE) <e 2 p(n)>f the predictin errr e p(n),givenby, e p(n) =y(n),y p(n): (14) The minimum mean square errr (MMSE) depends n the autcrrelatin functin f y(n) and the rder f the predictr. Let ^y(n), ^y p(n), and ^e p(n) dente the filter utput, the predictr utput, and the predictin errr, respectively, in presence f errrs due t sft cmputatins. efine ^y(n) = y(n) +y err(n), wherey err(n) dentes the errr in y(n) due t vltage reductin. Frm (1) and (14), we get ^e p(n) =y err(n) +e p(n): (15) Assuming that n mre errrs ccur in the next N p utput samples, we can shw that, ^e p(n + m) =,h p(m)y err(n) +e p(n+m); (16) fr m = 1; 2; ;N p: Equatins (15) and (16) can nw be expressed in vectr frm as ^e p(n) =y err(n)h + e p(n) (17) where ^e p(n) =[^e p(n) ^e p(n+1) ^e p(n+n p)] T ; h =[1,h p(1), h p(2),h p(n p)] T ; and e p(n) =[e p(n) e p(n+1) e p(n+n p)] T : w s(n) LPF, BPF, r HPF Signal Generatin Filter (SGF) s(n) w(n) s (n) c SOFT SP Signal Prcessing Filter (SPF) LPF, BPF r HPF SOFT FILTER PREICTOR ECISION BLOCK Figure 8: Simulatin setup t evaluate the prpsed scheme. 3.3 Errr-Cntrl Algrithm The fllwing algrithm, derived frm (17) is emplyed fr errr cntrl: Errr detectin: If jh T ^e p(n)j >E th, then an errr is declared. Errr crrectin: If an errr is declared, then y (n) =y p(n), else y (n) =^y(n). In this case, we set E th = ep, whereep 2 is the variance f the predictin errr with a niseless digital filter. Hence, if an errr is detected, the predictr utput based n the past crrect samples is declared as the system utput. The perfrmance f the predictinbased errr cntrl algrithm depends upn the chice f E th and the frequency with which errrs ccur. As, the magnitude f the errr in filter utput jy err(n)j will be several rders larger than jh T e p(n)j, ify err(n) 6=, jh T ^e p(n)j will be large. It can be seen frm (17) that, when y err(n) 6=,thejjhjj 2 term amplifies the effect f y err(n) n the prduct h T ^e p(n). This enables the predictin-based algrithm t detect errrs f smaller magnitude and hence we chse a smaller decisin threshld ep. The effectiveness f the errr detectin and crrectin scheme described abve depends n the fllwing assumptins: 1. The magnitude f y err(n) is relatively large. Errrs with higher magnitudes lead t a higher value f jh T ^e p(n)j and the errr is easily detected. 2. The prbability that ^y(n) 6= y(n) is small enugh such that the frequency f the errrs in the filter utput is less that 1=2N p. The perfrmance f the abve scheme deterirates when multiple errrs ccur at the filter utput in the span f 2N p samples. The errrs due t sft cmputatins ccur in the MSBs and hence are f large magnitude. This validates assumptin 1. Assumptin 2, limits the factr by which vltage can be reduced as the set f errr inducing input cmbinatins grws with increase in delay due t vltage reductin. The experimental results presented in this paper demnstrate that substantial energy savings can be btained befre assumptin 2 is vilated. In case f sft cmputatins, nte that the errrs ccur in the MSBs and hence are f higher magnitude. In such a case, the prpsed errr-cntrl algrithm can be relaxed further t reduce the cmplexity f the errr-cntrl circuitry. 4 Experimental Results The setup used t measure the perfrmance f the prpsed scheme in which the filtering algrithm is emplyed in the frequency selective filtering cnfiguratin is shwn in Figure 8. A lwpass, bandpass r a highpass filter (LPF, BPF r HPF), dented as the signal generatin filter (SGF), is used t generate a bandlimited signal s(n) frm a wideband input w s(n). The signal s(n) is the crrupted by wideband nise w(n), i.e., the signal s c(n) is btained

5 as s c(n) =s(n)+w(n),wheres(n) is the utput f the SGF fr a wideband input w s(n). Ass(n) is bandlimited, the SNR can be imprved by passing s c(n) thugh a frequency selective filter with bandwidth! b. This filter is dented as the signal prcessing filter (SPF) in Figure 8, and it supresses the ut-f-band cmpnents f the nise signal w(n). We emply the prpsed sft SP implementatin f the filtering algrithm t perfrm frequency selective filtering n s c(n) as shwn in Figure 8. Nte that this setup simulates several practical scenaris fr signal prcessing where the task is t extract a bandlimited signal embedded in wideband nise. We emply a flded implementatin fr the signal prcessing filter cntaining N taps where all the taps are mapped n t a single MAC. The cefficient and the input data precisins are chsen t be 1 and 8 bits, respectively. We have chsen N =29fr all the experimental results presented in this paper as it was sufficient in prviding the required SNR imprvement fr several bandwidths cnsidered in this paper. 4.1 Perfrmance Measures The perfrmance f the prpsed scheme is measured via tw experiments. In the first experiment, we study the perfrmance in restring the SNR degradatin due t sft cmputatins. We als measure the resulting savings in energy dissipatin, present the energy-perfrmance relatinship, and cmpare it t that f the cnventinal TCA. In the secnd experiment, we measure the perfrmance f the prpsed scheme in presence f SM nise by intrducing errrs randmly at the SPF utput. The SNR at the utput f the filter in presence f errrs is given by, SNR ^ = 2 lg 1 s n + c ; (18) where 2 s is the variance f the signal cmpnent (due t s(n)), 2 n is the variance f the nise cmpnent (due t w(n)),and 2 c is the variance f errr in the utput due sft cmputatins r SM nise (i.e., <y err(n) 2 >). In rder t estimate the energy savings btained via vltage reductin as prpsed, the energy dissipatin values are btained by using ME [14], a gate level energy estimatr. Nte that the simulatr uses a real delay mdel and hence takes int accunt the glitching activity in the circuit. An extended simulatin fr 2 input vectrs is perfrmed fr the arithmatic blcks emplyed in bth the traditinal and the prpsed schemes t btain energy estimates. The gate library parameters cmprised f delay and capacitance values that are typical f a :5m CMOS technlgy. When the supply vltage is scaled, the V dd values crrespnding t a given path-delay are btained by slving (1) with = 2: (n velcity saturatin) and fr =1:5and 1:2 (with velcity saturatin). The reductin in energy dissipatin is characterized by energy savings (ES), defined as ES = E riginal, E prpsed E riginal 1%; (19) where E riginal is the energy dissipatin with cnventinal vltage scaling (i.e., with V dd = V dd,crit ), and E prpsed is the energy dissipatin with the prpsed scheme. 4.2 Eect f velcity saturatin n sft SP The plt f K v vs. SNR fr a lwpass filter emplying the prpsed SMA, with filter bandwidth! b =:2fr several values f is shwn in Figure 9(a). Nte that smaller enables a smaller value f K v, the vltage scaling factr. With =1:2, V dd scalingbyafactrf:72 is pssible with a degradatin f less than :5dB in SNR using ANT. The difference-based ANT scheme is utput SNR fr ω b =.2π with ANT withut ANT α = 2. α = 1.5 α = K v Figure 9: K v vs. SNR fr several values f fr the prpsed SMA emplyed here as the filter bandwidth is small. It can be seen that reductin in due t velcity saturatin enables higher reductin in K v and hence higher energy savings. 4.3 Energy-Perfrmance Characteristics % energy savings SMA withut ANT SMA with ANT SMA with ANT (cmpared with TCA) TCA with ANT utput SNR (in db) Figure 1: Perfrmance vs. Energy Savings ( =1:2) with filter bandwidth! b =:2fr the difference-based ANT scheme. The plt f SNR vs. energy savings f the prpsed sft SP scheme fr! b =:2emplying the difference-based ANT scheme is shwn in Figure 1. Fr cmparisn purpses, we chse a cnventinal TCA architecture perating at its V dd,crit as a reference. Nte that this is the best that traditinal vltage scaling achieves. The prpsed SMA architecture with ANT leads t 8% energy savings ver the cnventinal TCA. The energy-savings via sft SP emplying the TCA is 34%, whereas the same with the prpsed SMA is 51% when the perfrmance degradatin allwed is less than :5dB. The prpsed architecture leads t savings ver cnventinal TCA due t the fllwing reasns: 1.) the critical path delay f the prpsed architecture is reduced due t the unsigned multiplier, and 2.) the transitin activity f the prpsed architecture is reduced due t the emplyment f the signed magnitude representatin in the multipliers. Nte that the reduced transitin activity in the MSBs allws fr higher vltage scaling fr a given errr frequency. Figure 11 shws the energy-perfrmance relatinship fr! b = :5. In this case, the pssible energy savings ver the cnven- desired utput SNR = 25dB

6 % energy savings SMA withut ANT SMA with ANT SMA with ANT (cmpared t TCA) utput SNR (in db) Figure 11: Perfrmance-Energy relatinship (with =1:2) fthe predictin-based ANT scheme with N p = 3 fr filter bandwidth! b =:5. SNR (in db) < REGION OF EFFECTIVE ANT F > withut nise tlerance with nise tlerance SNR withut SM nise (21dB) SNR desired (19dB) desired utput SNR = 21dB lg 1 (p err ) Figure 12: Perfrmance f the prpsed ANT scheme fr filter bandwidth! b =:4with predictr tap-length, N p =4. tinal TCA perating at V dd,crit is 78% with a perfrmance lss f abut :5dB: Nte that the energy savings cmpared t the prpsed architecture perating at V dd,crit is abut 58% and the crrespnding savings fr filter bandwidth = :3 is 64%. The drp in energy savings fr higher bandwidths is due t the reductin in crrelatin f the filter utput which requires a higher predictr length fr a given errr-cntrl perfrmance. 4.4 Perfrmance f ANT in the Presence f SM Nise In rder t experimentally verify the effectiveness f the prpsed apprach in presence f SM nise, errrs are intrduced at the system level by flipping the utput bits f the digital filter independently, with a fixed prbability dented by p err. Nte that mre accurate perfrmance results require detailed SM nise mdels fr the arithmetic units emplyed in the digital filter which are currently nt available. The perfrmance f the prpsed algrithm fr a digital filter with bandwidth! b =:4and 48 taps is shwn in Figure 12(a). As expected, withut nise-tlerance, the degradatin in perfrmance increases with increase in p err as expected. Als, the prpsed scheme prvides up t 1dB imprvement in perfrmance. The SNR with ANT stays almst cnstant abve 19dB till p err =1,3 and then reduces sharply. In this range, the prbability f errr is lw enugh that the assumptin f infrequent errrs (assumptin 2 in sectin 3.3) is satisfied. 5 Cnclusins & future wrk In this paper, we have prpsed sft SP fr reductin in energy dissipatin. It was shwn that the effectiveness f the prpsed apprach depends n tw key features: 1) the path delay distributin f the architecture emplyed and 2) the effectiveness f the errrcntrl schemes in restring perfrmance degradatin. Past wrk in lw-pwer arithmetic unit design fcuses n delay balancing t reduce glitch pwer. Hwever, this wrk suggests that emplying delay imbalanced arithmetic units in a sft SP framewrk leads t higher energy savings with marginal degradatin in perfrmance. Future wrk n this tpic will invlve explring varius arithmetic units and SP architectures fr their effectiveness in sft SP scenari and develping errr-cntrl schemes fr widely used SP algrithms. References [1] S. Iman and M. Pedram, An apprach fr multi-level lgic ptimizatin targeting lw pwer, IEEE Trans. n Cmputer Aided esign, Vl. 15, N. 8 (1996), pages [2] R. Gnzalez, et. al., Supply and threshld vltage scaling fr lw pwer CMOS, IEEE Jurnal f Slid State Circuits, vl. 32, N. 8, Aug [3] V. Gutnik and A. Chandrakasan, Embedded pwer supply fr lw pwer SP, IEEE Trans. n VLSI Syst., Vl. 5, pp , ec [4] R. Hegde and N. R. Shanbhag, A Lw-pwer phase splitting passband equalizer, IEEE Trans. n Signal Prcessing, vl. 47, n. 3, March [5] A. Chandrakasan and R. W. Brdersen, Minimizing pwer cnsumptin in digital CMOS circuits, Prceedings f the IEEE, vl. 83, n. 4, pp , April [6] P. J. Restle et. al. Intercnnect in high speed designs: prblems, methdlgies and tls, ICCA 98, San Jse, CA. [7] K. L. Shepard and V. Narayanan, Nise in deep submicrn digital design, pp , AC 96, San Francisc, CA. [8] N. R. Shanbhag, A mathematical basis fr pwer-reductin in digital VLSI systems, IEEE Trans. n Circuits and Systems, Part II, vl. 44, n. 11, pp , Nv [9] R. Hegde and N. R. Shanbhag, Energy efficiency in presence f deep submicrn nise, ICCA 98, San Jse, CA, Nv [1] J. M. Rabaey, igital Integrated Circuits: A esign Perspective. Prentice-Hall, New Jersey, [11]. Sylvester and K. Keutzer, Getting t the bttm f deep submicrn, ICCA 98, San Jse, CA. [12] M.. Ercegvac and T. Lang, Lw-Pwer Accumulatr (Crrelatr), in prc. Internatinal sympsium n Lw- Pwer Electrnic esign (ISLPE),san Francisc, CA, 1995, pp [13] J. G. Prakis and. G. Manlakis, igital Signal Prcessing: Principles, Algrithms and Applicatins Prentice-Hall, New Jersey, [14] M. Xakellis and F. Najm, Statistical estimatin f the switching activity in digital circuits, in 31 st ACM/IEEE esign Autmatin Cnference, San ieg, CA, June 6-1, 1994, pp