Designing Polymorphic Circuits with Periodical Weight Adjustment

Transcription

1 2015 IEEE Sympsium Series n Cmputatinal Intelligence Designing Plymrphic Circuits with Peridical Weight Adjustment Hujun Liang 1, Rui Xie 2 1 Department f Cmputer Science, 2 Department f Accunting Anhui University f Finance and Ecnmics Bengbu, Anhui, China lhjabc45@sina.cm Liang Chen Department f Transprtatin Service Autmbile NCO Academy Bengbu, Anhui, China aufecl1@163.cm Abstract A plymrphic circuit can perfrm tw r mre functins under different cnditins withut the need f extra cmpnents. Thse functins can be activated by envirnmental signals, such as temperature, pwer supply vltage, illuminatin, and s n. S far, existent evlutinary algrithms can nly evlve plymrphic circuits at lwer success rate. In this paper, the peridical weight adjustment methd is prpsed fr the Evlutinary Strategy t evlve plymrphic circuits. The experimental results demnstrate that the peridical weight adjustment methd can perfrm better than existent evlutinary techniques fr plymrphic circuits, and it has the ptential t evlve mre cmplex plymrphic circuits, e.g., by this methd a three-state plymrphic circuit is evlved fr the first time. I. INTRODUCTION The cncept f plymrphic electrnics was prpsed by Stica et al[1]. Unlike traditinal multifunctinal electrnics, which are based n switches r multiplexers, the plymrphic circuit des nt need any extra cmpnents t switch its different functins, but by sme external factrs, such as pwer supply vltage, temperature and light [2-4]. The Evlutinary Algrithms (EAs) fr designing the plymrphic circuits are firstly prpsed by Sekanina and his clleagues [5-7]. The advantages f evlutinary design appraches are: i) the circuits designed by the evlutinary design apprach ften need fewer gates. ii) The evlutinary design apprach can find nvel and creative tplgies fr the circuits. Gajda and Sekanina have dne a lt f imprtant wrk n designing plymrphic circuits with evlutinary algrithms [5, 8, 9]. Especially in [8], tw-state plymrphic circuits with 8-inputs/8-utputs and 13-inputs/1-utput have being evlved with the aid f the binary decisin diagrams (BDD) and multiplexer. Hwever, designing plymrphic circuits purely by evlutinary algrithms is still a hard prblem. In [10], an imprved Evlutinary Strategy (ES) based n weighted sum methd was prpsed t design plymrphic circuits. Nevertheless, this imprved algrithm need t set weight factrs manually, and the success rates are still relatively lw. S, mre effective design methd shuld be develped. Because a plymrphic circuit has tw r mre different functins, it is necessary t balance the search preferences amng different functins. The bjective f the peridical weight adjustment methd in this paper is t balance the search preference amng different functins autmatically. The experimental results demnstrate that the success rates are imprved. The ES based n peridical weight adjustment can evlve plymrphic circuits mre effectively and has the ptential t evlve mre cmplex plymrphic circuits, e.g. three-state plymrphic circuits. This paper prpses a methd fr designing plymrphic circuits by peridically adjusting weights, the rest is is rganized as fllws. Sectin II intrduces sme related wrk. Sectin III cnsiders the existent prblems. Sectin IV describes the Peridical Weight Adjustment Methd (PWAM) in detail. Sectin V gives the experimental results. Finally, a brief cnclusin is given in sectin VI. II. RELATED WORK A. Cartesian Genetic Prgramming The evlutinary algrithm adpted in this paper is based n Cartesian Genetic Prgramming (CGP) [11-14], which was riginally intrduced int Evlvable Hardware (EHW) field by Miller et al. [15]. CGP has already demnstrated its efficiency and is widely used fr the evlutinary design f digital circuits [8, 9, 14]. The CGP mdel is described as fllws. Representatin: CGP uses an array f c (clumns) r (rws) f Prgrammable Elements (PEs) t represent the desired circuit. The prgrammable elements can be traditinal primary lgic gates (e.g. AND, OR, NOT), r plymrphic gates (e.g. AND/OR, AND/AND), r high-level functinal units. If r=1, it means the number f candidate PEs is same with c. Cnnectin: Each Prgrammable Element has its wn inputs and utputs. The inputs f each PE can nly be /15 $ IEEE DOI /SSCI

2 cnnected t the previus clumns r the circuit inputs, but cannt be cnnected t the latter clumns. The intercnnectivity f each PE is defined by the levels back parameter L, which determines hw many previus clumns can be cnnected t the current ne. In this paper, L = c, and this means that all previus clumns can be cnnected. It is nted that the PEs in the first clumn can nly cnnect t the primary inputs f the circuit. In rder that the expected circuit can be evlved under the cntrl f EAs, the candidate circuits must be mapped int chrmsmes. A chrmsme is a string f parameters (genes) that are jined tgether. It represents a ptential slutin t a given prblem and defines the tplgy f a candidate circuit. Althugh the CGP mdel is ften adpted in evlvable hardware cmmunity, the exact encding methds are ften with minr differences. The encding methd used in this paper is exactly the same as that in [10]. The initial ppulatin is generated randmly. B. Evlutinary Algrithms and Existent Results The evlutinary algrithm chsen fr designing plymrphic circuits is (, )-ES [5, 10]. In this algrithm, each individual f the ppulatin represents a ptential slutin t the desired plymrphic circuit. Generally, the prcedure f the fitness evaluatin f an individual can be described as that in Fig. 1. Fr a circuit in the ith mde with n i inputs and n utputs, the maximum fitness ni value f Fit i is 2 n. When bth weight factrs and are set t 1, it means the circuit in each mde is treated with equal emphasis. Fr cnvenience, this kind f ES is called as Cnventinal ES (CES). Using this methd, several kinds f plymrphic circuits using plymrphic gates as primary building blcks were evlved [5]. Hwever, the success rate f evlutinary design f plymrphic circuits with CES is very lw. In [10], a Weighted Sum Methd (WSM) is prpsed t imprve the evlutinary prcess, where w1 and w2 are set accrding t the evlutinary difficulties under different mdes. /* Suppse the expected plymrphic circuit behaves as a functin f 1 in mde 1 and as a functin f in mde 2, and the weight factrs fr tw 2 functins are dented by w1 and w2, respectively.*/ 1. Initialize the fitness value Fit 0 and temprary variables Fit 1 0, Fit Fr each input-utput cmbinatin d 2.1 Set the circuit int mde 1 and calculate crrespnding fitness Fit 1 ; 2.2 Set the circuit int mde 2 and calculate crrespnding fitness Fit 2 ; 3. Calculate the fitness f the cmplete plymrphic circuit as Fit = w 1 Fit 1 + w2 Fit. 2 Fig. 1. The prcedure f the fitness evaluatin f an individual. The typical results f bth CES and WSM are listed in TABLE I. It can be seen that the scale f the evlved plymrphic circuits is small, and the success rate is still relatively lw. All the six kinds f plymrphic circuits are als adpted as the benchmark circuits in this paper. TABLE I. THE RESULTS OF EXISTENT EVOLUTIONARY TECHNIQUES Results [5] Results [10] Num.Gates* Circuits Gates Used w1 = w 2 =1w1 = w2 =1 Best Results [5] [10] Suc.Rate** Suc.Rate Ave. Ave. Suc.Rate (Std.) (Std.) w 1 / w 2 NAND/NOR b-parity-median XOR/XOR (106159) (102429) 1/2000 NAND/XOR b-parity-median XOR/NOR (91685) (114312) 1/8192 Mult2b-sn4b-1 NAND/NOR AND/AND (104416) (85035) 6/1 Mult2b-sn4b-2 ( ab )/XOR XOR/(a b) (117700) (105613) 1/256 2b-mult-add-1 NAND/NOR OR/XOR (106129) (84513) 48/1 2b-mult-add-2 NAND/NOR AND/AND (105874) (81271) 1/16 *Num.Gates dentes the number f ttal gates in each chrmsme. **Suc.Rate dentes the success rate. 1500

3 III. PROBLEM AND STRATEGY As descriptins in the frmer sectin, the success rate f existent Evlutinary Algrithms (EAs) is relatively lw, even fr small-scale tw-state plymrphic circuits. The typical appraches fr imprving the evlutinary ability is t design imprved versins f t EAs [16], r t intrduce high-level functinal cmpnents as the building blcks instead f primary gates (i.e. functin-level evlutin) [7], r t develp the Divide-and-Cnquer techniques [17]. Fr plymrphic circuits, due t their intrinsic cmplexity, neither effective functin-level evlutin appraches nr Divide-and- Cnquer appraches have been prpsed, s far. Cmpared t the CES, thugh the WSM can effectively imprve the success rate and decrease required evlutinary generatins fr mst plymrphic circuits. Hwever, the WSM needs t set up the apprpriate weight values. In this paper, an evlutinary algrithm based n peridical weight adjustment is prpsed. It can change its weights peridically accrding t a predefined functin, withut the need f effrts t d a number f experiments t btain apprpriate weights. IV. EVOLUTION STRATEGY WITH PERIODICAL WEIGHT ADJUSTMENT Fr a plymrphic circuit with n functins, the fitness value can be calculated as (1). Fit ( x ) w n i 1 i Fit ( x ) Where Fit i (x) dentes the fitness f the chrmsme x under mde i, and w i dentes the crrespnding nn-negative weight factr. Generally, the weight factr is imprtant and will affect the efficiency f EAs. In [5], bth weight factrs are actually set t 1. In [10], the weight factrs are set in advance, and during the evlutinary prcess, the weight factrs dn t change, while in this study, the weight factrs are set t change peridically. Fr cnvenience, it is named as PWAM. In the PWAM methd, the weight factrs are set t change dynamically and peridically accrding t the sinusid functin, which is expressed as (2). i (1) w sin( 2 t ) 1 1 i n (2) i i Where n means the number f functins included in a plymrphic circuit, and t i is calculated accrding t (3). Additinally, each weight factr is added by 1 in rder t avid being negative. t i ( CG ( i 1) Pd / Den) md Pd 1 i n Pd The bjective f (3) is t map the number f current generatin int interval [0, 1), where CG means the current evlutinary generatin in the evlutinary prcess. Pd means perid, i.e. the changing perid f the weight values, fr (3) example, if Pd=100, it means after 100 evlutinary generatins t i will be same with its riginal value. Generally, Pd is set smaller than the maximum number f evlutinary generatins. Due t the sinusidal functin in itself is peridical, (3) can be simplified int (4). t i CG ( i 1) Pd / Den 1 i n Pd Den is a psitive number, which can be set t n r ther designated values. Its main functin is t generate phase difference. Fr cnvenience, a new variable PhaseDifference is defined as fllws. [ i ( i 1)] Pd / Den 2 PhaseDifference 2 Pd Den The unit fr PhaseDifference is radian. Fr example, fr a 3-state plymrphic circuit, generally Den can be set t 3, and the phase difference between weights will be 2 / 3 ; if Den is set t 5, the phase difference between weights will be 2/5. Amng all the experiments, the case where PhaseDifference=0 shuld be paid mre attentin. It des nt mean Den. In this situatin, (4) shuld be rewritten as (6). This means all weights are changing with evlutinary generatins but still keep same with each ther. t i (4) (5) CG Pd md 1 i n Pd (6) V. EXPERIMENTS In this sectin, experiments are dne t test the perfrmance f PWAM. A. Parameter Settings In TABLE II, the parameters f Evlutin Strategy are given. The number f runs is 100, which means that each plymrphic circuit is evlved 100 times independently. In all the experiments, the mutatin rate is TABLE II. PARAMETERS USED IN THE EXPERIMENTS Number f runs 100 Mutatin rate 0.05 Circuit layut 1 Num.Gates Maximum number f evlutinary generatins 300, The gate array f the CGP mdel is 1 Num.Gates. That is t say, r=1, and the number f clumns c is equal t the number f gates (Num.Gates). Since the number f candidate 1501

4 gates used t evlve different plymrphic circuits is nt same, c is nt a fixed number. Fr fair cmparisns, the number f the gates used fr each plymrphic circuit are the same as thse in [10] (see TABLE I). Perfrmance indicatrs are Suc.Rate and Ave. Suc.Rate means average success rate, and Ave. means the average evlutinary generatins. As fr Ave., when ne run cannt find a functinally crrect circuit, the maximum number f evlutinary generatins is cunted B. Cmparisns f Different Weight Adjustment Methds In this sectin, the experimental results f the evlutinary design f tw-state plymrphic circuits are presented. The intentin f these experiments is t test hw well the peridical weight adjustment methd behaves. Fr this grup f experiments PhaseDifference=. Fig. 2. The relatinship between the perid and the success rate TABLE III. EXPERIMENTAL RESULTS OF DIFFERENT WEIGHT ADJUSTMENT METHODS WSM PWAM Circuit (The best results) (Perid(Pd)=10000) Suc.Rate Ave.(Std.) Suc.Rate Ave.(Std.) 5b-parity-median (102429) (88219) 5b-parity-median (114312) (115166) 2b-mult-add (84513) (90565) 2b-mult-add (81271) (104959) Mult2b-sn4b (85035) (59359) Mult2b-sn4b (105613) (89029) The data in parentheses are standard deviatins. As is shwn in TABLE III, PWAM wrks well than the WSM. It can be bserved that, fr the circuit 5b-parity-median-2, the perfrmance f the PWAM is wrse than that f the WSM. Fr the circuit 2b-mult-add-2, the success rates f WSM and PWAM are similar. Fr ther fur circuits, the PWAM is much better than the WSM. Especially, fr the circuit Mult2bsn4b-2, the success rate f the PWAM is higher than that f WSM by 42%. Due t the PWAM is better, it will be further analyzed in the fllwing sectins. C. The Impact f Parameters 1) Perid and PhaseDifference In this sectin, hw the parameters Perid (Pd) and PhaseDifference will affect the perfrmance f the PWAM are evaluated. Fig. 2 demnstrates hw the Perid affects the success rate. It can be bserved that, when the Perid is t small r t large, the success rate is relatively lw. The ideal value fr the Perid is between 2000 and Within this range, the Perid is nt a sensitive parameter fr the evlutinary Fig. 3. The relatinship between the phase lag and the success rate algrithm. In the fllwing experiments, the parameter Perid is fixed at Fig. 3 reveals hw the phase lag (i.e. PhaseDifference) affects the success rate. Similar t the parameter Perid, the PhaseDifference is als nt a sensitive value in a certain range. The ideal value fr PhaseDifference can be chsen frm 60 ( 2 / 6 ) t 330 ( 211/ 12 ). When the phase lag is set t 0 (0) r 360 ( 2 ), it means there are n phase differences amng the weight factrs. 2) The Number f Candidate Gates This sectin explre the relatinship between the number f candidate gates and the success rate. The tw-state plymrphic circuits 5b-parity-median-2 and 2b-mult-add-1 are taken as a test wrkbench. Since the trend is evident, nly the test parameters f 5b-parity-median-2 are given in details in TABLE IV. In TABLE IV, when Perid=10000, with the number f candidate gates increases frm 40 t 60, the success rate increases frm 59% t 72%, and the average generatin needed fr btaining a slutin decreases. It seems the number f candidate gates has much impact n the evlutin prcess. Since the selected CGP array cnsists f ne rw, the number f clumns c is same with the number f candidate gates. 1502

5 TABLE IV. THE RELATIONSHIP BETWEEN THE NUMBER OF CANDIDATE GATES AND THE SUCCESS RATE Perid(Pd)=2000 Perid(Pd)= b-parity-median-2 Suc.Rate Ave.(Std.) Suc.Rate Ave.(Std.) Num.Gates= (i.e. c=40) (113462) (115166) Num.Gates= (i.e. c=60) (117044) (114527) Fig. 4. The number f candidate gates and the success rate In rder t reveal hw the number f candidate gates affects the perfrmance f the PWAM, mre experiments n 5b-parity-median-2 and 2b-mult-add-1 are cnducted, and experimental results are given in Fig. 4. Fig. 5. The number f candidate gates and the average evlutinary generatin Frm Fig. 4, it can be bserved that the success rate increases with the increment f the number f candidate gates. When the number f candidate gates is large enugh, the success rate is clse t 100%. As can be bserved frm Fig. 5, fr circuits 5b-parity-median-2 and 2b-mult-add-1, the average evlutinary generatin decreases gradually at first. Hwever, when the number f candidate gates exceeds 500, the difference f average evlutinary generatins is n lnger bvius. D. Evlving a Three-State Plymrphic Circuit with the PWAM In rder t cmpare the perfrmance f the CES, in which each weight factr is 1, with that f the PWAM, experiments n a 3-state plymrphic circuit are cnducted. The 3-state plymrphic circuit is cmpsed f a 2-bit multiplier, a 2-bit adder and a 4-bit srt net. In this experiment, Num.Gates=80, Perid= TABLE V. EXPERIMENTAL RESULTS OF A 3-STATE POLYMORPHIC CIRCUIT The style f weight adjustment Suc.Rate Ave.(Std.) w 1 = w2 = w 3 = (98169) PhaseDifference= 2/ (83570) w 1 = w2 = w (105860) (same but changing) Frm TABLE V, it can be bserved that, when all weight factrs are set at 1 (i.e. the CES is used), the success rate is nly 42%. While with the PWAM (PhaseDifference= 2 / 3), the success rate is 92%. It is higher by 50%. The case in which all weight factrs are equal but changing simultaneusly is als given in TABLE V. Its perfrmance is between thse f the frmer tw cases. Except fr tw-state plymrphic circuits, the PWAM can be used t evlve mre cmplex circuits. An evlved slutin fr the 3-state plymrphic circuit is shwn in Fig. 6. The difference f success rate caused by PhaseDifference n the evlutin design f a 3-state plymrphic circuit is given in TABLE VI. It is bvius that when the PhaseDifference is nt clse t 0 r 360 the result is acceptable. N matter which value is chsen frm [60, 300 ] fr PhaseDifference, the perfrmance f the algrithm will nt change greatly. TABLE VI. Statistics Suc.Rate Ave. (Std.) THE RELATIONSHIP BETWEEN PHASEDIFFERENCE AND THE PERFORMANCE OF THE PWAM PhaseDifference (in Degree) (94321) (83570) (89125) (92527) (90799) (105860) 1503

6 Fig. 6. A three-state plymrphic circuit 2b-mult-add-sn4b. The inputs: A (0-1), B (2-3); the utputs: 0-3 (0-2 in case f adder); gates: 0-nand/nr/r, 1- r/xr/nand, 2-and/nand/and, 3-nr/and/nr VI. DISCUSSION AND CONCLUSIONS In rder t imprve the ability f the evlutinary design f plymrphic circuits, the peridical weight adjustment methd fr Evlutinary Strategy, i.e. the PWAM is prpsed. The weight factrs are made t change dynamically during the evlutinary prcess. Experiments n six 2-state circuits demnstrate that the PWAM is better than the CES and the WSM in mst cases. A 3-state plymrphic circuit is evlved fr the first time. The PWAM shws much better perfrmance. Hwever, fr a plymrphic circuit with a bit large scale (e.g. a 3-bit multiplier/3-bit adder); the PWAM still can nt design it easily. Therefre, in the future, the scalability is still an imprtant issue t be reslved and why PWAM is better than CES and WSM shuld be further analyzed. REFERENCES [1] Adrian Stica, Ricard Zebulum and Didier Keymeulen, "Plymrphic Electrnics," in the 4th Internatinal Cnference n Evlvable Systems: Frm Bilgy t Hardware (ICES'01), Tky, Japan, 2001, pp [2] Richard Ruzicka and Lukas Sekanina, "Physical Demnstratin f Plymrphic Self-Checking Circuits," in IEEE Internatinal On-Line Testing Sympsium, 2008, pp [3] Adrian Stica, Ricard Zebulum and Didier Keymeulen, "Taking evlutinary circuit design frm experimentatin t implementatin: sme useful techniques and a silicn demnstratin," IEE Prceedings n Cmputers and Digital Techniques, vl. 151, pp , 18 July [4] Adrian Stica, Ricard Zebulum and Didier Keymeulen, "On Plymrphic Circuits and Their Design using Evlutinary Algrithms," in IASTED Internatinal Cnference n Applied Infrmatics(AI2002), Innsbruck, Austrilia, [5] Lukas Sekanina, "Evlutinary Design f Gate-Level Plymrphic Digital Circuits," in Applicatins n Evlutinary Cmputing: EvWrkkshps 2005, 2005, pp [6] Lukas Sekanina and Zdenek Vasicek, "A SAT-based Fitness Functin fr Evlutinary Optimizatin f Plymrphic Circuits " in Design, Autmatin & Test in Eurpe Cnference & Exhibitin (DATE), 2012, Singapre, 2012, pp [7] Lukas Sekanina, Vjtech Salajka and Zdenek Vasicek, "Tw-Step Evlutin f Plymrphic Circuits fr Image Multi-Filtering," in WCCI 2012 IEEE Wrld Cngress n Cmputatinal Intelligence, Brisbane, Australia, 2012, pp [8] Z. Gajda and L. Sekanina, "On Evlutinary Synthesis f Cmpact Plymrphic Cmbinatinal Circuits," Multiple-Valued Lgic and Sft Cmputing, pp , [9] Z. Gajda and L. Sekanina, "Gate-level ptimizatin f plymrphic circuits using Cartesian Genetic Prgramming," in IEEE Cngress n Evlutinary Cmputatin, Trndheim, Nrway, 2009, pp [10] Hujun Liang, Wenjian Lu and Xufa Wang, "Designing Plymrphic Circuits with Evlutinary Algrithm Based n Weighted Sum Methd," in the 7th Internatinal Cnference n Evlvable Systems: Frm Bilgy t Hardware (ICES'07), Wuhan, China, 2007, pp [11] Julian F. Miller, Cartisian genetic prgramming: Springer Berlin Heidelberg, [12] P. Burian, "Reductin f Fitness Calculatins in Cartesian Genetic Prgramming," in 2013 Internatinal Cnference n Applied Electrnics (AE), Pilsen, 2013, pp [13] P. Burian, "Cmpact Versin f Cartesian Genetic Prgramming " in 2014 Internatinal Cnference n Applied Electrnics (AE), Pilsen, 2014, pp [14] B.W. Gldman and W.F. Punch, "Analysis f Cartesian Genetic Prgramming's Evlutinary Mechanisms," IEEE Transactins n Evlutinary Cmputatin, vl. 19, pp ,

7 [15] Julian Miller and Dminic Jb, "Principles in the Evlutinary Design f Digital Circuits - Part I," in Genetic Prgramming and Evlvable Machines. vl. 1, 2000, pp [16] Michal Bidl and Zdenek Vasicek, "Cellular Autmata-Based Develpment f Cmbinatinal and Plymrphic Circuits: A Cmparative Study," in Internatinal Cnference n Evlvable Systems: Frm Bilgy t Hardware (ICES'08), 2008, pp [17] Emanuele Stme, Tatiana Kalganva and Cyrille Lambert, "Generalized disjunctin decmpsitin fr evlvable hardware," IEEE Transactins n Systems, Man and Cybernetics, Part B, vl. 36, pp ,