An Alternative to Error Correction for SRAM-Like PUFs

Transcription

1 An Alternative to Error Correction for SRAM-Like PUFs Maximilian Hofer and Christoph Boehm Institute of Electronics, Graz University of Technology Abstract. We propose a new technique called stable-puf-marking as an alternative to error correction to get reproducible (i.e. stable) outputs from physical unclonable functions (PUF). The concept is based on e influence of e mismatch on e stability of e PUF-cells output. To use is fact, cells providing a high mismatch between eir crucial transistors are selected to substantially lower e error rate. To verify e concept, a statistical view to is approach is given. Furermore, an SRAM-like PUF implementation is suggested at puts e approach into practice. Keywords: Physical Unclonable Functions, SRAM, Pre-Selection. Introduction Due to e widespread use of Smart Cards and radio frequency identification (RFID) devices, e demand for secure identification/auentication and oer cryptographic applications is continuously increasing. For is purpose a fingerprint of a chip can be useful. Physical unclonable functions (PUFs) provide such an output. In 200, Pappu et al. introduced e concept of PUFs []. In is approach a unique output is produced by evaluating e interference pattern of a transparent optical medium. Unfortunately, due to e way of pattern extraction, Pappu s approach turns out to be quite expensive. In [2,3], Gassend et al. introduce physical unclonable functions in silicon. The concept utilizes manufacturing process variation to distinguish between different implementations of e same integrated circuit (IC). This is done by measuring e frequency of self-oscillating loop circuits. These frequencies differ slightly between e realizations. However, e chip area is large and e current consumption is high. Anoer approach is to use e initial values of SRAM cells. [4,5] shows at ere exist SRAM chips which deliver e same start-up value again and again which is e crucial property of a PUF. The best of em deliver an error rate of less an 3 %. So it seems at SRAM-like structures are feasible as dedicated PUF-cells [6]. One way to deal wi errors in e PUFs responses is to use error-correction codes (ECC) [7]. Here, redundace is added by storing parity bits during an initialization phase. These bits can be used afterwards to reconstruct e reference S. Mangard and F.-X. Standaert (Eds.): CHES 200, LNCS 6225, pp , 200. c International Association for Cryptologic Research 200

2 336 M. Hofer and C. Boehm value. Unfortunately, efficient decoding is difficult. If e error rate is high, e runtime increases strongly [8,9]. Oer meods use statistical data of e fuzziness [0] (i.e. e degree of instability) of e PUF responses. In [0], Maes et. al. read out e response several times to collect data about e stability of e different PUF-cells. An advantage of is Soft Decision Data Helper Algorim is at e number of PUF-cells can be reduced up to 58.4 %. A drawback is at e initialization phase needs a higher number of runs (e.g. 64 in [0]). In is work we propose an alternative meod to deal wi unstable PUFcells. The time needed for e read-out phase is reduced due to e fact at furer post-processing of e PUF response becomes less complex or even needless depending on e application. The remainder of e paper is organized as follows. Section 2 describes e idea behind e concept. In Section 3 a statistical analysis is given. Section 4 provides an approach to an implementation in silicon. Finally, section 5 concludes e paper. In e appendix some additional calculations and tables are given. 2 Idea Figure shows a CMOS SRAM-cell at can be used as a PUF-cell. A whole PUF consists of an application dependent number of such cells. We assume at e design and e layout of at PUF-cell are optimized in such a way at e PMOS transistors match and e NMOS transistors mismatch. In an SRAM PUF, e output which is defined by e state of OUT after power-up, mainly depends on e reshold voltage (V ) mismatch. Assuming identical initial potentials at OUT and OUT, e mismatch of e NMOS transistors lead to a difference between i and i 2 in e two branches of e SRAM cell. If i 2 is higher an i,epotentialatout will move towards V SS,epotentialatOUT will move towards V DD.Ifi 2 is lower an i, e cell behaves e oer way round. This behavior at OUT and OUT should be an intrinsic property of e cell and should not change over time. If e mismatch is too small, e cell result will be unstable due to noise, temperature shifts, and oer shifts in e working point, e.g. caused by changes in V DD. The idea is to select only e stable cells (i.e. ose cells providing a high mismatch) to generate e PUF output. Before e PUF is used for e first time, during an initialization phase e stable PUF-cells are detected. These cells are marked. All e oer PUF-cells are not used any longer. From now on, only stable PUF-cells generate a stable response. This gives rise to e question of how to select e stable bits. An intuitive approach is to measure e results of a PUF-cell repeatedly and chose only ose cells which always provide e same output. For various reasons is is not practicable. First of all, additional measurements must be done to get useful The mismatch s variance of e transistors can be controlled over e transistor area: Smaller area leads to higher mismatch. This means at e analog designer can influence e variance but not e individual value of e mismatch which defines e PUF-cell output.

3 An Alternative to Error Correction for SRAM-Like PUFs 337 Fig.. Common SRAM-cell statistical data and us is not feasible for an initial production test flow where measurement time has proportional impact on e product costs. Anoer problem is at ere are cells which show temperature depending behavior. So e initial measurements would have to be done over e whole temperature range. Furermore, e influence of aging changes e mismatch behavior [5] and could cause additional errors after some time. Anoer approach to find unstable PUF-cells is to use e fact at stable cells decide faster [6]. To detect e fast flipping cells, e decision time has to be measured. In figure 2 is concept is illustrated. After a certain time t useful e Fig. 2. Measurement of decision time (UF:useful,NUF: not useful) cells above an upper reshold or under a lower reshold are marked as useful. All oer cells which lie between e two resholds are marked as not useful. Unfortunately, simulations show at e decision time strongly depends on e temperature. Therefore during e initialization phase a constant temperature is necessary to allow e use of an absolute time t useful. Anoer solution to is problem could be to measure e time spans needed to reach a reshold value. The fastest cells are used. Since it may happen at e fastest cells of a chip are still not fast enough to meet e above requirements a stable behavior can not be expected in all cases.

4 338 M. Hofer and C. Boehm Fig. 3. The mismatch is divided in ree classes: The useful PUF-cells wi positive mismatch (UF +), e useful PUF-cells wi negative mismatch(uf ) and e not useful PUFs (NUF) The approach we propose in is paper is based on e selection of cells which provide a mismatch at exceeds a certain reshold. In e case of e shown SRAM-PUF, e mismatch of e NMOS transistors must be above such a reshold. In figure 3, e mismatch ΔV of two transistors is depicted schematically. Here, is distribution is assumed to be Gaussian. A positive and a negative reshold value (ΔV + and ΔV,wi ΔV + = ΔV ) are defined, which is necessary to divide e PUF-cells into ree classes: e useful PUF-cells wi positive mismatch (UF + ), e useful PUF-cells wi negative mismatch (UF ) and e not useful PUF-cells (NUF). In figure 3, e ree sections are depicted. In e middle section, e mismatch is too small to provide a stable behavior. These bits are marked as NUF. The mismatch of e oer bits is big enough to provide a stable output. Thus, e reshold value must be chosen correctly to reach an acceptable error rate. The larger e reshold value, e smaller e number of PUF-cells at are marked as stable and e smaller e error rate. Thus, to be able to provide e required number of useful cells, e number of initial PUF-cells has to be adapted to e chosen reshold value. For is reason, e reshold value is a trade-off between e ratio of e useful PUF-cells and all PUF-cells and e error rate. One meod to measure ΔV is to use a common analog to digital converter (ADC). In figure 4 a block diagram is shown. The disadvantage of is approach is e size of e ADC caused by e requirements on it. In order to get a balanced output, e ADC must have a small offset. Furermore e ADC has to be fast and e result should not depend on e noise of e circuit. The proposed concept to classify e cells into UF and NUF is to add a systematical V offset to e circuit (see figure 7): Two measurements per PUFcell are needed. During e first measurement we add a negative offset. Thus e reshold is set to V. During e second measurement we move e reshold to V +. This is illustrated in figure 3 denoted by e two arrows. The classification can be done as follows: If e mismatch of e transistors exceeds e

5 An Alternative to Error Correction for SRAM-Like PUFs 339 Fig. 4. Measurement of e mismatch using an ADC reshold, e PUF-cell will provide e same output for bo measurements and us e cell is marked as useful. If e mismatch is too small, e output OUT of e cell will differ for e two measurements. The cell is marked as not useful. Problems will occur if e reshold value is chosen too big. In such a case, only a few or even no cells are marked as useful which can lead to severe problems. On e oer hand, if e reshold is chosen too small, disturbances like noise will lead to output errors and make e whole pre-selection process useless. 3 Modeling and Statistical Aspects To analyze e performance of is approach, Monte Carlo simulations are not feasiblesinceeerrorrateafterepre-selection process (i.e. after e useful- PUF-marking) should be so small at e number of simulation runs to determine e error probability would exceed a tolerable number. So we prefer an analytic meod to estimate e performance of e pre-selection process: For all furer analyses we assume at e distribution of e V mismatch as well as e distribution of e disturbances (noise, temperature-dependent errors, etc.) is Gaussian [,2,3,4]. To determine e effect of e pre-selection process, we need e probability density function (PDF) f(x) and its integral, e cumulative distribution function (CDF) F (x) of a Gaussian: f(x) =φ μ, (x) = 2π e 2( x μ () F (x) =Φ μ, (x) = x e 2( x μ dx, (2) 2π where μ is e mean and e variance of e Gaussian. If ere is no disturbance at e PUF-cell, e cell output will be e same whenever e PUF is read-out. In is case e output would be zero for all PUFcells having a negative ΔV and one for all cells wi positive ΔV (see figure 5a). If ere are disturbances due to noise, temperature, etc., it may happen at if e mismatch is sufficiently small or e disturbance sufficiently large, e decision is defined by is disturbance. That effect can be seen in figure 5b where Φ 2 shows e mean output depending on ΔV taking e distribution of e

6 340 M. Hofer and C. Boehm (a) (b) (c) (d) (e) (f) Fig. 5. (a) Ideal distributions Φ Φ 4.(b) Real distributions Φ Φ 4.(c)Usefulpositive PUF-cells(UF+). (d) Useful negative PUF-cells(UF-). (e) PUF-cells which occur in UF + and UF. (f) Useful PUF-cells(UF) and not-useful PUF-cells(NUF). disturbance into account. At ΔV = 0 e mean output equals 0.5. The same curve but biased wi e reshold ΔV and ΔV + depict Φ 4 and Φ 3. φ is e distribution of e mismatch. After selecting e useful PUF-cells, e error rate can be decreased significantly. Figures 5c and 5d show e product of Φ 3 and φ, and e product of ( Φ 4 )andφ respectively. These curves depict e distribution of being selected as useful including disturbances, e distribution of e V mismatch and a certain V offset. Hence e figures represent e number of selected PUF-cells. Figure 5e shows ose cells at are selected twice, i.e. at are declared to be useful for bo offsets. To get correct results ese double-selections have to be compensated for in e analysis. Figure 5f shows e distributions of selected and not selected cells. Since 2 = 3 = 4 =, μ = μ 2 =0,andμ 3 = μ 4 can be assumed, we get e following equation for e number of useful PUF cells α (see appendix):

7 An Alternative to Error Correction for SRAM-Like PUFs 34 α = 2π μ [ ( ) V 2 ( ) V 2 μ dv + 2 ( ) V 2 μ dv + ( ) V 2 μ dv 2 2π ] dv (3) The error rate e at ΔV can be derived using e following equation (see appendix): e(δv )=φ Φ 2 φ Φ 2 Φ 4 φ Φ 2 Φ 3 Φ 4 +φ Φ 3 φ Φ 3 +φ Φ 3 Φ 4 Φ 2 φ Φ 3 Φ 4, (4) where all φ i and Φ i are evaluated at ΔV. Example. The standard deviation of ΔV is 30 mv, e standard deviation of φ 2,3,4 equals 6.6 mv. This coresponds to an error-rate of 5%. 2 In figure 6 e error rate and e ratio of useful PUF-cells α are shown in a diagram. It can be seen at selecting for example e best 50 % can decrease e error rate significantly. A table of different examples is shown in appendix B. 4 Implementation Different circuits are possible to implement e approach described above. One of em is presented. To understand e circuit we consider an ordinary SRAMcell depicted in figure 7. We assume at P and P 2 match. Hence, e decision depends on e mismatch of e reshold voltage of N and N 2 denoted ΔV. To mark e cells as introduced in section 2, we have to add an additional voltage source at e gate of one of e NMOS transistors to provide e bias we need for e reshold (see figure 7a). Since e implementation of such a circuit is difficult, e preferred way is to use its Norton equivalent - a current source - in parallel to one of e NMOS transistors (see figure 7b). From figure 8, e equivalence of e two circuits can be seen. The characteristics of two different diode-loaded MOSFETS are shown. For e same V GS and different reshold voltages, e amount of current rough e transistors will be different. Thus, additional current at one of e branches of e SRAM-cell acts as a mismatch of V. The circuit depicted in figure 9 is a practical implementation of e approach. During e first phase N 7 is switched-off. N 3, N 4 and P, P 2 are building a SRAM similar circuit. N 2 acts as a current limiter for is circuit. The circuit is designed, at e mismatch between P and P 2 is small and should not affect e result. Due to e fact at e transistors N 3 and N 4 are diode loaded, e 2 We meassured an error-rate of 4% in a dedicated PUF-cell in e temperature range from 0 80 C. So is is a raer pessimistic value.

8 342 M. Hofer and C. Boehm (a) (b) Fig. 6. a) Error rate e. (b) Ratio of useful PUF-cells α against μ 3,4. circuit does not flip as fast as e SRAM depicted in figure. During e second phase, N 7 is switched-on and e circuit flips completely to one direction. The bias transistors which are used for e PUF-cell selection (P 3 and P 4 )areused during e first phase and switched-off during e second phase (P 7 and P 8 are switched-on; P 5 and P 6 are switched-off). If we want to add a fictive negative offset voltage at e transistor N 4, P 8 is opened and P 6 is closed. Thus, e transistor P 4 is in parallel wi transistor P 2. A higher current passes N 4. The same can be done on e right branch (P 7, P 5, P 3 and N 3 ). The tru table for e control of e transistors P 5, P 6, P 7,and P 8 is shown in table. A furer improvement of is circuit can be achieved by separating e mismatching transistors N 3 and N 4 from e evaluation circuit consisting of e transistors N 5 to N 7 and P to P 8. Additionally, two transistors are required to connect each cell to e evaluation circuit. So, one PUF-cell consists of only five

9 An Alternative to Error Correction for SRAM-Like PUFs 343 (a) (b) Fig. 7. (a) SRAM-cell wi additional voltage source at e gate of N ; (b) SRAM-cell wi additional current source at e drain of N. Fig. 8. Characteristics of two MOSFETS having different V transistors as depicted in figure 0. The cells can be selected sequentially and evaluated using e same evaluation circuit (i.e. sense amplifier). Thus, e area of one PUF-cell is scaled-down to about e size of a common SRAM-cell. For e particular topology at is about 00F 2 ( minimum featured size ). In such a circuit it could happen at e mismatch of e evaluation circuit influences e decision. Due to is fact, cells using e same evaluation circuit could tend to output e same value. To reduce e influence of an asymmetric sense amplifier, e number of PUF-cells which use e same evaluation logic should be chosen carefully. The whole structure diagram of e system is depicted in figure. There are two modes: One for e initialization phase and anoer one for e nominal operation. The addresses of e useful cells are stored in a non-volatile memory (NVM). During e initialization phase is memory is filled wi data: The outputs of e single PUF-cells after adding bo bias currents are compared. If e output stays constant for bo bias values, e address of e PUF-cell is written

10 344 M. Hofer and C. Boehm Fig. 9. Implementation example of an SRAM-like PUF wi pre-selection transistors P 3 and P 4 Table. Control of e transistors P 5, P 6, P 7, P 8 for adding e current bias to e circuit function n p init p ninit p init n ninit n no reshold p reshold n reshold Fig. 0. PUF-cells wi shared sense amplifier into e NVM. The address of e NVM is incremented and e next PUF-cell is tested. This is done until e necessary number of outputs is reached. If not enough useful cells are provided an error occurs and e PUF must be considered to be defect. This indicates at e mismatch between e transistors is too small or at e ratio of required PUF-cells and available PUF-cells is too high. Possible solutions to is problem are to increase e number of PUF-cells or to reduce e upper and lower reshold values ΔV and ΔV +. During e nominal mode, e PUF-cells stored in e NVM are read-out.

11 An Alternative to Error Correction for SRAM-Like PUFs Conclusion Fig.. Structure diagram wi initialization logic In is paper we introduced a pre-selection process for SRAM-like PUFs which can be implemented wi little effort. We demonstrated at error-rates of 0E-6 are achievable. Due to e smaller error rate, using e marking procedure makes post-processing less complex or even unnecessary depending on e application. Hence, e area of e digital part of e circuit can be reduced. Furermore, e smaller error rate leads to less power consumption and faster read-out. The additional effort caused by e initialization phase is small since e whole process can be done at one temperature and only two read-out cycles are necessary to separate e stable and e unstable PUF-cells. References. Pappu, R., Recht, R., Taylor, J., Gershenfeld, N.: Physical one-way function. Science 297(5589), (2002) 2. Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Silicon physical random functions. In: CCS 02: Proceedings of e 9 ACM conference on Computer and communications. security, pp (2002) 3. Blaise, G., Daihyun, L., Dwaine, C., van Dijk, M., Srinivas, D.: Identification and a2entication of integrated circuits. Concurrency Computation: Pract. Exper. 6, (2004) 4. Guajardo, J., Kumar, S.S., Schrijen, G.-J., Tuyls, P.: FPGA Intrinsic PUFs and Their Use for IP Protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES LNCS, vol. 4727, pp Springer, Heidelberg (2007) 5. Boehm, C., Hofer, M.: Using SRAMs as Physical Unclonable Functions. In: Proceedings of e 7 Austrian Workshop on Microelectronics - Austrochip, pp (2009) 6. Ying, S., Holleman, J., Otis, B.P.: A Digital.6 pj/bit Chip Identification Circuit Using Process Variations. IEEE Journal of Solid-State Circuits 43(), (2008) 7. Dodis, Y.: Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Oer Noisy Data. In: Naor, M. (ed.) EUROCRYPT LNCS, vol. 455, pp Springer, Heidelberg (2007) 8. Hong, J., Vitterli, M.: Simple Algorims for BCH Decoding. IEEE Transactions of Communications 43, (995)

12 346 M. Hofer and C. Boehm 9. Boesch, C., Guajardo, J., Sadeghi, A.R., Shokrollahi, J., Tuyls, P.: Efficient Helper Data Key Extractor on FPGAs. In: Oswald, E., Rohatgi, P. (eds.) CHES LNCS, vol. 554, pp Springer, Heidelberg (2008) 0. Maes, R., Tuyls, P., Verbauwhede, I.: Low-Overhead Implementation of a Soft Decision Helper Data Algorim for SRAM PUFs. In: Clavier, C., Gaj, K. (eds.) CHES LNCS, vol. 5747, pp Springer, Heidelberg (2009). Pelgrom, M., Duinmaijer, A., Welbers, A.: Matching Properties of MOS- Transistors. IEEE Journal of Solid-State Circuits 24, (989) 2. Pelgrom, M.J.M., Tuinhout, H.P., Vertregt, M.: Transistor matching in analog CMOS applications. In: International Electron Devices Meeting, IEDM 98 Technical Digest., pp (998) 3. Mizuno, T., Okumtura, J., Toriumi, A.: Experimental study of reshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET s. IEEE Transactions on Electron Devices 4, (994) 4. Tsividis, Y.: The MOS Transistor. Oxford University Pres, New York (999) A Calculations Ratio of Useful PUF-Cells α: Partial probability of occurrence of selected PUF cells depending on ΔV (see figure 7(c) and 7(d)): 3 UF + = φ Φ 3 (5) UF = φ ( Φ 4 ) (6) Probability of occurrence PUF-cells being selected twice depending on ΔV (see figure 7(e)): UF + UF = φ Φ 3 ( Φ 4 ) (7) Total probability of occurrence depending on ΔV : UF = UF + + UF 2(UF + UF )= = φ [Φ 3 +( Φ 4 ) 2Φ 3 ( Φ 4 )] = = φ [ Φ 4 Φ 3 +2Φ 3 Φ 4 ] (8) From UF e ratio of useful PUF-cells α can be determined: α = = 3 2π UF dv = ( ) e V μ 2 2 [ 2π 4 2π μ V 3 2π μ μ The results of is section depend on e reshold values V + andv.

13 4 2π = 2π 3 An Alternative to Error Correction for SRAM-Like PUFs 347 ( ) V 2 ] μ 4 4 dv dv = [ ( ) ( ) V μ 2 V e V 2 μ dv + 4 μ μ 4 4 ] 3 4 2π μ 3 3 dv (9) In general we can assume at 2 = 3 = 4 =, μ = μ2 = 0, and μ 3 = μ 4. Then α becomes: α = 2π μ [ ( ) V 2 ( ) V 2 μ dv + 2 ( ) V 2 μ dv + ( ) V 2 μ dv 2 2π ] dv (0) Ratio of Not-Useful PUF-Cells β: To verify e result of α, eratioβ of not selected PUF-cells is determined as well: β = NUF dv () NUF = φ [( Φ 3 )( ( Φ 4 )+Φ 3 ( Φ 4 ))] = φ [( Φ 3 )(Φ 4 )+Φ 3 ( Φ 4 ))] = φ [Φ 4 Φ 4 Φ 3 + Φ 3 Φ 4 Φ 3 ))] = φ [Φ 4 + Φ 3 2Φ 4 Φ 3 ))] (2) β = + 4 2π 4 2π ( e V μ 2 2π [ 3 2π μ 4 4 μ V 3 2π ] dv = μ μ 3 3

14 348 M. Hofer and C. Boehm [ = ( ) V μ 2 V 2π μ 4 4 μ 4 4 ] π μ μ 3 3 dv (3) In general we can assume at 2 = 3 = 4 =, μ = μ2 = 0, and μ 3 = μ 4. Thus, β becomes: β = 2π [ ( ) + e V 2 μ ] ( ) V 2 μ dv 2 ( ) V 2 μ dv + ( ) V 2 μ dv dv (4) Check: =α + β Estimation of e Error Rate e: An error occurs, if one of e PUF-cells which were marked useful provides e wrong output. Like e total ratio of selected PUFs, e total error e(δv ) is e sum of e two partial errors e (ΔV )and e + (ΔV ). The following errors are evaluated at a certain e(δv ): e (ΔV )= α Φ 2[UF (UF + UF )] = = α Φ 2[φ ( Φ 4 ) φ Φ 3 ( Φ 4 )] (5) e + (ΔV )= α ( Φ 2)[UF + (UF + UF )] = = α ( Φ 2)[φ Φ 3 φ Φ 3 ( Φ 4 )], (6) where α is a normalization factor. e(δv )=e + (ΔV )+e (ΔV )= = α ( Φ 2)[φ Φ 3 φ Φ 3 ( Φ 4 )] + + α Φ 2[φ ( Φ 4 ) φ Φ 3 ( Φ 4 )] = = α {[φ Φ 2 φ Φ 2 Φ 4 φ Φ 2 Φ 3 + φ Φ 2 Φ 3 Φ 4 ]+

15 An Alternative to Error Correction for SRAM-Like PUFs 349 +[φ Φ 3 φ Φ 3 ( Φ 4 )] Φ 2 φ Φ 3 + Φ 2 φ Φ 3 ( Φ 4 )} = = α {φ Φ 2 φ Φ 2 Φ 4 φ Φ 2 Φ 3 Φ 4 + φ Φ 3 φ Φ 3 + φ Φ 3 Φ 4 Φ 2 φ Φ 3 + Φ 2 φ Φ 3 Φ 2 φ Φ 3 Φ 4 } (7) Table 2. Examples for e error rate e and e ratio of useful PUF-cells α. *The number in e brackets shows e BER wiout any pre-selection. num 2, 3, 4 μ 3 = μ 4 α e 30 mv mv( 0.7%*) 5mV E mv mv( 0.7%*) 0 mv e mv 2mV(.5%*) 0 mv E mv 2mV(.5%*0 mv e mv 5mV( 4%*) 0 mv mv 5mV( 4%*0 mv E mv 5mV( 4%*) 40 mv E-9 Table 3. Numeric examples of e error rate e and e ratio of useful PUF-cells α in dependence of μ 3,4( = 30mV, 2,3,4 = 6, 6 mv ). Wiout any pre-selection (μ 3,4 = 0mV) we get an error-rate of about 5%. μ 3,4(mV) e α μ 3,4(mV) e α E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E

16 350 M. Hofer and C. Boehm To get e error e over all e(δv ), e(δv ) has to be integrated over all ΔV : e = e(δv ) dδv (8) B Numerical Examples Table 2 shows some numeric examples for α and e. The number of useful PUFcells depends mainly on e ratio μ 3,4. The main factors for e error are 2,3,4 and μ 3,4. influences e error rate only marginally. Table 3 shows e in dependence of μ 3,4.