EVALUATION OF PHYSICAL UNCLONABLE FUNCTIONS

Size: px
Start display at page:

Download "EVALUATION OF PHYSICAL UNCLONABLE FUNCTIONS"

Transcription

1 EVALUATION OF PHYSICAL UNCLONABLE FUNCTIONS ECE 646 PROJECT PRESENTATION DEC 11, 2012 YAMINI RAVISHANKAR

2 PHYSICAL UNCLONABLE FUNCTIONS A challenge-response mechanism in which the mapping between a challenge and the corresponding response is dependent on the complex and variable nature of the physical material Unique challenge-response pairs for each chip

3 BIOMETRICS OF INTEGRATED CIRCUITS Identify individual PUF response Identify Integrated Circuit

4 WHY UNCLONABLE? Physical Unclonable Mathematical

5 TYPES OF PUFS Silicon Arbiter PUF Ring Oscillator based PUF Butterfly PUF SRAM based PUF Non-Silicon Coating PUF Magnetic PUF RF PUF

6 RING OSCILLATOR PUF r = 1 if Freq(ROi) > Freq(ROi+1) else r = 0

7 NOTATIONS USED N = total number of chips analyzed n = index of a chip (range 1 to N) M = total number of ring oscillators K = total number of identifiers(ids) generated per chip k = index of an ID in a chip (range 1 to K) T = total number of samples measured per ID t = index of a sample (range 1 to T) R = L-bit response from the PUF r = l th bit of the response R

8 DATA SETS COMPARED GMU Virginia Tech N (no of chips) M (no of ROs) K (no of Identifiers) L (length of response) T (no of samples) in configurable mode 512 in normal mode

9 CONFIGURABLE RING OSCILLATOR Each RO consists of 8 frequencies such as a look-up table GMU 2 datasets Horizontal scanning Vertical scanning

10 NEED FOR METRICS To evaluate the performance of different types of PUFs To be able to compare one PUF with the other To standardize the security requirements expected from the PUF

11 METRICS ANALYZED Uniqueness Bit-Aliasing Uniformity Randomness Reliability Correctness Steadiness Domains specified by Maiti et al. for the metrics

12 UNIQUENESS (DEVICE) Average inter-chip Hamming distance (HD) computed across a group of chips According to Maiti et al., Ideal value = 50% According to Hori et al., Ideal value = 100% Estimate of the inter-chip variation in terms of PUF responses

13 BIT ALIASING (DEVICE) Hamming weight of the l-th bit of the identifier across N devices Bit-aliasing is given by Ideal value = 50% Estimating the bias of a particular response bit across several chips Gives information about any systematic and spatial effect across several devices

14 UNIFORMITY (SPACE) Proportion of 0 s and 1 s in the response bits of a PUF Uniformity is given by Ideal Value = 50% Uniformity is the percentage Hamming Weight of the l- bit response Calculated for each chip individually from one response

15 RANDOMNESS (SPACE) Randomness indicates the balance of 0 and 1in the response bits of the PUF (Hori 2010) Randomness is given by Ideal value = 100% Similar to the uniformity parameter defined by Maiti et al. Takes into consideration T samples of the response bits

16 RELIABILITY (TIME) How reliable are the response bits at varying operating conditions Reliability is given by Ideal value = 100% Calculated based on the average value of the intrachip Hamming Distance Calculated over T samples for each chip

17 CORRECTNESS (TIME) Sum of the Hamming Distances (SHD) normalized by T, K and L Correctness is given by Ideal value = 100% Similar to the reliability parameter defined by Maiti et al. Can be correlated with the reliability parameter as Correctness = (2xReliability) - 1

18 STEADINESS (TIME) Degree of bias of a response bit towards 0 or 1 over T samples Steadiness is given by Ideal value = 100% Bias of individual response bits on an average Calculated for each individual bit in a response over T samples Does not take time factor into consideration

19 PARAMETERS NOT ANALYZED Diffuseness (space) Degree of difference among the IDs generated from the different challenge sets in the same device More than one identifier required to calculate the value of diffuseness Probability of Misidentification (device) Rate of error in the identification of a chip by a PUF due to noise in the response bits

20 CALCULATED METRICS Parameter Uniqueness Maiti Uniqueness Hori Ideal value (in %) Maiti thesis VT data (in %) VT Calculated values (in %) GMU - Horizontal GMU - Vertical Bit-aliasing Uniformity Randomness Reliability Correctness Steadiness

21 COMPARISON PLOTS Ideal Value Maiti thesis VT GMU - Horizontal GMU - Vertical 0

22 RESULTS AND ANALYSIS GMU PUF exhibits better reliability, steadiness and correctness in comparison with the VT data Uniformity and bit-aliasing of GMU PUF responses is closer to the ideal value than the VT responses Randomness is almost the same in both cases The uniqueness in the GMU data is very low. This can be attributed to the continuous strings of 0 s and 1 s in the identifiers The uniqueness of the GMU data can be improved by performing post-processing operations like Identity- Mapping and Quantization such that continuous strings of 1 s and 0 s are avoided

23 TIME SCHEDULE Oct Literature survey on the metrics available for evaluating PUFs Oct Familiarized with the scripting language Python to analyze the data Nov Worked on the GMU and VT data available and calculated the various metrics Nov Comparative analysis of the data Dec 11 Final Presentation

24 REFERENCES A. Maiti and P. Schaumont, Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive, Journal of Cryptology, DOI: /s Hori et.al., Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs, ReConfig2010, Pg

25 Thank you

Physically Unclonable Functions

Physically Unclonable Functions Physically Unclonable Functions Rajat Subhra Chakraborty Associate Professor Department of Computer Science and Engineering IIT Kharagpur E-mail: rschakraborty@cse.iitkgp.ernet.in ISEA Workshop IIT Kharagpur,

More information

Formal Design of Composite Physically Unclonable Function

Formal Design of Composite Physically Unclonable Function Formal Design of Composite Physically Unclonable Function Durga Prasad Sahoo Debdeep Mukhopadhyay Rajat Subhra Chakraborty Computer Science and Engineering Indian Institute of Technology, Kharagpur, India

More information

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs Yohei Hori, Takahiro Yoshida, Toshihiro atashita and Akashi Satoh Research Center for Information Security

More information

From Statistics to Circuits: Foundations for Future Physical Unclonable Functions

From Statistics to Circuits: Foundations for Future Physical Unclonable Functions From Statistics to Circuits: Foundations for Future Physical Unclonable Functions Inyoung Kim, Abhranil Maiti, Leyla Nazhandali, Patrick Schaumont, Vignesh Vivekraja, and Huaiye Zhang 1 Introduction Identity

More information

Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation

Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation Siarhei S. Zalivaka 1, Alexander V. Puchkov 2, Vladimir P. Klybik 2, Alexander A. Ivaniuk 2, Chip-Hong Chang 1 1 School

More information

Trapdoor Computational Fuzzy Extractors

Trapdoor Computational Fuzzy Extractors 1 Trapdoor Computational Fuzzy Extractors Charles Herder, Ling Ren, Marten van Dijk, Meng-Day (Mandel) Yu, Srinivas Devadas cherder@mit.edu, renling@mit.edu, vandijk@engr.uconn.edu, myu@verayo.com, devadas@mit.edu

More information

An Easy-to-Design PUF based on a Single Oscillator: the Loop PUF

An Easy-to-Design PUF based on a Single Oscillator: the Loop PUF An Easy-to-Design PUF based on a Single Oscillator: the Loop PUF Zhoua Cherif Jouini, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet To cite this version: Zhoua Cherif Jouini, Jean-Luc Danger, Sylvain

More information

MXPUF: Secure PUF Design against State-of-the-art Modeling Attacks

MXPUF: Secure PUF Design against State-of-the-art Modeling Attacks MXPUF: Secure PUF Design against State-of-the-art Modeling Attacks Phuong Ha Nguyen 1, Durga Prasad Sahoo 2, Chenglu Jin 1, Kaleel Mahmood 1, and Marten van Dijk 1 1 University of Connecticut, USA, 2 Robert

More information

Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches

Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches Dai Yamamoto 1, Kazuo Sakiyama 2, Mitsugu Iwamoto 2, Kazuo Ohta 2, Takao Ochiai 1, Masahiko Takenaka 1 and

More information

HELPER-LESS PHYSICALLY UNCLONABLE FUNCTIONS AND CHIP AUTHENTICATION. Riccardo Bernardini and Roberto Rinaldo

HELPER-LESS PHYSICALLY UNCLONABLE FUNCTIONS AND CHIP AUTHENTICATION. Riccardo Bernardini and Roberto Rinaldo 2014 IEEE International Conference on Acoustic, Speech and Signal Processing (ICASSP) HELPER-LESS PHYSICALLY UNCLONABLE FUNCTIONS AND CHIP AUTHENTICATION Riccardo Bernardini and Roberto Rinaldo DIEGM University

More information

Secure and Reliable Key Agreement with Physical Unclonable Functions

Secure and Reliable Key Agreement with Physical Unclonable Functions Article Secure and Reliable Key Agreement with Physical Unclonable Functions Onur Günlü 1, * ID, Tasnad Kernetzky 2 ID, Onurcan İşcan 3 ID, Vladimir Sidorenko 1 ID, Gerhard Kramer 1 ID, and Rafael F. Schaefer

More information

A Physical Unclonable Function derived from the power distribution system of an integrated circuit

A Physical Unclonable Function derived from the power distribution system of an integrated circuit University of New Mexico UNM Digital Repository Electrical and Computer Engineering ETDs Engineering ETDs 2-8-2011 A Physical Unclonable Function derived from the power distribution system of an integrated

More information

A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks

A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks Sensors 2014, 14, 11542-11556; doi:10.3390/s140711542 Article OPEN ACCESS sensors ISSN 1424-8220 www.mdpi.com/journal/sensors A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor

More information

An Accurate Probabilistic Reliability Model for Silicon PUFs

An Accurate Probabilistic Reliability Model for Silicon PUFs An Accurate Probabilistic Reliability Model for Silicon PUFs Roel Maes Intrinsic-ID, Eindhoven, the Netherlands roel.maes@intrinsic-id.com Abstract. The power of an accurate model for describing a physical

More information

Extracting Secret Keys from Integrated Circuits

Extracting Secret Keys from Integrated Circuits Extracting Secret Keys from Integrated Circuits Daihyun Lim April 5, 005 Abstract Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access

More information

Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs

Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs Variable-Length Bit Mapping and Error-Correcting Codes for Higher-Order Alphabet PUFs Vincent Immler 1, Matthias Hiller 1, Qinzhi Liu 1,2, Andreas Lenz 3, and Antonia Wachter-Zeh 3 1 Fraunhofer Institute

More information

An Alternative to Error Correction for SRAM-Like PUFs

An Alternative to Error Correction for SRAM-Like PUFs An Alternative to Error Correction for SRAM-Like PUFs Maximilian Hofer and Christoph Boehm Institute of Electronics, Graz University of Technology maximilian.hofer@tugraz.at, christoph.boehm@tugraz.at

More information

MINIATURIZATION and cost reduction of processors

MINIATURIZATION and cost reduction of processors This article has been accepted for This publication is the author's in a future version issue of of an this article journal, that has but been has not published been fully in this edited. journal. Content

More information

Eindhoven University of Technology MASTER. Entropy analysis of physical unclonable functions. van den Berg, R. Award date: Link to publication

Eindhoven University of Technology MASTER. Entropy analysis of physical unclonable functions. van den Berg, R. Award date: Link to publication Eindhoven University of Technology MASTER Entropy analysis of physical unclonable functions van den Berg, R. Award date: 2012 Link to publication Disclaimer This document contains a student thesis (bachelor's

More information

SUPPLEMENTARY INFORMATION

SUPPLEMENTARY INFORMATION Physically unclonable cryptographic primitives using self-assembled carbon nanotubes Zhaoying Hu, Jose Miguel M. Lobez Comeras, Hongsik Park, Jianshi Tang, Ali Afzali, George S. Tulevski, James B. Hannon,

More information

Obtaining Statistically Random Information from Silicon Physical Unclonable Functions

Obtaining Statistically Random Information from Silicon Physical Unclonable Functions Obtaining Statistically Random Information from Silicon Physical Unclonable Functions Chi-En Yin and Gang Qu Department of Electrical and Computer Engineering & Institute for Systems Research University

More information

DRV- Fingerprin,ng: Using Data Reten,on Voltage of SRAM Cells for Chip Iden,fica,on

DRV- Fingerprin,ng: Using Data Reten,on Voltage of SRAM Cells for Chip Iden,fica,on DRV- Fingerprin,ng: Using Data Reten,on Voltage of SRAM Cells for Chip Iden,fica,on Daniel E. Holcomb, UC Berkeley Amir Rahma,, UMass Amherst Mastooreh Salajegheh, UMass Amherst Wayne P. Burleson, UMass

More information

Extracting Secret Keys from Integrated Circuits

Extracting Secret Keys from Integrated Circuits Extracting Secret Keys from Integrated Circuits by Daihyun Lim Submitted to the Department of Electrical Engineering and Computer Science in partial fulfillment of the requirements for the degree of Master

More information

Entropy Evaluation for Oscillator-based True Random Number Generators

Entropy Evaluation for Oscillator-based True Random Number Generators Entropy Evaluation for Oscillator-based True Random Number Generators Yuan Ma DCS Center Institute of Information Engineering Chinese Academy of Sciences Outline RNG Modeling method Experiment Entropy

More information

Physically Uncloneable Functions in the Universal Composition Framework. Christina Brzuska Marc Fischlin Heike Schröder Stefan Katzenbeisser

Physically Uncloneable Functions in the Universal Composition Framework. Christina Brzuska Marc Fischlin Heike Schröder Stefan Katzenbeisser Physically Uncloneable Functions in the Universal Composition Framework Marc Fischlin Heike Schröder Stefan Katzenbeisser Security of s Optical Arbiter Coating Many other s bounded noise physically uncloneable

More information

Novel Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation

Novel Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation Novel trong PUF based on Nonlinearity of MOFET ubthreshold Operation Mukund Kalyanaraman and Michael Orshansky Department of Electrical and Computer Engineering The University of Texas at Austin email:{mukundkm,orshansky}@utexas.edu

More information

VLSI. Faculty. Srikanth

VLSI. Faculty. Srikanth J.B. Institute of Engineering & Technology Department of CSE COURSE FILE VLSI Faculty Srikanth J.B. Institute of Engineering & Technology Department of CSE SYLLABUS Subject Name: VLSI Subject Code: VLSI

More information

Algebraic Security Analysis of Key Generation with Physical Unclonable Functions

Algebraic Security Analysis of Key Generation with Physical Unclonable Functions Algebraic Security Analysis of Key Generation with Physical Unclonable Functions Matthias Hiller 1, Michael Pehl 1, Gerhard Kramer 2 and Georg Sigl 1,3 1 Chair of Security in Information Technology 2 Chair

More information

UNIVERSITY OF CONNECTICUT. CSE (15626) & ECE (15284) Secure Computation and Storage: Spring 2016.

UNIVERSITY OF CONNECTICUT. CSE (15626) & ECE (15284) Secure Computation and Storage: Spring 2016. Department of Electrical and Computing Engineering UNIVERSITY OF CONNECTICUT CSE 5095-004 (15626) & ECE 6095-006 (15284) Secure Computation and Storage: Spring 2016 Oral Exam: Theory There are three problem

More information

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND

More information

First Results and Realization Status of a Proton Computed Radiography Device

First Results and Realization Status of a Proton Computed Radiography Device First Results and Realization Status of a Proton Computed Radiography Device V. Sipala for the PRIMA collaboration V.Sipalaa,b, D.LoPrestia,b, N.Randazzob, M.Bruzzid,e, D.Menichellie,d, C.Civininid, M.Bucciolinic,d,

More information

SINCE the introduction of Arbiter Physically Unclonable

SINCE the introduction of Arbiter Physically Unclonable A Multiplexer based Arbiter PUF Composition with Enhanced Reliability and Security Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty, and Phuong Ha Nguyen Abstract Arbiter Physically Unclonable

More information

CSAIL. Computer Science and Artificial Intelligence Laboratory. Massachusetts Institute of Technology

CSAIL. Computer Science and Artificial Intelligence Laboratory. Massachusetts Institute of Technology CSAIL Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology Reliable Secret Sharing With Physical Random Functions Marten van Dijk, Daihyun Lim, Srinivas Devadas

More information

Quantum Computing. Separating the 'hope' from the 'hype' Suzanne Gildert (D-Wave Systems, Inc) 4th September :00am PST, Teleplace

Quantum Computing. Separating the 'hope' from the 'hype' Suzanne Gildert (D-Wave Systems, Inc) 4th September :00am PST, Teleplace Quantum Computing Separating the 'hope' from the 'hype' Suzanne Gildert (D-Wave Systems, Inc) 4th September 2010 10:00am PST, Teleplace The Hope All computing is constrained by the laws of Physics and

More information

Fibonacci Ring Oscillators as True Random Number Generators - A Security Risk. Markus Dichtl. Siemens Corporate Technology

Fibonacci Ring Oscillators as True Random Number Generators - A Security Risk. Markus Dichtl. Siemens Corporate Technology Fibonacci Ring Oscillators as True Random Number Generators - A Security Risk Markus Dichtl Siemens Corporate Technology Abstract. Fibonacci ring oscillators are shown to have a risk to oscillate periodically

More information

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2009 PROBLEM SET #7. Due (at 7 p.m.): Thursday, Dec. 10, 2009, in the EE C245 HW box in 240 Cory.

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2009 PROBLEM SET #7. Due (at 7 p.m.): Thursday, Dec. 10, 2009, in the EE C245 HW box in 240 Cory. Issued: Thursday, Nov. 24, 2009 PROBLEM SET #7 Due (at 7 p.m.): Thursday, Dec. 10, 2009, in the EE C245 HW box in 240 Cory. 1. Gyroscopes are inertial sensors that measure rotation rate, which is an extremely

More information

Practical Public PUF Enabled by Solving Max-Flow Problem on Chip

Practical Public PUF Enabled by Solving Max-Flow Problem on Chip Practical Public PUF Enabled by Solving Max-Flow Problem on Chip Meng Li 1, Jin Miao 2, Kai Zhong 3, David Z. Pan 1 1 Electrical and Computer Engineering Department, University of Texas at Austin, Austin,

More information

Prepared by: B.ELANGOVAN. M.Sc., M.Ed., M.Phil.,

Prepared by: B.ELANGOVAN. M.Sc., M.Ed., M.Phil., Book back One Mark questions And answers Prepared by: B.ELANGOVAN. M.Sc., M.Ed., M.Phil., (Tamil Nadu Dr. Radhakrishnan Best Teacher Award - 2011 recipient) Post Graduate Teacher in Physics ( Date of Appointment

More information

A Formal Foundation for the Security Features of Physical Functions

A Formal Foundation for the Security Features of Physical Functions 2011 IEEE Symposium on Security and Privacy A Formal Foundation for the Security Features of Physical Functions Frederik Armknecht, Roel Maes, Ahmad-Reza Sadeghi, François-Xavier Standaert, and Christian

More information

DFT & Fast Fourier Transform PART-A. 7. Calculate the number of multiplications needed in the calculation of DFT and FFT with 64 point sequence.

DFT & Fast Fourier Transform PART-A. 7. Calculate the number of multiplications needed in the calculation of DFT and FFT with 64 point sequence. SHRI ANGALAMMAN COLLEGE OF ENGINEERING & TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR,TRICHY-621105. DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING UNIT I DFT & Fast Fourier

More information

A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation

A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation Congbing Li Haruo Kobayashi Gunma University Gunma University Kobayashi Lab Outline Research Objective & Background

More information

CMOS Inverter. Performance Scaling

CMOS Inverter. Performance Scaling Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS

More information

EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 9

EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 9 EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 9 Name: Instructions: Write your name and section number on all pages Closed book, closed notes; Computers and cell phones are not allowed You can

More information

PHYSICAL UNCLONEABLE FUNCTION HARDWARE KEYS UTILIZING KIRCHHOFF-LAW- JOHNSON-NOISE SECURE KEY EXCHANGE AND NOISE-BASED LOGIC

PHYSICAL UNCLONEABLE FUNCTION HARDWARE KEYS UTILIZING KIRCHHOFF-LAW- JOHNSON-NOISE SECURE KEY EXCHANGE AND NOISE-BASED LOGIC July 26, 2013; second version. PHYSICAL UNCLONEABLE FUNCTION HARDWARE KEYS UTILIZING KIRCHHOFF-LAW- JOHNSON-NOISE SECURE KEY EXCHANGE AND NOISE-BASED LOGIC LASZLO B. KISH (1), CHIMAN KWAN (2) (1) Texas

More information

Introduction to CMOS RF Integrated Circuits Design

Introduction to CMOS RF Integrated Circuits Design V. Voltage Controlled Oscillators Fall 2012, Prof. JianJun Zhou V-1 Outline Phase Noise and Spurs Ring VCO LC VCO Frequency Tuning (Varactor, SCA) Phase Noise Estimation Quadrature Phase Generator Fall

More information

Course Name: Digital Signal Processing Course Code: EE 605A Credit: 3

Course Name: Digital Signal Processing Course Code: EE 605A Credit: 3 Course Name: Digital Signal Processing Course Code: EE 605A Credit: 3 Prerequisites: Sl. No. Subject Description Level of Study 01 Mathematics Fourier Transform, Laplace Transform 1 st Sem, 2 nd Sem 02

More information

EECS150 - Digital Design Lecture 26 - Faults and Error Correction. Types of Faults in Digital Designs

EECS150 - Digital Design Lecture 26 - Faults and Error Correction. Types of Faults in Digital Designs EECS150 - Digital Design Lecture 26 - Faults and Error Correction April 25, 2013 John Wawrzynek 1 Types of Faults in Digital Designs Design Bugs (function, timing, power draw) detected and corrected at

More information

Efficient electron transport on helium with silicon integrated circuits

Efficient electron transport on helium with silicon integrated circuits Efficient electron transport on helium with silicon integrated circuits - - + - - Forrest Bradbury 1 and Maika Takita 1, Kevin Eng 2, Tom M Gurrieri 2, Kathy J Wilkel 2, Stephen A Lyon 1 1 Princeton University

More information

EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 16

EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 16 EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 16 Instructions: Write your name and section number on all pages Closed book, closed notes; Computers and cell phones are not allowed You can use

More information

ECE 645: Lecture 3. Conditional-Sum Adders and Parallel Prefix Network Adders. FPGA Optimized Adders

ECE 645: Lecture 3. Conditional-Sum Adders and Parallel Prefix Network Adders. FPGA Optimized Adders ECE 645: Lecture 3 Conditional-Sum Adders and Parallel Prefix Network Adders FPGA Optimized Adders Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 7.4, Conditional-Sum

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Exam 1 ` March 22, 2018

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Exam 1 ` March 22, 2018 Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Exam 1 ` March 22, 2018 INSTRUCTIONS: Every problem must be done in the separate booklet Only

More information

Generation of True Random Numbers using quasi-monte Carlo methods

Generation of True Random Numbers using quasi-monte Carlo methods Generation of True Random Numbers using quasi-monte Carlo methods Ana I Gomez, Domingo Gómez-Pérez, Florian Pausinger Universidad de Cantabria, Queen s University Belfast MCQMC 2018 Ana I Gomez, Domingo

More information

Acknowledgements. Control System. Tracking. CS122A: Embedded System Design 4/24/2007. A Simple Introduction to Embedded Control Systems (PID Control)

Acknowledgements. Control System. Tracking. CS122A: Embedded System Design 4/24/2007. A Simple Introduction to Embedded Control Systems (PID Control) Acknowledgements A Simple Introduction to Embedded Control Systems (PID Control) The material in this lecture is adapted from: F. Vahid and T. Givargis, Embedded System Design A Unified Hardware/Software

More information

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits

Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits E = B; H = J + D D = ρ ; B = 0 D = ρ ; B = 0 Yehia Massoud ECE Department Rice University Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits ECE Affiliates 10/8/2003 Background: Integrated

More information

Example: vending machine

Example: vending machine Example: vending machine Release item after 15 cents are deposited Single coin slot for dimes, nickels o change Reset Coin Sensor Vending Machine FSM Open Release Mechanism Clock Spring 2005 CSE370 - guest

More information

0 volts. 2 volts. 5 volts

0 volts. 2 volts. 5 volts CS101 Binary Storage Devices and Boolean Logic Now that we have discussed number representation, why do computers use the binary representation and not something we are more familiar with, like decimal?

More information

PERFORMANCE ANALYSIS OF CLA CIRCUITS USING SAL AND REVERSIBLE LOGIC GATES FOR ULTRA LOW POWER APPLICATIONS

PERFORMANCE ANALYSIS OF CLA CIRCUITS USING SAL AND REVERSIBLE LOGIC GATES FOR ULTRA LOW POWER APPLICATIONS PERFORMANCE ANALYSIS OF CLA CIRCUITS USING SAL AND REVERSIBLE LOGIC GATES FOR ULTRA LOW POWER APPLICATIONS K. Prasanna Kumari 1, Mrs. N. Suneetha 2 1 PG student, VLSI, Dept of ECE, Sir C R Reddy College

More information

ELEC 3908, Physical Electronics, Lecture 27. MOSFET Scaling and Velocity Saturation

ELEC 3908, Physical Electronics, Lecture 27. MOSFET Scaling and Velocity Saturation ELEC 3908, Physical Electronics, Lecture 27 MOSFET Scaling and Velocity Saturation Lecture Outline Industry push is always to pack more devices on a chip to increase functionality, which requires making

More information

Fault Injection Modeling Attacks on 65nm Arbiter and RO Sum PUFs via Environmental Changes

Fault Injection Modeling Attacks on 65nm Arbiter and RO Sum PUFs via Environmental Changes Fault Injection Modeling Attacks on 65nm Arbiter and RO Sum PUFs via Environmental Changes Jeroen Delvaux and Ingrid Verbauwhede ESAT/SCD-COSIC and iminds, KU Leuven Kasteelpark Arenberg, B-3 Leuven-Heverlee,

More information

Technical note on seasonal adjustment for M0

Technical note on seasonal adjustment for M0 Technical note on seasonal adjustment for M0 July 1, 2013 Contents 1 M0 2 2 Steps in the seasonal adjustment procedure 3 2.1 Pre-adjustment analysis............................... 3 2.2 Seasonal adjustment.................................

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

Trapdoor Computational Fuzzy Extractors and Stateless Cryptographically-Secure Physical Unclonable Functions

Trapdoor Computational Fuzzy Extractors and Stateless Cryptographically-Secure Physical Unclonable Functions IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING, VOL. 14, NO. 1, JANUARY/FEBRUARY 2017 65 Trapdoor Computational Fuzzy Extractors and Stateless Cryptographically-Secure Physical Unclonable Functions

More information

Entropy Extraction in Metastability-based TRNG

Entropy Extraction in Metastability-based TRNG Entropy Extraction in Metastability-based TRNG Vikram B. Suresh Dept. of Electrical & Computer Engineering University of Massachusetts Amherst, USA vsuresh@ecs.umass.edu Wayne P. Burleson Dept. of Electrical

More information

Design of Secure TRNGs for Cryptography Past, Present, and Future

Design of Secure TRNGs for Cryptography Past, Present, and Future Design of Secure TRNGs for Cryptography Past, Present, and Future Viktor FISCHER Univ Lyon, UJM-Saint-Etienne, CNRS Laboratoire Hubert Curien UMR 5516 F-42023, SAINT-ETIENNE, France fischer@univ-st-etienne.fr

More information

Information Redundancy: Coding

Information Redundancy: Coding Info Redundancy April 2, 23 Information Redundancy: Coding Often applied to Info transfer: often serial communication thru a channel Info storage Hamming distance: error detection & correction capability

More information

EECS150 - Digital Design Lecture 26 Faults and Error Correction. Recap

EECS150 - Digital Design Lecture 26 Faults and Error Correction. Recap EECS150 - Digital Design Lecture 26 Faults and Error Correction Nov. 26, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof.

More information

Atomic-Photonic Integration (A-PhI) A-Φ Proposers Day

Atomic-Photonic Integration (A-PhI) A-Φ Proposers Day Atomic-Photonic Integration (A-PhI) A-Φ Proposers Day Dr. John Burke Microsystems Technology Office (MTO) 1 August 2018 1 What is A-PhI? Atomic physics allows for accurate and sensitive measurements. Supporting

More information

RELIABLE BIOMETRIC AUTHENTICATION WITH PRIVACY PROTECTION

RELIABLE BIOMETRIC AUTHENTICATION WITH PRIVACY PROTECTION RELIABLE BIOMETRIC AUTHENTICATION WITH PRIVACY PROTECTION E. VERBITSKIY, P. TUYLS, D. DENTENEER, J.P. LINNARTZ PHILIPS RESEARCH LABORATORIES PROF. HOLSTLAAN 4, AA 5656 EINDHOVEN, THE NETHERLANDS {EVGENY.VERBITSKIY,PIM.TUYLS,DEE.DENTENEER,J.P.LINNARTZ@PHILIPS.COM}

More information

JFETs - MESFETs - MODFETs

JFETs - MESFETs - MODFETs Technische Universität raz Institute of Solid State Physics JFETs - MESFETs - MOFETs JFET n n-channel JFET S n-channel JFET x n 2 ( Vbi V) en S p-channel JFET 2 Pinch-off at h = x en n h Vp 2 V p = pinch-off

More information

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits

Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits Afshin Abdollahi University of Southern California Farzan Fallah Fuitsu Laboratories of America Massoud Pedram University of Southern

More information

Secure Key Generation from Biased PUFs

Secure Key Generation from Biased PUFs Secure Key Generation from Biased PUFs Roel Maes 1, Vincent van der Leest 1, Erik van der Sluis 1, and Frans Willems 2 1 Intrinsic-ID, Eindhoven, Netherlands {roel.maes, vincent.van.der.leest, erik.van.der.sluis}@intrinsic-id.com

More information

CDs Have Fingerprints Too

CDs Have Fingerprints Too CDs Have Fingerprints Too Ghaith Hammouri 1, Aykutlu Dana 2, and Berk Sunar 1 1 CRIS Lab, Worcester Polytechnic Institute 100 Institute Road, Worcester, MA 01609-2280 {hammouri,sunar}@wpi.edu 2 UNAM, Institute

More information

II/IV B.Tech. DEGREE EXAMINATIONS, NOV/DEC-2017

II/IV B.Tech. DEGREE EXAMINATIONS, NOV/DEC-2017 CSE/IT 213 (CR) Total No. of Questions :09] [Total No. of Pages : 03 II/IV B.Tech. DEGREE EXAMINATIONS, NOV/DEC-2017 First Semester CSE/IT BASIC ELECTRICAL AND ELECTRONICS ENGINEERING Time: Three Hours

More information

R&T PROTON DIRECT IONIZATION

R&T PROTON DIRECT IONIZATION R&T PROTON DIRECT IONIZATION Assessment of the Direct Ionization Contribution to the Proton SEU Rate N. Sukhaseum,, J. Guillermin,, N. Chatry, F. Bezerra and R. Ecoffet TRAD, Tests & Radiations Introduction

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing!

More information

Secure Goods Supply Chain and Key Exchange with Virtual Proof of Reality

Secure Goods Supply Chain and Key Exchange with Virtual Proof of Reality Secure Goods Supply Chain and Key Exchange with Virtual Proof of Reality Yansong Gao 1,2, Damith C. Ranasinghe 2, Said F. Al-Sarawi 1, and Derek Abbott 1 1 School of Electrical and Electronic Engineering,

More information

Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories

Digital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification

More information

MP112D GHz GaAs MMIC Attenuator. Datasheet

MP112D GHz GaAs MMIC Attenuator. Datasheet MP112D 0.1-15 GHz GaAs MMIC Attenuator Datasheet MP112D 0.1-15 GHz GaAs MMIC Attenuator MAIN FEATURES Operating range 0.1 to 15 GHz Insertion loss 4.5 db at 10 GHz Attenuation range 31.5 db (6 bit, 64

More information

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation Jeroen Delvaux and Ingrid Verbauwhede ESAT/COSIC and iminds, KU Leuven Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee,

More information

FPGA-based Niederreiter Cryptosystem using Binary Goppa Codes

FPGA-based Niederreiter Cryptosystem using Binary Goppa Codes FPGA-based Niederreiter Cryptosystem using Binary Goppa Codes Wen Wang 1, Jakub Szefer 1, and Ruben Niederhagen 2 1. Yale University, USA 2. Fraunhofer Institute SIT, Germany April 9, 2018 PQCrypto 2018

More information

Breakdown Characterization

Breakdown Characterization An Array-Based Test Circuit it for Fully Automated Gate Dielectric Breakdown Characterization John Keane, Shrinivas Venkatraman, Paulo Butzen*, and Chris H. Kim *State University of Rio Grande do Sul,

More information

Using a Mercury itc with thermocouples

Using a Mercury itc with thermocouples Technical Note Mercury Support Using a Mercury itc with thermocouples Abstract and content description This technical note describes how to make accurate and reliable temperature measurements using an

More information

Introduction. Entropy and Security

Introduction. Entropy and Security Truth in Randomness Practical Insights on Randomness, the Nature of the Universe, and Using Ring Oscillators as Entropy Sources for High-Security Applications December 2011 Introduction Most engineers

More information

Algebraic Codes for Error Control

Algebraic Codes for Error Control little -at- mathcs -dot- holycross -dot- edu Department of Mathematics and Computer Science College of the Holy Cross SACNAS National Conference An Abstract Look at Algebra October 16, 2009 Outline Coding

More information

COURSE OUTLINE. Upon completion of this course the student will be able to:

COURSE OUTLINE. Upon completion of this course the student will be able to: 1 School of Arts & Science PHYSICS DEPARTMENT PHYS 210-01/02 2016Q1 COURSE OUTLINE Instructor Information (a) Instructor: Dr. Julie Alexander (b) Office Hours: M:9:30, T:10:30, Th:2:30, F:11:30 (c) Location:

More information

Analytical Optimization of High Performance and High Quality Factor MEMS Spiral Inductor

Analytical Optimization of High Performance and High Quality Factor MEMS Spiral Inductor Progress In Electromagnetics Research M, Vol. 34, 171 179, 2014 Analytical Optimization of High Performance and High Quality Factor MEMS Spiral Inductor Parsa Pirouznia * and Bahram Azizollah Ganji Abstract

More information

ECE 512 Digital System Testing and Design for Testability. Model Solutions for Assignment #3

ECE 512 Digital System Testing and Design for Testability. Model Solutions for Assignment #3 ECE 512 Digital System Testing and Design for Testability Model Solutions for Assignment #3 14.1) In a fault-free instance of the circuit in Fig. 14.15, holding the input low for two clock cycles should

More information

Read-Proof Hardware from Protective Coatings

Read-Proof Hardware from Protective Coatings Read-Proof Hardware from Protective Coatings Pim Tuyls, Geert-Jan Schrijen, Boris Škorić, Jan van Geloven, Nynke Verhaegh, and Rob Wolters Philips Research Laboratories, The Netherlands Abstract. In cryptography

More information

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation

Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation Key-recovery Attacks on Various RO PUF Constructions via Helper Data Manipulation Jeroen Delvaux and Ingrid Verbauwhede ESAT/COSIC and iminds, KU Leuven Kasteelpark Arenberg 10, B-001 Leuven-Heverlee,

More information

Analysis of Some Quasigroup Transformations as Boolean Functions

Analysis of Some Quasigroup Transformations as Boolean Functions M a t h e m a t i c a B a l k a n i c a New Series Vol. 26, 202, Fasc. 3 4 Analysis of Some Quasigroup Transformations as Boolean Functions Aleksandra Mileva Presented at MASSEE International Conference

More information

Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults

Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Dictionary-Less Defect Diagnosis as Surrogate Single Stuck-At Faults Chidambaram Alagappan and Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849,

More information

ALIGNMENT RESULT FOR MAGNET UNITS OF THE SPRING-8 STORAGE RING

ALIGNMENT RESULT FOR MAGNET UNITS OF THE SPRING-8 STORAGE RING ALIGNMENT RESULT FOR MAGNET UNITS OF THE SPRING-8 STORAGE RING Chao ZHANG, Sakuo MATSUI, Jun-ichi OHNISHI and Koji TSUMAKI SPring-8, Kamigori, Ako-gun, Hyogo 678-12, Japan 1. INTRODUCTION Magnet installation

More information

EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 12

EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 12 EECE 2150 Circuits and Signals Final Exam Fall 2016 Dec 12 Instructions: Write your name and section number on all pages Closed book, closed notes; Computers and cell phones are not allowed You can use

More information

Jitter Decomposition in Ring Oscillators

Jitter Decomposition in Ring Oscillators Jitter Decomposition in Ring Oscillators Qingqi Dou Jacob A. Abraham Computer Engineering Research Center Computer Engineering Research Center The University of Texas at Austin The University of Texas

More information

An Introduction to Low Density Parity Check (LDPC) Codes

An Introduction to Low Density Parity Check (LDPC) Codes An Introduction to Low Density Parity Check (LDPC) Codes Jian Sun jian@csee.wvu.edu Wireless Communication Research Laboratory Lane Dept. of Comp. Sci. and Elec. Engr. West Virginia University June 3,

More information

Design and Implementation of Carry Adders Using Adiabatic and Reversible Logic Gates

Design and Implementation of Carry Adders Using Adiabatic and Reversible Logic Gates Design and Implementation of Carry Adders Using Adiabatic and Reversible Logic Gates B.BharathKumar 1, ShaikAsra Tabassum 2 1 Research Scholar, Dept of ECE, Lords Institute of Engineering & Technology,

More information

MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application

MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application 2011 11th Non-Volatile Memory Technology Symposium @ Shanghai, China, Nov. 9, 20112 MTJ-Based Nonvolatile Logic-in-Memory Architecture and Its Application Takahiro Hanyu 1,3, S. Matsunaga 1, D. Suzuki

More information

Status of the LHCb RICH and hadron particle identification

Status of the LHCb RICH and hadron particle identification Status of the LHCb RICH and hadron particle identification M. Adinolfi University of Oxford On behalf of the LHCb collaboration (with many thanks to all the people whose presentations have been n hacked)

More information

A Fourier Analysis Based Attack against Physically Unclonable Functions

A Fourier Analysis Based Attack against Physically Unclonable Functions A Fourier Analysis Based Attack against Physically Unclonable Functions Fatemeh Ganji, Shahin Tajik, Jean-Pierre Seifert Security in Telecommunications Technische Universität Berlin Germany {fganji,stajik,jpseifert}@sec.t-labs.tu-berlin.de

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive

More information