Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation
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1 Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation Siarhei S. Zalivaka 1, Alexander V. Puchkov 2, Vladimir P. Klybik 2, Alexander A. Ivaniuk 2, Chip-Hong Chang 1 1 School of Electrical and Electronic Engineering Nanyang Technological University 2 Faculty of Computer Systems and Networks Belarusian State University of Informatics and Radioelectronics January 28, /35
2 Outline 1 Introduction 2 Arbiter PUF Architecture 3 Multi-Arbiter PUF with Enhanced Response Set 4 Metastability Detection 5 Experimental Results 6 Conclusion and future works 2/35
3 Introduction 3/35
4 Counterfeiting * Intellectual Property Rights Seizures Statistics Fiscal Year /35
5 Counterfeiting * Intellectual Property Rights Seizures Statistics Fiscal Year /35
6 Counterfeiting * Intellectual Property Rights Seizures Statistics Fiscal Year /35
7 Physical Unclonable Function (PUF) as a security primitive Classic Unique Physical Property Measurement Method Authentication Key Generation Silicon 5/35
8 Reliability Issues 6/35
9 Reliability Issues Error Correction Codes 6/35
10 Reliability Issues Error Correction Codes Structure Enhancement 6/35
11 Arbiter PUF Architecture 7/35
12 Classical Arbiter PUF architecture A-PUF L L n L N Arb N D Q C LR R Ch 1 Ch n Ch N Init Control * J. Lee, D. Lim, B. Gassend, G. E. Suh, M. van Dijk, S. Devadas A technique to build a secret key in integrated circuits for identification and authentication applications, VLSIC 04 (Conference), June /35
13 Classical Arbiter PUF architecture A-PUF L L n L N Arb N D Q C LR R Ch 1 Ch n Ch N Init Control * J. Lee, D. Lim, B. Gassend, G. E. Suh, M. van Dijk, S. Devadas A technique to build a secret key in integrated circuits for identification and authentication applications, VLSIC 04 (Conference), June /35
14 Classical Arbiter PUF architecture A-PUF L L n L N Arb N D Q C LR R Ch 1 Ch n Ch N Init Control * J. Lee, D. Lim, B. Gassend, G. E. Suh, M. van Dijk, S. Devadas A technique to build a secret key in integrated circuits for identification and authentication applications, VLSIC 04 (Conference), June /35
15 Classical Arbiter PUF architecture A-PUF L L n L N Arb N D Q C LR R Ch 1 Ch n Ch N Init Control Reliability is * J. Lee, D. Lim, B. Gassend, G. E. Suh, M. van Dijk, S. Devadas A technique to build a secret key in integrated circuits for identification and authentication applications, VLSIC 04 (Conference), June /35
16 Metastability 9/35
17 Efforts Big Challenge Size 10/35
18 Efforts Only One Bit Response Big Challenge Size 10/35
19 Multi-Arbiter PUF with Enhanced Response Set 11/35
20 Multi-arbiter PUF Architecture MA-PUF 1 Control TPG LFSR N S Challenge... Arb1 Arb2... L 1 L L N Ch 1 Ch 2... Ch N Challenge ArbN MUX Adr R REG D Responses MA-PUF D R D D * V. P. Klybik, A. A. Ivaniuk Use of Arbiter Physical Unclonable Function to solve identification problem of digital device, AC& CS (Journal), May /35
21 Multiplexer chain length investigation Uniqueness Sokal-Michener dist. Reliability 13/35
22 Multiplexer chain length investigation Uniqueness Sokal-Michener dist. Reliability For arbiter index greater than 16, PUF figures of merit became stable and vary within a narrow range. * Gray colored bars represent average values, Black colored minimal. 13/35
23 Metastability Detection 14/35
24 Identification of metastable arbiter bits 15/35
25 4-DFF based arbiter MA-PUF d Ln Arb n D Q D Q D Q D Q R 3 d,n CLR CLR CLR CLR R 2 d,n R 1 d,n R 0 d,n Ch n Init Control 16/35
26 4-DFF based arbiter MA-PUF d Ln Ch n Arb n D Q CLR Init D Q CLR Control D CLR Q D CLR Q R 3 d,n R 2 d,n R 1 d,n R 0 d,n S 1 S 2 S 1 S 2 Stable zero Stable one R 0 d,n=1 R 1 d,n=0 R 2 d,n=0 R 3 d,n=1 R 0 d,n=0 R 1 d,n=1 R 2 d,n=1 R 3 d,n=0 16/35
27 4-DFF outputs distribution 17/35
28 SR latch based arbiter MA-PUF d L n Arb n 1 D Q CLR D Q C LR R 0 d,n R 1 d,n CLR Ch n Control Init 18/35
29 SR latch based arbiter MA-PUF d L n Arb n 1 D Q CLR D Q C LR R 0 d,n R 1 d,n CLR Ch n Control Init Rd,n 0 = 0, R1 d,n = 0 stable one 18/35
30 SR latch based arbiter MA-PUF d L n Arb n 1 D Q CLR D Q C LR R 0 d,n R 1 d,n CLR Ch n Control Init Rd,n 0 = 0, R1 d,n = 0 stable one Rd,n 0 = 1, R1 d,n = 0 stable zero 18/35
31 SR latch based arbiter MA-PUF d L n Arb n 1 D Q CLR D Q C LR R 0 d,n R 1 d,n CLR Ch n Control Init Rd,n 0 = 0, R1 d,n = 0 stable one Rd,n 0 = 1, R1 d,n = 0 stable zero Rd,n 0 = 1, R1 d,n = 1 high frequency oscillation (HFO) 18/35
32 Damping oscillation detection Each metastable output is unique and repeatable for particular challenge: 19/35
33 Damping oscillation detection Each metastable output is unique and repeatable for particular challenge: 19/35
34 Damping oscillation detection Each metastable output is unique and repeatable for particular challenge: The frequency can be roughly measured by a counter. 19/35
35 SR latch based arbiter with a counter MAPUF d L n Arb n CNT +1 Q 8 R d,n C LR Ch n Control Init * T. Kacprzak Analysis of Oscillatory Metastable of an RS Flip-Flop, IEEE SSC (Journal), February /35
36 Experimental Results 21/35
37 Experimental equipment 10 Digilent Nexys-4 Artix-7 FPGA boards. Data transferred via UART interface. CAD Xilinx ISE Scripts in C# and Python. 30 experiments with 10,000 challenges applied. 22/35
38 Experiment Structure /35
39 Figures of merit for PUF designs Uniqueness. Reliability. Randomness. 24/35
40 Figures of merit for PUF designs Uniqueness. Reliability. Randomness. Sokal-Michener Distance (similar to Uniqueness). 24/35
41 Experimental results. Uniqueness Let R u and R v two n-bit responses generated by different PUF instances for the same challenge. Uniqueness for the m PUF instances can be computed by: m 1 m u=1 v=u+1 2 U = m(m 1) The ideal value is 0.5. HD(R u,r v ) n Type of arbiter DFF (Classical) 4 DFF SR latch Uniqueness /35
42 Distance metrics modification with respect to metastability Values 0 1 X X Variable v 1 (i)v 2 (i) a 11 b 01 c 10 d 00 e XX f 0X g X 0 h 1X i X 1 26/35
43 Distance metrics modification with respect to metastability Values 0 1 X X Variable v 1 (i)v 2 (i) a 11 b 01 c 10 d 00 e XX f 0X g X 0 h 1X i X 1 26/35
44 Experimental results. Sokal-Michener distance This is also a metric to estimate uniqueness. Let v 1 and v 2 are two ternary vectors. The Sokal-Michener distance can be computed as follows: 0.5 (f +g+h+i) + m = D Sokal Michener = b+c m The ideal value is (b+c)+f +g+h+i 2 m Type of arbiter DFF (Classical) 4 DFF SR latch Average Minimum /35
45 Experimental results. Reliability Reliability measures the temporal reproducibility of the responses. Let R i is a reference response of size n. E = 30 tests were done. Each element can be computed as follows: R i = max(n 0,n 1,n X ) n 0 +n 1 +n X Let R i,e is the response at different time e. The reliability S can be computed by: S = 1 BER = 1 1 E E e=1 HD(R i,r i,e ) n Type of arbiter DFF (Classical) 4 DFF SR latch Average Minimum /35
46 Experimental results. Randomness The NIST test results Test Description Passed/Total P-value 4-DFF SR 4-DFF SR Frequency (Monobit) Test 100/ / Frequency Test within a Block 100/ / Runs Test 100/ / Test for the Longest Run of Ones in a Block 100/ / Binary Matrix Rank Test 100/ / Discrete Fourier Transform (Spectral) Test 100/ / Non-overlapping Template Matching Test 97/100 98/ Overlapping Template Matching Test 100/ / Maurer s Universal Statistical Test 100/ / Serial Test 100/ / Cumulative Sums (Cusum) Test 100/ / Random Excursions Test 10/10 10/10 Random Excursions Variant Test 10/10 10/10 29/35
47 Hardware overhead analysis Component # slice LUTs # slice registers A-PUF 256 / / MA-PUF 298 / / DFF 302 / / SR latch 506 / / Entire system 2494 / / /35
48 Hardware overhead analysis Component # slice LUTs # slice registers A-PUF 256 / / MA-PUF 298 / / DFF 302 / / SR latch 506 / / Entire system 2494 / / Less than 0.4% of logic slices and 0.4% of registers. 30/35
49 Hardware overhead analysis Component # slice LUTs # slice registers A-PUF 256 / / MA-PUF 298 / / DFF 302 / / SR latch 506 / / Entire system 2494 / / Less than 0.4% of logic slices and 0.4% of registers. Flexibility to choose different arbiter outputs. 30/35
50 Correlations analysis Arb i /35
51 Correlations analysis Arb i The average correlation per Arbiter is 29 out of /35
52 Correlations analysis Arb i The average correlation per Arbiter is 29 out of 128. The minimum 3 out of /35
53 Correlations analysis Arb i The average correlation per Arbiter is 29 out of 128. The minimum 3 out of 128. The maximum 78 out of /35
54 Conclusion and future works 32/35
55 Contributions Reconfigurable multi-response A-PUF design with enhanced response alphabet. Two metastability detection techniques. Adopted PUF figures of merit. 33/35
56 Future works Simulate proposed design on ASIC platform. Test the PUF under varying operational conditions. Check the vulnerability to modeling attacks (machine learning attacks). Arbiter choosing algorithm considering correlation. Develop the high level concept of metastability detection. 34/35
57 Thanks and Q & A 35/35
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