Distinguishing Manufacturing Defects From Variability Induced Faults in Analog Circuits

Transcription

1 Distinguishing Manufacturing Defects From Variability Induced Faults in Analog Circuits Suraj Sindia Vishwani D. Agrawal Dept. of ECE, Auburn University, AL, USA Virendra Singh Indian Institute of Science, Bangalore, India March 16, 2011 Suraj SSST2011 1/ 22

2 Outline 1 Motivation 2 Coefficient Based Test 3 Fault Classification 4 Results Suraj SSST2011 2/ 22

3 Outline 1 Motivation 2 Coefficient Based Test 3 Fault Classification 4 Results Suraj SSST2011 3/ 22

4 Fault Classification Motivation 1 Semiconductor processes at advanced nodes are subject to random variability Poly/thin film resistors - line edge roughness (σ 15%µ) Capacitors - Oxide thickness fluctuation & line edge roughness (σ 20%µ) Suraj SSST2011 4/ 22

5 Fault Classification Motivation 1 Semiconductor processes at advanced nodes are subject to random variability Poly/thin film resistors - line edge roughness (σ 15%µ) Capacitors - Oxide thickness fluctuation & line edge roughness (σ 20%µ) 2 Faults due to variability can mask or exacerbate failure from conventional defect mechanisms. Dust contamination, Processing Equipment, Material impurity, Clean room contamination, Operator imperfection, etc., (Fault sizes µ dev > 50%) Suraj SSST2011 4/ 22

6 Fault Classification Motivation 1 Semiconductor processes at advanced nodes are subject to random variability Poly/thin film resistors - line edge roughness (σ 15%µ) Capacitors - Oxide thickness fluctuation & line edge roughness (σ 20%µ) 2 Faults due to variability can mask or exacerbate failure from conventional defect mechanisms. Dust contamination, Processing Equipment, Material impurity, Clean room contamination, Operator imperfection, etc., (Fault sizes µ dev > 50%) 3 Distinguishing failure mechanisms between process variation (PV) and conventional ones can possibly help improve yield. Suraj SSST2011 4/ 22

7 Types Of Faults Suraj SSST2011 5/ 22

8 Ideal Test For An Analog Circuit Wish list for an analog circuit test scheme Suitable for large class of circuits Detects sufficiently small parametric faults high sensitivity Low design complexity of the input signal Small area overhead requires little circuit augmentation Large number observables handy in diagnosis Suraj SSST2011 6/ 22

9 Ideal Test For An Analog Circuit Wish list for an analog circuit test scheme Suitable for large class of circuits Detects sufficiently small parametric faults high sensitivity Low design complexity of the input signal Small area overhead requires little circuit augmentation Large number observables handy in diagnosis Aids distinction of small defects from process variation (PV) induced faults need in advanced tech nodes Suraj SSST2011 6/ 22

10 Outline 1 Motivation 2 Coefficient Based Test 3 Fault Classification 4 Results Suraj SSST2011 7/ 22

11 Cascaded Amplifiers An Example Vdd R1 I M1 R2 I M2 V out M1 M2 V in Two stage amplifier with 4 th degree non-linearity in V in v out = c 0 + c 1 v in + c 2 v 2 in + c 3v 3 in + c 4v 4 in S. Sindia, V. Singh and V. D. Agrawal, Polynomial Coefficient Based DC Testing of Nonlinear Analog Circuits, pp.69-74, GLSVLSI Suraj SSST2011 8/ 22

12 Polynomial Coefficients ( ) [ W c 0 = V DD R 2 K L 2 ( ) [ ( W W c 1 = R 2 K 4R 2 L 1K 2 2 L ( ) [ W c 2 = R 2 K L 2 (V DD V T ) 2 + R1 2K ( ) ] 2 W 2 ( L 1 V T 4 2(V DD V T )R W ) 1 L 1 V T 2 ( ) W VT 3 + 2(V DD V T )R 1 K 1 L ) 2 2(V DD V T )R 1 K c 3 = 4V T K 3 ( W L c 4 = K 3 ( W L ) 2 ) 2 1 ( ) ( W W 6R 2 L 1K 2 1 L ( ) 2 W R 1 L 1R ( ) 2 W R L 1R ) 2 ] V T 1 ] VT 2 1 Suraj SSST2011 9/ 22

13 V-Transform Definition V Ci = e γc i 0 i n dc i = dc i dp j dp 0 i n j C i i th polynomial coefficient C i i th modified polynomial coefficient V Ci i th V-Transform coefficient Suraj SSST / 22

14 V-Transform Coefficient Sensitivity Gain Sensitivity of coefficients S V C i dc i p i dp i γe γc i p i e S C = γc i i p i dc i dp i p i C i = γc i γc i Increased sensitivity over ordinary polynomial coefficients γ Sensitivity parameter that can be chosen according to the desired degree of sensitivity Suraj SSST / 22

15 Test Setup v in v out a 0 - a N V C0 - V CN f (. ) v ac V bias Variable Frequency Variable Offset Suraj SSST / 22

16 Outline 1 Motivation 2 Coefficient Based Test 3 Fault Classification 4 Results Suraj SSST / 22

17 Fault Classification R R 1 R 2 G 1 G2 m s m m s C th m C C H 2 H 1 C th H 1 : Fault likely due to manufacturing defect H 2 : Fault likely due to process parameter variation Suraj SSST / 22

18 Fault Classification Summary of steps Probability density function of the coefficients are computed by Monte Carlo simulations for fault-free Probability density function of the coefficients are computed by Monte Carlo simulations for faulty circuits Threshold values of coefficients Boundaries between process variation (PV) and manufacturing defects is estimated for each frequency Confidence of classifying a fault as PV or manufacturing defect is improved by observing one or more coefficients at multiple frequencies. Suraj SSST / 22

19 Outline 1 Motivation 2 Coefficient Based Test 3 Fault Classification 4 Results Suraj SSST / 22

20 Results Benchmark Elliptic Filter R2 C1 Vin R1 + R4 R3 R7 C3 + R11 R12 + Vout R8 C5 R14 R5 C2 R6 C4 R9 R13 R15 R10 C6 C7 Suraj SSST / 22

21 Results - V-Transform Coefficients Output Voltage (Vout) Polynomial Coefficient Plot Simulated 5th degree polynomial a5 = a4 = a3 = a2 = a1 = a0 = V Transformed Output Voltage V Transform Coefficient plot Vc5 = Vc4 = Vc3 = Vc2 = Vc1 = Vc0 = Input DC Voltage (Vin) Input DC Voltage (Vin) V C5 = V C4 = V C3 = V C2 = V C1 = V C0 = Suraj SSST / 22

22 Results at DC - Elliptic Filter Parameter combinations leading to max values of V-Transform coefficients with α = 0.05 Circuit V c0 V c1 V c2 V c3 V c4 V c5 Parameter, (ohm) R 1 = 19.6k 18.6k 20.5k 20.5k 20.5k 18.6k 18.6k R 2 = 196k 186k 205k 186k 186k 186k 205k R 3 = 147k 139k 154k 154k 154k 139k 154k R 4 = 1k R 5 = R 6 = 37.4k 37.4k 37.4k 37.4k 37.4k 37.4k 37.4k R 7 = 154k 161k 161k 146k 161k 146k 146k R 11 = 110k 115k 115k 104k 115k 104k 104k R 12 = 110k 104k 115k 104k 104k 104k 104k Suraj SSST / 22

23 Results at DC - Elliptic Filter Parameter combinations leading to min values of V-Transform coefficients with α = 0.05 Circuit V c0 V c1 V c2 V c3 V c4 V c5 Parameter, (ohm) R 1 = 19.6k 20.5k 18.6k 18.6k 20.5k 20.5k 20.5k R 2 = 196k 205k 186k 205k 205k 205k 186k R 3 = 147k 150k 139k 139k 146k 154k 139k R 4 = 1k R 5 = R 6 = 37.4k 39.2k 39.2k 39.2k 39.2k 35.5k 39.2k R 7 = 154k 146k 146k 161k 146k 161k 161k R 11 = 110k 104k 104k 115k 104k 115k 115k R 12 = 110k 115k 104k 115k 115k 115k 115k Suraj SSST / 22

24 Results at DC - Elliptic Filter Fault detection for some injected faults Circuit Out of bound Fault Out of bound Fault Parameter polynomial detected? V-Transform detected? coefficient coefficient R 1 down 25% c 3, c 4 Yes V c0 V c4 Yes R 2 down 30% c 2 Yes V c2, V c5 Yes R 3 up 25% c 3 Yes V c1, V c2, V c3 Yes R 4 down 30% c 0 Yes V c0 V c4 Yes R 5 up 30% c 4 Yes V c0, V c4 Yes R 7 up 10% None PV (C = 200) V c1, V c2 Yes R 11 up 15% None PV (C = 120) V c4, V c5 Yes R 12 down 15% None PV (C = 90) V c4, V c5 Yes Suraj SSST / 22

25 Conclusion and Future Work Conclusion Technique for parametric fault detection in analog circuits faults as small as 25% were uncovered for an elliptic filter example. Addressed parametric fault distinction between process variation induced faults. Enhanced technique for uncovering parametric faults by increasing sensitivity of polynomial coefficients to circuit parameters. Suraj SSST / 22

26 Conclusion and Future Work Conclusion Technique for parametric fault detection in analog circuits faults as small as 25% were uncovered for an elliptic filter example. Addressed parametric fault distinction between process variation induced faults. Enhanced technique for uncovering parametric faults by increasing sensitivity of polynomial coefficients to circuit parameters. Future work Technique for optimal choice of frequencies at which CUT ought to be excited Optimal order of polynomial expansion as a tradeoff between test time and diagnostic resolution Algorithms to predict/map RF & other circuit specifications to polynomial/v-transform coefficients Suraj SSST / 22