High Sensitivity Signatures for Test and Diagnosis of Analog, Mixed-Signal and Radio-Frequency Circuits

Transcription

1 High Sensitivity Signatures for Test and Diagnosis of Analog, Mixed-Signal and Radio-Frequency Circuits Ph.D. Dissertation Defense Suraj Sindia Dept. of ECE, Auburn University, AL, USA June 8, 2013 Suraj Sindia 1/ 47

2 Outline 1 Motivation 2 Contributions of This Thesis 3 Circuit Signatures: Snapshot of This Thesis 4 Recent Work 5 Publications Suraj Sindia 2/ 47

3 Outline 1 Motivation 2 Contributions of This Thesis 3 Circuit Signatures: Snapshot of This Thesis 4 Recent Work 5 Publications Suraj Sindia 3/ 47

4 Conventional Analog Circuit Test How are analog circuits tested today? Suraj Sindia 4/ 47

5 Conventional Analog Circuit Test How are analog circuits tested today? Test programs on Automatic Test Equipment (ATE) arrive at pass/fail decision based on whether Circuit Under Test (CUT) meets all data-sheet specifications. Suraj Sindia 4/ 47

6 High Costs of Conventional Analog Circuit Test Manufacturing cost Analog/Mixed signal test cost Digital test cost Cost: Cents/10,000 transistors International Technology Roadmap for Semiconductors 1999 & 2009 Suraj Sindia 5/ 47

7 What is Wrong With Conventional Analog Circuit Test? Need for unconventional test paradigms for analog circuits Testing devices for all specifications consumes long test times, on expensive test instruments. Suraj Sindia 6/ 47

8 What is Wrong With Conventional Analog Circuit Test? Need for unconventional test paradigms for analog circuits Testing some specifications may need multiple configurations and complex input stimulus. Suraj Sindia 6/ 47

9 What is Wrong With Conventional Analog Circuit Test? Need for unconventional test paradigms for analog circuits Today, analog portions of a mixed signal system on chip (SoC) can contribute as much as 50% of total test cost though they occupy less than 5% of silicon area. R. Wilson, Under the Lid: Analog test is suddenly the critical ingredient, Electronics, Design, Strategy, News, Jan Suraj Sindia 6/ 47

10 What is Wrong With Conventional Analog Circuit Test? Need for unconventional test paradigms for analog circuits Testing devices for all specifications consumes long test times, on expensive test instruments. Testing some specifications may need multiple configurations and complex input stimulus. Today, analog portions of a mixed signal system on chip (SoC) can contribute as much as 50% of total test cost though they occupy less than 5% of silicon area. R. Wilson, Under the Lid: Analog test is suddenly the critical ingredient, Electronics, Design, Strategy, News, Jan Suraj Sindia 6/ 47

11 Unconventional Analog Test Paradigms Key advantage over conventional test: pass/fail decision is arrived at based on a few easily available measurements. Suraj Sindia 7/ 47

12 Unconventional Analog Test Paradigms Key advantage over conventional test: pass/fail decision is arrived at based on a few easily available measurements. Can be broadly classified into Fault model based test techniques Alternate circuit test techniques Suraj Sindia 7/ 47

13 Unconventional Analog Test Paradigms Key advantage over conventional test: pass/fail decision is arrived at based on a few easily available measurements. Can be broadly classified into Fault model based test techniques Defects in circuit components are modeled as faults. Test stimulus is geared towards detecting faults in circuit components. Pass/fail decision is based on where component values lie w.r.t their fault free range. M. Soma CICC 91, K. Arabi ITC 93, IEEE DTC 92, J. Abraham IEEE DTC 96, S. Sunter VTS 98, J. Savir ITC 03. Suraj Sindia 7/ 47

14 Unconventional Analog Test Paradigms Key advantage over conventional test: pass/fail decision is arrived at based on a few easily available measurements. Can be broadly classified into Fault model based test techniques Alternate circuit test techniques A regression model relating circuit outputs to specifications is built. Test stimulus is crafted to maximize correlation of circuit output to specification. Pass/fail decision is based on predicted value of specification by the regression model. A. Chatterjee ICCAD 97, VTS 00, Y. Makris VTS 05, 06. Suraj Sindia 7/ 47

15 Unconventional Analog Test Paradigms But these unconventional test paradigms... Are rarely used in the industry. Suraj Sindia 8/ 47

16 Unconventional Analog Test Paradigms But these unconventional test paradigms... Are rarely used in the industry. Why? Suraj Sindia 8/ 47

17 Unconventional Analog Test Paradigms But these unconventional test paradigms... Are rarely used in the industry. Why? Lack of circuit outputs (or signatures) with High sensitivity to circuit parameters, and High correlation to specifications. Suraj Sindia 8/ 47

18 Outline 1 Motivation 2 Contributions of This Thesis 3 Circuit Signatures: Snapshot of This Thesis 4 Recent Work 5 Publications Suraj Sindia 9/ 47

19 Principal Contribution of This Work To design analog circuit test signatures High sensitivity detects sufficiently small parametric faults, thus augmenting existing fault model based test schemes Suraj Sindia 10/ 47

20 Principal Contribution of This Work To design analog circuit test signatures High sensitivity detects sufficiently small parametric faults, thus augmenting existing fault model based test schemes High correlation with circuit specifications augmenting alternate circuit test schemes Suraj Sindia 10/ 47

21 Principal Contribution of This Work To design analog circuit test signatures High sensitivity detects sufficiently small parametric faults, thus augmenting existing fault model based test schemes High correlation with circuit specifications augmenting alternate circuit test schemes Small area overhead requires little additional hardware on chip for production testing Suraj Sindia 10/ 47

22 Principal Contribution of This Work To design analog circuit test signatures High sensitivity detects sufficiently small parametric faults, thus augmenting existing fault model based test schemes High correlation with circuit specifications augmenting alternate circuit test schemes Small area overhead requires little additional hardware on chip for production testing Large number observables handy in diagnosis Suitable for large class of circuits Aids distinction of small defects from process variation (PV) induced faults need in advanced tech nodes Amenable to self-test. Suraj Sindia 10/ 47

23 In This Dissertation Main Contribution Design analog circuit test signatures. Additional contributions Extend the use of these signatures for diagnosis of component faults. Suraj Sindia 11/ 47

24 In This Dissertation Main Contribution Design analog circuit test signatures. Additional contributions Extend the use of these signatures for diagnosis of component faults. Demonstrate the use of signatures for classifying faults due to manufacturing defects from those due to process related variations. Suraj Sindia 11/ 47

25 In This Dissertation Main Contribution Design analog circuit test signatures. Additional contributions Extend the use of these signatures for diagnosis of component faults. Demonstrate the use of signatures for classifying faults due to manufacturing defects from those due to process related variations. Evaluate the bounds on minimum achievable defect level and yield loss resulting from the use of these test signatures. Suraj Sindia 11/ 47

26 A Statement on Methods Proposed signatures and associated test procedures Are analyzed theoretically. Validated empirically through simulations on common analog circuits such as filters and low noise amplifier. Are additionally validated by conducting hardware measurements on these circuits using NI-ELVIS instrumentation boards. NI-ELVIS National Instruments ELectronic Virtual Instrumentation Suite Suraj Sindia 12/ 47

27 Outline 1 Motivation 2 Contributions of This Thesis 3 Circuit Signatures: Snapshot of This Thesis 4 Recent Work 5 Publications Suraj Sindia 13/ 47

28 Test Setups: Unconventional Test Paradigms vs. Proposed Test setup commonly used in unconventional test paradigms Suraj Sindia 14/ 47

29 Test Setups: Unconventional Test Paradigms vs. Proposed Proposed test Setup Suraj Sindia 14/ 47

30 Polynomial Coefficient Based Testing Test Setup Suraj Sindia 15/ 47

31 Polynomial Coefficient Based Testing Taylor series expansion of circuit function about v in = 0 v out = f (v in ) v out = f (0) + f (0) 1! v in + f (0) 2! v 2 in + f (0) 3! v 3 in + + f (n) (0) n! v n in + S. Sindia et. al., GLSVLSI 2009, ATS Suraj Sindia 16/ 47

32 Polynomial Coefficient Based Testing Taylor series expansion of circuit function about v in = 0 v out = f (v in ) v out = f (0) + f (0) 1! v in + f (0) 2! v 2 in + f (0) 3! v 3 in + + f (n) (0) n! v n in + Ignoring the higher order terms we have v out a 0 + a 1 v in + a 2 v 2 in + + a nv n in where every a i R and is bounded between its extreme values for a i,min < a i < a i,max i 0 i n S. Sindia et. al., GLSVLSI 2009, ATS Suraj Sindia 16/ 47

33 Polynomial Coefficient Based Testing Cascaded amplifiers quick example Vdd R1 I M1 R2 I M2 V out M1 M2 V in Suraj Sindia 17/ 47

34 Polynomial Coefficient Based Testing Cascaded amplifiers quick example Vdd R1 I M1 R2 I M2 V out M1 M2 V in Two stage amplifier with 4 th degree non-linearity in V in v out = a 0 + a 1 v in + a 2 v 2 in + a 3v 3 in + a 4v 4 in Suraj Sindia 17/ 47

35 Polynomial Coefficient Based Testing Polynomial coefficients are related to circuit components Suraj Sindia 18/ 47

36 Polynomial Coefficient Based Testing Polynomial coefficients are related to circuit components ( ) [ W (V a 0 = V DD R 2 K DD V T ) 2 + R1 2K ( ) ] 2 W 2 ( L 1 V T 4 L 2 2(V DD V T )R W ) 1 L 1 V T 2 ( ) [ ( ) 2 ( ) ] W W W a 1 = R 2 K 4R 2 L 1K 2 VT 3 2 L + 2(V DD V T )R 1 K V T 1 L 1 ) [ ] a 2 = R 2 K ( W L 2 2(V DD V T )R 1 K a 3 = 4V T K 3 ( W L a 4 = K 3 ( W L ) 2 ) 2 1 ( ) W L ( W 1 L ( W L ) 2 ) 2 1 6R 2 1K 2 ( W L R1R R1R ) 2 VT 2 1 Suraj Sindia 18/ 47

37 Polynomial Coefficient Based Testing MSDF Calculation Minimum Size Detectable Fault(ρ) of a circuit parameter is defined as its minimum fractional deviation to force at least one of the polynomial coefficients out of its fault free range Suraj Sindia 19/ 47

38 Polynomial Coefficient Based Testing MSDF Calculation Minimum Size Detectable Fault(ρ) of a circuit parameter is defined as its minimum fractional deviation to force at least one of the polynomial coefficients out of its fault free range Overview( of) MSDF( calculation ) of R 1 with V DD =1.2V, V T = 400mV, W L = 1 W 1 2 L = 20, and K = 100µA/V2 2 Suraj Sindia 19/ 47

39 Polynomial Coefficient Based Testing MSDF Calculation Minimum Size Detectable Fault(ρ) of a circuit parameter is defined as its minimum fractional deviation to force at least one of the polynomial coefficients out of its fault free range Overview( of) MSDF( calculation ) of R 1 with V DD =1.2V, V T = 400mV, W L = 1 W 1 2 L = 20, and K = 100µA/V2 2 Maximize a 0 { ( 2.56x R R 2,nom (1 + y) 1,nom (1 + x) x10 7 )} 5.12x10 4 R 1,nom (1 + x) subject to a 1, a 2, a 3, a 4 being in their fault free ranges and α x, y α Suraj Sindia 19/ 47

40 Polynomial Coefficient Based Testing MSDF Calculation (contd..) Assuming single parametric faults, ρ for R 1 ρ = (1 α) α 0.375α 2 Suraj Sindia 20/ 47

41 Polynomial Coefficient Based Testing MSDF Calculation (contd..) Assuming single parametric faults, ρ for R 1 ρ = (1 α) α 0.375α 2 MSDF for Cascaded Amplifier with α = 0.05 Circuit parameter %upside MSDF %downside MSDF Resistor R Resistor R Suraj Sindia 20/ 47

42 Polynomial Coefficient Based Testing In a nutshell Find the V out v/s V in relationship at DC & and selected tones Suraj Sindia 21/ 47

43 Polynomial Coefficient Based Testing In a nutshell Find the V out v/s V in relationship at DC & and selected tones Compute the coefficients of fault-free circuit Suraj Sindia 21/ 47

44 Polynomial Coefficient Based Testing In a nutshell Find the V out v/s V in relationship at DC & and selected tones Compute the coefficients of fault-free circuit Fault simulate to obtain fault free intervals of each of these coefficients Estimate coefficients of CUT by curve fitting the I/O response Suraj Sindia 21/ 47

45 Polynomial Coefficient Based Testing In a nutshell Find the V out v/s V in relationship at DC & and selected tones Compute the coefficients of fault-free circuit Fault simulate to obtain fault free intervals of each of these coefficients Estimate coefficients of CUT by curve fitting the I/O response Compare each of the obtained coefficients with fault-free circuit range Suraj Sindia 21/ 47

46 Polynomial Coefficient Based Testing In a nutshell Find the V out v/s V in relationship at DC & and selected tones Compute the coefficients of fault-free circuit Fault simulate to obtain fault free intervals of each of these coefficients Estimate coefficients of CUT by curve fitting the I/O response Compare each of the obtained coefficients with fault-free circuit range Classify CUT as Good or Bad Suraj Sindia 21/ 47

47 V-Transform Coefficient An Introduction Definition V Ci = e γc i 0 i n dc i = dc i dp j dp 0 i n j C i i th polyomial coefficient C i i th modified polynomial coefficient V Ci i th V-Transform coefficient S. Sindia et. al., EWDTS 2009, VTS Suraj Sindia 22/ 47

48 V-Transform Coefficient Sensitivity Gain Sensitivity of coefficients S V C i dc i p i dp i γe γc i p i e S C = γc i i p i dc i dp i p i C i = γc i γc i Increased sensitivity over ordinary polynomial coefficients γ Sensitivity parameter that can be chosen according to the desired degree of sensitivity S. Sindia et. al., EWDTS 2009, VTS Suraj Sindia 23/ 47

49 V-transform Coefficient Based Test Test Set-up S. Sindia et. al., EWDTS 2009, VTS Suraj Sindia 24/ 47

50 Let us Generalize Suraj Sindia 25/ 47

51 Generalization Fault Simulation 1 Start 2 Choose frequency for fault simulation 3 Apply sweep to input and note corresponding output voltage levels 4 Polynomial Curve fit the obtained I/O data find the coefficient values of fault free circuit. Compute corresponding V-Transform coefficients. 5 Simulate for all parametric faults at the simplex of hypercube 6 Find min-max values of each coefficient (C i ) from i = 1 N across all simulations. Compute the V-Transform coefficient V Ci bounds. 7 Repeat process at all chosen frequencies 8 Stop Suraj Sindia 26/ 47

52 Generalization Test Procedure 1 Start 2 Choose a frequency 3 Sweep input and note corresponding output voltage levels 4 Polynomial Curve fit the obtained I/O data. Obtain coefficients C i i = 1 N. 5 Obtain corresponding V Ci 6 Consider the coefficient V Ci, starting from i = 1 N 7 V Ci > VCi,max or VCi < VCi,min? Yes or No 8 If Yes, conclude CUT is faulty. If not, repeat the test for next coefficient. 9 If all coefficients are inside the bounds, subject CUT to further tests. Stop Suraj Sindia 27/ 47

53 Results Benchmark Elliptic Filter R2 C1 Vin R1 + R4 R3 R7 C3 + R11 R12 + Vout R8 C5 R14 R5 C2 R6 C4 R9 R13 R15 R10 C6 C7 Suraj Sindia 28/ 47

54 Results - Curve Fitting at DC Output Voltage(Vout) Simulated 5th degree polynomial a5 = a4 = a3 = a2 = a1 = a0 = Input DC voltage (Vin) v out = v in v 2 in v 3 in v 4 in v 5 in Suraj Sindia 29/ 47

55 Results - V-Transform Coefficients Output Voltage (Vout) Polynomial Coefficient Plot Simulated 5th degree polynomial a5 = a4 = a3 = a2 = a1 = a0 = V Transformed Output Voltage V Transform Coefficient plot Vc5 = Vc4 = Vc3 = Vc2 = Vc1 = Vc0 = Input DC Voltage (Vin) Input DC Voltage (Vin) V C5 = V C4 = V C3 = V C2 = V C1 = V C1 = Suraj Sindia 30/ 47

56 Results at DC - Elliptic Filter Parameter Combinations Leading to Max Values of V-Transform Coefficients with α = 0.05 Circuit V c0 V c1 V c2 V c3 V c4 V c5 Parameter, (ohm) R 1 = 19.6k 18.6k 20.5k 20.5k 20.5k 18.6k 18.6k R 2 = 196k 186k 205k 186k 186k 186k 205k R 3 = 147k 139k 154k 154k 154k 139k 154k R 4 = 1k R 5 = R 6 = 37.4k 37.4k 37.4k 37.4k 37.4k 37.4k 37.4k R 7 = 154k 161k 161k 146k 161k 146k 146k R 11 = 110k 115k 115k 104k 115k 104k 104k R 12 = 110k 104k 115k 104k 104k 104k 104k Suraj Sindia 31/ 47

57 Results at DC - Elliptic Filter Parameter Combinations Leading to Min Values of V-Transform coefficients with α = 0.05 Circuit V c0 V c1 V c2 V c3 V c4 V c5 Parameter, (ohm) R 1 = 19.6k 20.5k 18.6k 18.6k 20.5k 20.5k 20.5k R 2 = 196k 205k 186k 205k 205k 205k 186k R 3 = 147k 150k 139k 139k 146k 154k 139k R 4 = 1k R 5 = R 6 = 37.4k 39.2k 39.2k 39.2k 39.2k 35.5k 39.2k R 7 = 154k 146k 146k 161k 146k 161k 161k R 11 = 110k 104k 104k 115k 104k 115k 115k R 12 = 110k 115k 104k 115k 115k 115k 115k Suraj Sindia 32/ 47

58 Fault Classification Motivation 1 Semiconductor processes at advanced nodes are subject to random variability Poly/TFR resistance (LER), oxide thickness fluctuation/ler capacitors (σ 30%) Suraj Sindia 33/ 47

59 Fault Classification Motivation 1 Semiconductor processes at advanced nodes are subject to random variability Poly/TFR resistance (LER), oxide thickness fluctuation/ler capacitors (σ 30%) 2 Faults due to variability can mask or exacerbate failure from conventional defect mechanisms. Dust contamination, Processing Equipment, Material impurity, Clean room contamination, Operator imperfection, etc., (Fault sizes > 50%) Suraj Sindia 33/ 47

60 Fault Classification Motivation 1 Semiconductor processes at advanced nodes are subject to random variability Poly/TFR resistance (LER), oxide thickness fluctuation/ler capacitors (σ 30%) 2 Faults due to variability can mask or exacerbate failure from conventional defect mechanisms. Dust contamination, Processing Equipment, Material impurity, Clean room contamination, Operator imperfection, etc., (Fault sizes > 50%) 3 Distinguishing failure mechanisms between PV and conventional ones can possibly help improve yield. Suraj Sindia 33/ 47

61 Fault Classification Suraj Sindia 34/ 47

62 Fault Classification R R 1 R 2 G 1 G2 m s m m s C th m C C H 2 H 1 C th H 1 : Fault likely due to manufacturing defect H 2 : Fault likely due to process parameter variation Suraj Sindia 35/ 47

63 Fault Classification Summary of steps PDF of the coefficients are computed by monte-carlo simulations for fault-free PDF of the coefficients are computed by monte-carlo simulations for faulty circuits Threshold values of coefficients Boundaries between PV and manufacturing defects is estimated for each frequency Confidence of classifying a fault as PV or manufacturing defect is improved by observing one or more coefficients at multiple frequencies. Suraj Sindia 36/ 47

64 Fault Classification Confidence of classification If P i is the probability of coefficient being outside its permissible interval due to process variation, then we define confidence in diagnosing CUT to be faulty due to PV, C (N is the total number of coefficients). 1 C = 1 i=n (1 P i ) i=1 Suraj Sindia 37/ 47

65 Results at DC - Elliptic Filter Fault detection for some injected faults Circuit Out of bound Fault Out of bound Fault Parameter polynomial detected? V-Transform detected? coefficient coefficient R 1 down 25% a 3, a 4 Yes V c0 V c4 Yes R 2 down 30% a 2 Yes V c2, V c5 Yes R 3 up 25% a 3 Yes V c1, V c2, V c3 Yes R 4 down 30% a 0 Yes V c0 V c4 Yes R 5 up 30% a 4 Yes V c0, V c4 Yes R 7 up 10% None PV (C = 200) V c1, V c2 Yes R 11 up 15% None PV (C = 120) V c4, V c5 Yes R 12 down 15% None PV (C = 90) V c4, V c5 Yes Suraj Sindia 38/ 47

66 Results Not Presented in Today s Talk Circuit test using probability moments of the circuit output as a signature and noise as input. S. Sindia, et. al., LATW 11, ATS 11 Suraj Sindia 39/ 47

67 Results Not Presented in Today s Talk Parametric and catastrophic fault diagnosis using V-transform, polynomial and probability moments as circuit signatures. S. Sindia, et. al., VLSI Design 10, VTS 11, ATS 11 Suraj Sindia 39/ 47

68 Results Not Presented in Today s Talk An analytical bound on defect level and fault coverage achievable using transfer function coefficient based test. S. Sindia, et. al., VDAT 09 Suraj Sindia 39/ 47

69 Results Not Presented in Today s Talk Hardware validation of V-transform and polynomial coefficient based test on a 5th order elliptic filter using NI -ELVIS. S. Sindia, et. al., JETTA 11 (spl. issue) Suraj Sindia 39/ 47

70 Results Not Presented in Today s Talk Circuit test using probability moments of the circuit output as a signature and noise as input. Parametric and catastrophic fault diagnosis using V-transform, polynomial and probability moments as circuit signatures. An analytical bound on defect level and fault coverage achievable using transfer function coefficient based test. Hardware validation of V-transform and polynomial coefficient based test on a 5th order elliptic filter using NI -ELVIS. Suraj Sindia 39/ 47

71 Outline 1 Motivation 2 Contributions of This Thesis 3 Circuit Signatures: Snapshot of This Thesis 4 Recent Work 5 Publications Suraj Sindia 40/ 47

72 Closed Loop Signature Testing Idea: Applying stimulus based on the response of the CUT to a reference signal to enhance correlation of signatures to specification. Suraj Sindia 41/ 47

73 Results: Open Loop Signature Testing Suraj Sindia 42/ 47

74 Results: Closed Loop Signature Testing Suraj Sindia 43/ 47

75 Results Comparison of defect level, yield loss, and test time Test Method Defect Level Yield Loss Test Time (per device) Actual specification test 0% 0% 15s Signature test in open loop 8% 12% 100ms Signature test in closed loop 0.8% 1.8% 105ms Suraj Sindia 44/ 47

76 Outline 1 Motivation 2 Contributions of This Thesis 3 Circuit Signatures: Snapshot of This Thesis 4 Recent Work 5 Publications Suraj Sindia 45/ 47

77 PUBLICATIONS ALL JOURNAL PUBLICATIONS 1 S. Sindia, V. D. Agrawal, V. Singh, Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients, JETTA, Spl. issue on Mixed Signal Test Techniques. 2 S. Sindia, V. D. Agrawal, V. Singh Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing, JETTA Letters. 3 S. Sindia, V. D. Agrawal, Neural Network Guided Spatial Fault Resilience in Array Processors, To appear, JETTA, Spl. issue on Defect and Fault Tolerance. 4 S. Sindia, V. D. Agrawal, Testing Analog Circuits Via Moments as Output Signatures and Random Noise as Input, In preparation IEEE Trans. Comp. Aided Des. 5 S. Sindia, V. D. Agrawal, Closed Loop Testing of Analog Circuits Via V-Transform, In preparation IEEE Trans. Comp. Aided Des. Suraj Sindia 46/ 47

78 ALL CONFERENCE PUBLICATIONS 1 P. Venkataramani, S. Sindia, V. D. Agrawal, Finding Best Voltage and Frequency to Shorten Power-Constrained Test Time, VLSI Test Symp., VTS 2013, Berkeley, CA 2 S. Sindia, S. Gao, B. Black, V. D. Agrawal, A. Lim, P. Agrawal, MobSched: Customizable Scheduler for Mobile Cloud Computing, Proc. of Southeastern. Symp. on Systems Theory, SSST 2013, Waco, TX 3 S. Sindia, V. D. Agrawal, Analog and RF Circuit Testing Education Day Talk, VLSI Design and Test Symp., VDAT 2012, Shibpur, India 4 S. Sindia, V. D. Agrawal, V. Singh, Impact of Process Variations on Computers Used for Image Processing, Proc. of Int. Symp. on Circuits and Systems, ISCAS 2012, Seoul, South Korea 5 S. Sindia, V. D. Agrawal, Towards Spatial Fault Resilience in Array Processors, Proc. of 30th IEEE VLSI Test Symposium, VTS 2012, Maui, HI Suraj Sindia 46/ 47

79 6 S. Sindia, V. D. Agrawal, F. Dai, All-Digital Replica Techniques for Managing Random Mismatch in Time-to-Digital Converters, Proc. of Southeastern. Symp. on Systems Theory, SSST 2012, Jacksonville, FL 7 S. Sindia, V. D. Agrawal, V. Singh, Test and Diagnosis of Analog Circuits using Moment Generating Functions, Proc. of 20th Asian Test Symposium, ATS 2011, New Delhi, India 8 S. Sindia, V. D. Agrawal, F. Dai, LNA Test: A Polynomial Coefficient Approach, Proc. 20th IEEE North Atlantic Test Workshop, NATW 2011, Lowell, MA 9 S. Sindia, V. D. Agrawal, V. Singh, Non-Linear Analog Circuit Test using Moment Generating Functions, Proc. of 12th IEEE Latin American Test Workshop, LATW 2011, Porto de Galinhas, Brazil 10 S. Sindia, V. D. Agrawal, V. Singh, Non-Linear Analog Circuit Test and Diagnosis under Process Variation using V-Transform Coefficients, Proc. of 29th IEEE VLSI Test Symposium, VTS 2011, Dana Point, CA Suraj Sindia 46/ 47

80 11 S. Sindia, V. D. Agrawal, V. Singh, Distinguishing Process Variation Induced Faults from Manufacturing Defects in Analog ICs, Proc. of 43rd IEEE Southeastern Symposium on System Theory, SSST 2011, Auburn, AL 12 S. Sindia, V. Singh, V. D. Agrawal, Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients, Proc. of 23rd Intl. Conf. on VLSI Design, VLSI 2010, Bangalore, India 13 S. Sindia, V. Singh, V. D. Agrawal, Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients, Proc. of 18th Asian Test Symposium, ATS 2009, Taichung, Taiwan 14 S. Sindia, V. Singh, V. D. Agrawal, V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-Linear Analog Circuits, Proc. of 7th IEEE East-West Design and Test Symposium, EWDTS 2009, Moscow, Russia Suraj Sindia 46/ 47

81 15 S. Sindia, V. Singh, V. D. Agrawal, Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing, Proc. of 13th IEEE/VSI VLSI Design and Test Symposium, VDAT 2009, Bangalore, India 16 S. Sindia, V. Singh, V. D. Agrawal, Polynomial Coefficient Based Multi-Tone Test of Analog Circuits, Proc. of 18th IEEE North Atlantic Test Workshop, NATW 2009, Hopewell Jn., NY 17 S. Sindia, V. Singh, V. D. Agrawal, Polynomial Coefficient Based DC Testing of Non-Linear Analog Circuits, Proc. of 19th ACM Great Lakes Symposium on VLSI, GLSVLSI 2009, Boston, MA Suraj Sindia 47/ 47

82 Thanks for coming! Get some pizza Suraj Sindia 47/ 47