ALTERA MAX10 Development & Education Board (DE10-Lite)
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- Caroline Sanders
- 5 years ago
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1 LTER MX0 evelopment & Education oard (E0-Lite) PGE ONTENT PGE ONTENT over Page lock iagram MX 0 ank & MX 0 ank & MX 0 ank & MX 0 ank & MX 0 locks MX 0 onfiguration 0 0 MX0 Power MX0 Ground MX0 ecoupling SRM GPIO and rduino Interface LE, 'Seg, User IO VG and ccelerometer Power - V,.V Power -.V,.V,.V US laster opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev over Page ate: Friday, January 0, 0 Sheet of
2 opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev lock iagram ate: Friday, January 0, 0 Sheet of
3 MX0 ank & nalog input interface IN[..] VG VG_R[..0] VG_G[..0] VG_[..0] VG_HS VG_VS IN IN IN IN IN IN IN IN F F E E J J G F H J H G K K J K K K L L L E F H J G F M M K L U MX 0 LEFT NKS NK- VIO =.V IFFIO_RX_LN/IN IFFIO_RX_LP/IN IFFIO_RX_LN/IN IFFIO_RX_LP/IN IFFIO_RX_LN/IN IFFIO_RX_LP/IN IFFIO_RX_LN/IN IFFIO_RX_LP/IN IFFIO_RX_LP/IN IFFIO_RX_LN/IN IFFIO_RX_LN/IN IFFIO_RX_LP/IN IFFIO_RX_LN/IN IFFIO_RX_LP/IN IFFIO_RX_LP/IN IFFIO_RX_LN/IN NK- VIO =.V IFFIO_RX_LN IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_L0N IFFIO_RX_L0P IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP VREFN0 IO_NK NK-VIO =.V IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_L0N IFFIO_RX_L0P IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_LN IFFIO_RX_LP IFFIO_RX_L0N IFFIO_RX_L0P VREFN0 IO_NK P P N N R R T T N N P N T U U V U U U V P R W W R R M M VG_ VG_HS VG_ VG_ VG_G VG_0 VG_VS VG_R VG_G0 VG_G VG_G 0M0F opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX 0 ank & ate: Friday, January 0, 0 Sheet of
4 , GPIO 0 GPIO_[..0] MX0 ank & rduino igital Interface rduino_io[..0] U MX 0 OTTOM NKS igital ccelerometer VG GSENSOR_SI GSENSOR_SLK GSENSOR_INT GSENSOR_INT GSENSOR_S_n GSENSOR_SO VG_R[..0] GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 rduino_io0 rduino_io rduino_io GPIO_ rduino_io GPIO_ rduino_io GPIO_ VG_R VG_R VG_R0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ rduino_io GPIO_ GPIO_ GPIO_ Y Y Y Y V V Y Y Y Y W W0 W W R0 P0 W W Y0 0 U U W W V V R P NK-VIO =.V NK-VIO =.V IFFIO_RX_0N IFFIO_RX_N W Y IFFIO_RX_0P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_N 0 IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_N IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_N W W IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_N IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_0N Y IFFIO_RX_P IFFIO_RX_0P IFFIO_RX_N IFFIO_RX_N IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_N 0 IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_N Y IFFIO_RX_P IFFIO_RX_P IFFIO_RX_N IFFIO_RX_0N 0 IFFIO_RX_P IFFIO_RX_0P IFFIO_RX_N IFFIO_RX_N IFFIO_RX_P IFFIO_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N V V IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N R P IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N V W IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N R P IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N Y Y IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N V W IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N U V IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N Y IFFIO_TX_RX_P IFFIO_TX_RX_P IFFIO_TX_RX_N IFFIO_TX_RX_N V W IFFIO_TX_RX_P IFFIO_TX_RX_P VREFN0 IFFIO_TX_RX_N Y W IO_NK IFFIO_TX_RX_P VREFN0 IO_NK GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GSENSOR_SLK GPIO_ GSENSOR_S_n rduino_io0 rduino_io rduino_io rduino_io rduino_io rduino_io GSENSOR_SI GSENSOR_SO rduino_io rduino_io GSENSOR_INT GSENSOR_INT rduino_io rduino_io 0M0F opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX 0 ank & ate: Friday, January 0, 0 Sheet of
5 SRM RM_R[..0] RM_Q[..0] MX0 ank & SWITH KEY LE RM_KE RM_LQM RM_UQM RM_WE_N RM_S_N RM_RS_N RM_S_N RM_0 RM_ SW[..0] KEY[..0] LER[..0] -segment isplay HEX0[..0] HEX[..0] HEX[..0] HEX[..0] HEX[..0] HEX[..0] RM_R RM_R RM_R RM_R0 RM_Q RM_Q RM_Q RM_R RM_Q0 RM_Q RM_S_N RM_WE_N RM_LQM RM_Q RM_ RM_0 RM_R RM_R RM_R RM_R0 RM_RS_N RM_S_N RM_Q RM_Q RM_KE RM_Q RM_R RM_R RM_R RM_R U V U U W Y W0 W Y Y0 U0 V0 V V R R T T T T R0 T0 U U P P N P P R P0 P L M M N P R U MX 0 RIGHT NKS NK-VIO =.V NK-VIO =.V IFFIO_RX_RN IFFIO_RX_RN H H IFFIO_RX_RP IFFIO_RX_RP IFFIO_RX_RP/RUP IFFIO_RX_RN J J IFFIO_RX_RN/RN IFFIO_RX_RP IFFIO_RX_R0N IFFIO_RX_RN G G0 IFFIO_RX_R0P IFFIO_RX_RP IFFIO_RX_RN IFFIO_RX_RN F G IFFIO_RX_RP IFFIO_RX_RP IFFIO_RX_RN IFFIO_RX_RN/QR M IFFIO_RX_RP IFFIO_RX_RP/QR M IFFIO_RX_RN IFFIO_RX_RN E E IFFIO_RX_RP IFFIO_RX_RP IFFIO_RX_RN IFFIO_RX_RN/MR N IFFIO_RX_RP IFFIO_RX_RP/QR N IFFIO_RX_RN/QR IFFIO_RX_RP/QR M0 IFFIO_RX_RP/QR IFFIO_RX_RN/QR N0 IFFIO_RX_RN IFFIO_RX_RN F0 F IFFIO_RX_RP IFFIO_RX_RP IFFIO_RX_RN/MR IFFIO_RX_RN IFFIO_RX_RP/QR IFFIO_RX_RP IFFIO_RX_RN/QR IFFIO_RX_RN/QR L IFFIO_RX_RP/QR IFFIO_RX_RP/QR M IFFIO_RX_RN IFFIO_RX_RN/QR L0 IFFIO_RX_RP IFFIO_RX_RP/QR L IFFIO_RX_RN IFFIO_RX_RN F E IFFIO_RX_RP IFFIO_RX_RP IFFIO_RX_R0N/QR IFFIO_RX_RN E0 F IFFIO_RX_R0P/QR IFFIO_RX_RP IFFIO_RX_RN IFFIO_RX_RN/QSNR K IFFIO_RX_RP IFFIO_RX_RP/QSR K IFFIO_RX_RN/QSNR IFFIO_RX_RN 0 IFFIO_RX_RP/QSR IFFIO_RX_RP IFFIO_RX_RN/QR IFFIO_RX_RN/QR J IFFIO_RX_RP/QR IFFIO_RX_RP/QR K IFFIO_RX_RN IFFIO_RX_RN/QR K0 IFFIO_RX_RP IFFIO_RX_RP/QR K IFFIO_RX_RN IFFIO_RX_RN E F IFFIO_RX_RP IFFIO_RX_RP VREFN0 IFFIO_RX_R0N IO_NK IFFIO_RX_R0P IFFIO_RX_RN/MR J IFFIO_RX_RP/QR J IFFIO_RX_RN 0 IFFIO_RX_RP IFFIO_RX_RN/QR H IFFIO_RX_RP/QR H IFFIO_RX_RN/QR H0 IFFIO_RX_RP/QR J0 E IFFIO_RX_R0N/K#_ IFFIO_RX_R0P/K_ VREFN0 IO_NK RM_Q0 RM_Q RM_UQM RM_Q RM_Q RM_Q RM_Q RM_Q HEX HEX HEX HEX HEX HEX HEX HEX0 HEX HEX HEX HEX HEX0 HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX0 HEX HEX0 HEX HEX 0M0F opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX 0 ank & ate: Friday, January 0, 0 Sheet of
6 -segment isplay SWITH KEY LE HEX0[..0] HEX[..0] HEX[..0] HEX[..0] HEX[..0] HEX[..0] SW[..0] KEY[..0] LER[..0] rduino igital Interface rduino_reset_n HEX HEX HEX0 HEX0 HEX HEX LER HEX00 SW SW HEX0 HEX0 LER LER SW SW SW SW LER LER SW0 SW LER SW KEY0 LER HEX0 HEX0 LER KEY LER0 SW rduino_reset_n HEX HEX HEX HEX0 HEX HEX LER HEX0 J H E E E E J H 0 0 J H 0 F F 0 E U MX0 ank & MX 0 TOP NKS NK-VIO =.V NK-VIO =.V IFFIO_RX_T0N IFFIO_RX_TN IFFIO_RX_T0P IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN E IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN E IFFIO_RX_T0N IFFIO_RX_TP IFFIO_RX_T0P IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TP VREFN0 IFFIO_RX_TN IO_NK IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_T0N IFFIO_RX_T0P IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP IFFIO_RX_TN IFFIO_RX_TP VREFN0 IO_NK 0M0F opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX 0 ank & ate: Friday, January 0, 0 Sheet of
7 , GPIO 0 UT_LK_ GPIO_[..0] _LK_0 N N M M UE MX0 lock MX 0 LOK NK- VIO =.V IFFIO_RX_LN/LK0N IFFIO_RX_LN/PLK0 IFFIO_RX_LP/LK0P IFFIO_RX_LP/PLK IFFIO_RX_LN/LKN IFFIO_RX_LN/PLL_L_LKOUTN IFFIO_RX_LP/LKP IFFIO_RX_LP/PLL_L_LKOUTP P R T T SRM RM_LK GPIO_ GPIO_0 MX0_LK_0 V V0 R P NK- IFFIO_TX_RX_N/LKN IFFIO_TX_RX_P/LKP IFFIO_TX_RX_0N/LKN IFFIO_TX_RX_0P/LKP VIO =.V NK- VIO =.V IFFIO_TX_RX_N/PLL LKOUTN IFFIO_TX_RX_P/PLL LKOUTP W V MX0_LK_0 N N K K IFFIO_RX_RN/LKN IFFIO_RX_RP/LKP IFFIO_RX_R0N/LKN IFFIO_RX_R0P/LKP NK- VIO =.V IFFIO_RX_R0N/PLK/QSnR IFFIO_RX_R0P/PLK/QSR IFFIO_RX_RN/PLL_R_LKOUTN IFFIO_RX_RP/PLL_R_LKOUTP L L G H RM_LK E0 E J0 H IFFIO_RX_TN/LKN IFFIO_RX_TP/LKP IFFIO_RX_T0P/LKP IFFIO_RX_T0N/LKN NK- VIO =.V IFFIO_RX_TN/PLL_T_LKOUTN IFFIO_RX_TP/PLL_T_LKOUTP E 0M0F VP Note: Place near pin and ( & ) Note: Place near I power pin L 0 ohm, 0. VP 0 0.0u 0V n 0V 0.u 0V 0.u 0V 0.u 0V.u.V p.v NI Y.00MHz p.v NI R.K VP R.K 0 U Xin/lk Xout S0 S/S S/SL Vctrl V GN GN GN 0 Vddout Vddout Vddout Y Y Y Y Y Y Y R. R. R0. R. UT_LK LK_0 MX0_LK_0 MX0_LK_0 efault: MHz efault: MHz efault: 0MHz efault: 0MHz efault: 0MHz efault: 0MHz efault: 0MHz EPWRG efault : I ddress 0x/0x opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX 0 locks ate: Friday, January 0, 0 Sheet of
8 JTG Interface JTG_TK JTG_TMS JTG_TI JTG_TO JTG_EN MX0 onfiguration FPG ONFIG NONFIG NSTTUS ONF_ONE ONFIG_SEL VP UF VP VP VP VP VP R0 0 NI p NI R 0K R K R 0K R 0K JTG_EN JTG_TK JTG_TMS JTG_TO JTG_TI esign Note: Optional termination resistor for JTG TK Note: Place near JTG TK pin MX 0 onfiguration NK- NK- VIO =.V VIO =.V K G IFFIO_RX_LP/JTGEN NONFIG H IFFIO_RX_LP/TK ONFIG_SEL L IFFIO_RX_LN/TMS IFFIO_RX_TN/EV_LRN M IFFIO_RX_LN/TI IFFIO_RX_TP/EV_OE IFFIO_RX_LP/TO IFFIO_RX_TN/R_ERROR IFFIO_RX_T0P/NSTTUS IFFIO_RX_T0N/ONF_ONE 0M0F H H0 0 F G F NONFIG ONFIG_SEL NSTTUS ONF_ONE R 0K R 0K R 0K R 0K NI R 0K R K oot Select JP NI X Header OOT Select efault isable (Jumper Open) OPEN = configuration image 0 (Low) SHORT = configuration image (High) opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX 0 onfiguration ate: Friday, January 0, 0 Sheet of
9 MX0 Power VP_V L0 0ohm, VP_V.u VP_V L VP_ORE 0ohm, 0u Notes: Place the 0uF cap close to ferrite bead. Place the 0.uF cap close to MX0 pin. REF_VP Notes: Put the caps close to MX0 pin. L 0ohm, 0.u R 0u VP_V 0u 0.u 0 u _VREF VP_V VP_V VP_V VP_V VP_V _VREF N VP_V N N0 M M M L L L0 K K T G G U R H H T J H H G J UG V V V V V V V V V V V_PLL V_PLL V_PLL V_PLL V V V V VINT V VREF NIN NIN MX 0 POWER VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO L K M L R P N N U U T T T0 U U U T T T R R P N N M L K K J H G G G F F G G0 F F VP Place filter close to VIO pins. 0.u VP VP VP VP VP VP L 0 ohm, 0. 00m VP 0M0F VP_ORE L 0ohm,. VP_V 0u 0.u Notes: Place the 0uF cap close to ferrite bead. Place the 0.uF cap close to MX0 pin. opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX0 Power ate: Friday, January 0, 0 Sheet of
10 MX0 Ground UH MX 0 GROUN TP REFGN Y Y Y W V V V U U0 T T T T R R P P P N N M M M M0 L L L L L H GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN NU REFGN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN N N K K0 K J J J J G G G G G F F0 E E 0 E F Notes: Place this F close to MX0 _VREF. L 0ohm, 0M0F. Use REFGN as ground reference.. Route analog input signal adjacent to VSSREF as possible. opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX0 Ground ate: Friday, January 0, 0 Sheet 0 of
11 MX0 ecoupling VP_V VP_V 0 0u 0u 0 u u u 0 u u u u u 0 n n 0 0n 0n 0.u 0.u 0.u 0.u Note: Place capacitor near FPG pins Notes: Place a uf cap close to each MX0 V pins. VP_V 0.u 0.u 0.u 0.u Notes: Place a 0.uF cap close to each MX0 V pins. VP.u.u 0.u 0.u 0 0.u 0.u 0.u 0.u 0.u 0.u 0.u 0.u 0.u 0.u 0V 0.u 0V 0.u 0V 0.u 0V 0.u 0V 0.u 0V 00 0.u 0V 0 0.u 0V Notes: Place these caps close to MX0 VIO, VIO, VIO, VIO and VIO pins. VP u u u 0.u 0.u 0.u 0.u 0n 0n opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev MX0 ecoupling ate: Friday, January 0, 0 Sheet of
12 Note: Place near I power pin VP 0.u 0V 0 0.u 0V 0.u 0V 0.u 0V 0.u 0V 0 0.u 0V 0.u 0V SRM RM_R[..0] RM_Q[..0] RM_LK RM_KE RM_LQM RM_UQM RM_WE_N RM_S_N RM_RS_N RM_S_N RM_0 RM_ VP RN.K R.K RM_S_N RM_RS_N RM_S_N RM_WE_N RM_KE RM_R0 RM_R RM_R RM_R RM_R RM_R RM_R RM_R RM_R RM_R RM_R0 RM_R RM_R RM_LK RM_KE RM_LQM RM_UQM RM_WE_N RM_S_N RM_RS_N RM_S_N RM_0 RM_ 0 0 U VP SRM Mx LK KE LQM UQM nwe ns nrs ns 0 V V V VSS VSS VSS 0 0 RM_Q0 RM_Q RM_Q RM_Q RM_Q RM_Q RM_Q RM_Q RM_Q RM_Q RM_Q0 RM_Q RM_Q RM_Q RM_Q RM_Q VQ VQ VQ VQ VSSQ VSSQ VSSQ VSSQ opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev SRM ate: Friday, January 0, 0 Sheet of
13 , GPIO GPIO_[..0] rduino igital Interface rduino_io[..0] rduino_reset_n nalog input interface IN[..] lock_in lock_in V VP GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO_ GPIO_ GPIO_0 GPIO_ GPIO_ GPIO JP x0_ox_header GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ V rduino_reset_n VP V L 0ohm, _IN0 _IN _IN _IN _IN _IN JP HEER JP HEER rduino UNO Rev rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io0 rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io0 JP 0 HEER 0 JP HEER SL S SK MISO MOSI SS IN R 0 p VP_V V+ V- + - VP_V U 0.u 0V MP-E/SL n 0V NI R R _IN IN R 0 p VP_V V+ V- + - VP_V U 0.u 0V MP-E/SL 0 n 0V NI R R _IN _IN _IN rduino_io rduino_io rduino_reset_n TP NI TP_YELLOW TP NI TP_YELLOW JP HEER x VP V rduino_io IN R 0 p VP_V U V+ + 0 V- - MP-E/SL n 0V NI R0 R _IN IN R 0 0 p VP_V V+ + V- - U MP-E/SL n 0V NI R R _IN0 rduino_io rduino_io rduino_reset_n R.K NI R.K NI R 0K rduino Pin out Pin. IN IN R 0 p R 0 p VP_V V+ + V- - VP_V U V+ + 0 V- - U MP-E/SL MP-E/SL n 0V NI n 0V NI R R R R _IN _IN IN IN R 0 p R0 0 p VP_V U V+ + V- - VP_V V+ + V- - MP-E/SL U MP-E/SL n 0V NI 0 n 0V NI R R R R _IN _IN opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. TP TP Pin. JP Pin. JP JP Pin. JP Pin. JP E0-Lite Size ocument Number Rev rduino Expansion Header ate: Friday, January 0, 0 Sheet of
14 SWITH KEY LE -segment isplay SW[..0] KEY[..0] LER[..0] HEX0[..0] HEX[..0] HEX[..0] HEX[..0] HEX[..0] HEX[..0] SW0 SLIE SW SW SLIE SW SLIE SW SLIE SW User IO, -Seg, LE VP VP VP VP SW SW SW SLIE SW VP VP VP VP SW SW SW SLIE SW SW SLIE SW VP SW VP SLIE SW SLIE SW SLIE SW VP RN 0 RN 0 RN0 0 SW SW SW SW0 SW SW SW SW SW SW HEX0 HEX0 HEX0 HEX00 HEX0 HEX0 HEX0 HEX0 HEX HEX HEX0 HEX HEX HEX HEX HEX HEX0 HEX HEX HEX HEX HEX HEX HEX HEX0 HEX HEX HEX HEX HEX HEX HEX RN K RN K RN K RN K RN K RN K RN K RN K P F0 G0 E0 0 P F G E P F G E P F G E HEX0 0 0 a 0 b 0 c 0 d E0 e F0 f G0 g P0 dp HEX 0 a b c d E e F f G g P dp HEX 0 a b c d E e F f G g P dp HEX 0 a b c d E e F f G g P dp Segment isplay Segment isplay Segment isplay Segment isplay VP VP VP VP VP RN 00K KEY0 TT SW KEY TT SW u 0V 0.u V TN0 TN u 0V U V SNU TN0 TN ETP Y Y Y Y 0 Y Y GN R00 R0 R0 R0 NI 0K 0K NI 0K 0K KEY0 KEY HEX0 HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX HEX0 HEX HEX HEX HEX RN K RN K RN K RN K P E G F P F G E HEX 0 a b c d E e F f G g P dp HEX 0 a b c d E e F f G g P dp Segment isplay Segment isplay VP VP LER0 LER LER LER LER LER LER0 LER LER LER RN 0 LER LER LER LER LER LER LER LER LER LER RN 0 LER LER LER LER LER LER LER LER RN 0 LER LER opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev LE, 'Segment, User I/O ate: Friday, January 0, 0 Sheet of
15 VG VG_R[..0] VG_G[..0] VG_[..0] VG_HS VG_VS VG and ccelerometer VG_R0 VG_R VG_R VG_R RN0 K RN K VG VG_G0 VG_G VG_G VG_G VG_0 VG_ VG_ VG_ RN RN K RN K K VG_R VG_G VG_ J 0 0 VG RN K VG_HS VG_VS R 0 R0 0 igital ccelerometer GSENSOR_SI GSENSOR_SLK GSENSOR_INT GSENSOR_INT GSENSOR_S_n GSENSOR_SO VP L V_Gsensor E L u 0V V_Gsensor V_VS E u 0V R.K NI.u.V 0.u 0V 0.u 0V igital ccelerometer Tie S_n to high to I mode only R.K NI U V GN RESERVE GN GN VS S_n SL_SLK S_SI_SIO SO_LT_RESS RESERVE_ N 0 INT INT XL V_Gsensor R 0K NI R.K NI R 0 R 0 R.K NI VP R.K R.K GSENSOR_SLK GSENSOR_SI GSENSOR_SO GSENSOR_INT GSENSOR_INT GSENSOR_S_n efault : I ddress 0x/0x opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev VG and ccelerometer ate: Friday, January 0, 0 Sheet of
16 V Power from US Port V_US JP Power - HR Input Power Range:. ~. V PMEG00E PMEG00E PMEG00E PMEG00E ZXV Power - V_IN /.V Power up Sequence: V---> VP, VP ---> VP_V Overvoltage Protection Threshold Voltage :. ~.V R 0 R0.K Q HE0G u 0V R 00K Q O R.K 0.u 0V NI V V u 0V P_POK VP_V R0 R 0 K NI V R 0 LEG Power Good Power LE Q UT00 NI R 0 V R 0 NI LEG NI V Power LE V U Ramp Time Tsoft-start = msec Switching Frequency :.MHz.V / P_POK 0u 0V 0 0u 0V 0 0u 0V 0u 0V SVIN PVIN_ PVIN_ PVIN_RV SW_ SW_ SW_ SW_ L 0nH VP VP Panasonic RTPE0MZ R 0.0 VP_V V V P_POK VP_ORE R 00K NI R 00K NI R 0 NI R 0 P_POK u 0V NI 0 PGOO RUN TRK/SS RT/SYN ITH MOE SGN PGN_EP VF R R 0K R 0K p + 0u.V 00u.V LTEU#TRPF MH MH MH MH P P FI FI FI FI FI FI FI FI FI FI FI0 FI opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev Power - V, V ate: Friday, January 0, 0 Sheet of
17 V U Power -.V /.V Ramp Time Tsoft-start = msec Switching Frequency :.MHz.V / P_POK 0u 0V V V 0u 0V R R 0u 0V 00K NI 00K 0u 0V P_POK u 0V NI 0 SVIN PVIN_ PVIN_ PVIN_RV PGOO RUN TRK/SS RT/SYN ITH MOE SGN PGN_EP SW_ SW_ SW_ SW_ VF R L 0nH R K R.K 0 p Panasonic TPE00MZ u 00u.V.V VP 00u.V VP VP L 0ohm, 0u.V VP_V 0.u 0V LTEU#TRPF V u 0V VP 0u 0V.V / 0. Ramp Time = msec REG IS IN LT0- OUT J SHN GN EP_GN R.K R 0K VP VP u.v R 0 R 0K NI.u NI U VIN VOUT ON O GN TPS NI VP_ORE.u 0V VP_ORE VP R0 0K.u NI V u 0V VP 0u 0V.V / 0. Ramp Time = msec REG IS IN SHN GN EP_GN LT0- OUT J R R.K K VP u.v VP.u 0V VP_V Voltage Reference 0.u 0V U VIN VOUT GN REF REF_VP 0.u 0V VP R 0K.u NI opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. E0-Lite Size ocument Number Rev Power -.V,.V,.V ate: Friday, January 0, 0 Sheet of
18 J US -TYPE + X EN - GN VUS R GN MHz M 0.u 0V V OUT NI V_US US_P US_M 0.u 0V U VP OS_ UT_LK_ V L + GN - 0.u 0V NI L TPEUS0 0 0u 0V V_UT 0ohm, 0ohm, NI R 0 NI R LK_MHz V_US VP p 0V R 0 R R UT_MX_ R 00K R 00K NI R 0 p 0V 0.u 0V VP R 0K 0.u 0V n V R.K US_RESETn EEPT EEPLK EEPS U0 VOUT RSTOUT# USP USM XTIN XTOUT RESET# EET EESK EES TEST VIO V 0 V V FTL GN GN GN 0 LQFP- 0 R# WR TXE# RXF# SI/WU 0 PWREN# 0.u 0V U0 U U U U U U U UR UWR UTXE URXF SI_WU PWRON V_UT 0.u 0V 0u.V VP R 0K URXF UTXE UWR UR UT_MX_ PWRON ULE LK_MHz US_RESETn SI_WU EEPT EEPLK EEPS U0 U U U U U U U ISP_TK ISP_TMS ISP_TI ISP_TO VP 0.u 0V 0.u 0V VP U VP 0 VINT VINT VIO VIO VIO VIO VIO VIO VP IO--0 IO--0 IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO--/GLK0 IO-- IO--/GLK IO-- IO-- IO--/GLK IO--0 IO--0/GLK IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- EPM0T00 IO-- IO--0 IO--0 IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO--0 IO--0 IO--/EV_OE IO-- IO--/EV_LRN IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- TK IO-- TMS IO--0 TI IO-- TO GNINT GNINT GNIO GNIO GNIO GNIO GNIO GNIO VP 0.u 0V 0 0.u 0V ONFIG_SEL ONF_ONE_ISP NONFIG NSTTUS ONF_ONE JTG_TI JTG_TO JTG_TMS JTG_TK JTG_EN VP 0.u 0V 0.u 0V 0 0 laster lock UT_LK_ JTG to MX0 (.V), JTG_TK JTG_TMS JTG_TI JTG_TO JTG_EN onfiguration NONFIG NSTTUS ONF_ONE ONFIG_SEL VP VP R0 0 R 0 LEG LO LEG ONF_ONE ULE ONF_ONE_ISP GN VP RN 0K ISP_TK ISP_TO ISP_TMS ISP_TI opyright (c) 0 by Terasic Inc. Taiwan. ll rights reserved. PL ISP VP E0-Lite J 0 Header_x NI 0.u 0V Size ocument Number Rev US laster ate: Friday, January 0, 0 Sheet of
COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT
LTER YLONE III EP evelopment & Education OR SHEMTI ONTENT PGE TOP MEMORY OVER PGE, TOP SRM,FLSH 0 ~ 0 0 ~ 0 ISPLY VG, LE, SEGMENT 0 ~ 0 IN/OUT LOK, PS, RS, UTTON, SWITH, ONNETOR,S R 0 ~ FPG yclone II EP
Quickfilter Development Board, QF4A512 - DK
Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U
8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1
isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion
KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power
KEIm aseboard REV TE PGES ESRIPTION.0.0 Oct//0 ll INITIL REVISION RELESE..0 Feb//0 ll MP REVISION RELESE PGE ESRIPTION lock iagram, History SoM onnector L onnector Ethernet URT nalog Peripheral Power KONO
HF SuperPacker Pro 100W Amp Version 3
HF SuperPacker Pro 00W mp Version Revised 0 0 V Stamps KOOR This is the third generation HF SuperPacker Pro 00W Version home construction project offered by HF Projects. This is a group construction project
RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7
Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
MSP430F16x Processor
MSP0x Processor V_. V_ V_. U Vcc Vcc R 0K SW, ETHER_T_00, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0, ETHER_T_0 P.0/TLK P./T0 P./T P./T P./SMLK P./T0 P./T P./T /RST/NMI 0.u P UTTON_
XO2 DPHY RX Resistor Networks
PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX
Cyclone V GX Starter Kit SCHEMATIC
yclone V GX Starter Kit SHEMTI ONTENT PGE over over Page lock iagram FPG Memory lock iagram FPG IO, lock, onfiguration and Power LPR ~ Memory Memory udio Video HSM SRM S ard udio OE HMI TX HSM Interface
#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N
P REVISION REOR J SP88 0 - RE N_JK P 90-00_-POS TP # - Remove these components to stack north # - Populate these components to stack north Use k Resistors or adjust as needed Header - Molex 90-0 PITORS,
ALEX +12VBUS PTC 1A J17 PTTOUT U1B 3V3 C IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR RUP3
F PT VUS J J V_LEX V LEX LEX_SPI_SO LEX_SPI_SO R R LEX_SPI_SK LEX_SPI_SK LEX_SPI_RX_LO LEX_SPI_RX_LO R LEX_SPI_TX_LO LEX_SPI_TX_LO R FW_PWR REV_PWR 0 LEX HR 0P LEX J HR P R PWR IN THRU HEER x/sm PTTOUT
ALEX +12VBUS PTC 1A J17 PTT U1B. 126 IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR. IO_VB1N1_9/DIFFIO_L7p/DQS2L/CQ3L/CDPCLK0 RUP3
F PT VUS J J HEER X V_LEX V LEX LEX_SPI_SO LEX_SPI_SO R R LEX_SPI_SK LEX_SPI_SK LEX_SPI_RX_LO LEX_SPI_RX_LO R LEX_SPI_TX_LO LEX_SPI_TX_LO R FW_PWR REV_PWR 0 LEX HR 0P LEX J HR P R PWR IN THRU FW_PWR REV_PWR
THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia
MicroL MicroLon.Sch Timers_nalog Timers_nalog.Sch IO ufferingsch IO uffering.sch Power Supply Power Supply.Sch Mitsubishi ackplane oard ate: THE UNIVERSITY OF NEWSTLE University rive allaghan NSW 0 ustralia
Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page
Intel Edison reakout Sept/0 V to V rick Power Supply V power supply and battery recharger SPI GPIO Intel Edison PWM I S URT 0 0" header US 0TG URT Level Shifter URT US FTI P P lient US Micro Type- lient
OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP
MU ROOTIS / ORO MU_NRESET R_[0..] R_[0..] R_ R_ R_ R_ R_ R_0 R_0 R_ R_ R_ R_ R_ R_ OTG_S_VUS OTG_S_N OTG_S_P OTG_S_I OTG_S_O OTG_S_PWR OTG_S_I OTG_S_N OTG_S_P OTG_S_O OTG_S_VUS UT_USER UT_USER SW_USER
CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-
SPST SW L 0uH.uF TP HEER NO STUFF TP 0 HEER NO STUFF TP TP pf Y.uF.uF 0 HEER NO STUFF 0 HEER NO STUFF MHz, 0ppm pf.uf (OUT) (IN) R 0K /W % 0uF OUT OUT OUT OUT KLT L 0 L_MISO L_MOSI L_SK S_S- L_S- L_- L_
B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History
0-SH-0 R-0 VEG STP0 (VI to PTx) Reference esign P# 00- Revision History SHEMTI SHEET ate uthor Version omments 0. ontents, Revision History Sept., 00 Tony W. Rev. Initial schematic. 0. Overview Oct., 00
REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
Reference Schematic for LAN9252-SPI/SQI+GPIO16 Mode
Reference Schematic for LN-SPI/SQI+GPIO Mode onfigurations SPI/SQI+GPIO Mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
Reference Schematic for LAN9252-HBI-Multiplexed Mode
Reference Schematic for LN-HI-Multiplexed Mode onfigurations HI Multiplexed mode EEPROM - F (High) Port mode Port0 & Port = opper Page No. Schematic Page Title Power Supply LN(Part) LN(Part), Strap & EEPROM
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board
ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).
THAT Corporation. QSC Digital Cinema Monitor DCM-2/DCM-3 Monitor Board
anyone without the written permission of THT orporation. escription ate 00 Released // 0 Per EO # /0/ pproved ataports,,, -00.SH VMON & IMON Input Select of -00.SH UNLESS OTHERWISE NOTE: ataports E,F,G,H
AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT + 0 uf SM or LMMPX-J REG_V VIN VOUT + 0uF 0 0.uF U R 0.0K % J R.K % REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09
Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with
AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115
PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.
VREF XREF=1/A1,1/B2,7/A2 C103 AVDD 0.1U VDDCORE DRVDD VDDIO ENC+ ENC- AIN+ OVR EC2 XREF=2/B2 XREF=2/B2 XREF=2/B2 XREF=2/A1 XREF=1/A1,7/B1 XREF=2/B2
--00_: RV;E,F,G,H,J,K,L,M,N,P,R V;H,H,J,J,K,K,L,L,M,M,N,N,P,P V;,,,,,,,E,E,F,F,G,G SMOE MOE S EXP EXP EXP0 HIPI HIIPI HIPI HIPI0 EXTFILTER GN_ GN_0 IN- IN+ EN- EN+ VREF V_ES N RY PLK PULK LK SYN SYN SYN
nrf52840-mdk V1.0 An Open-Source, Micro Development Kit for IoT Applications using the nrf52840 SoC Revision History Function Description Page Rev.
nrf0-mk V.0 n Open-Source, Micro evelopment Kit for IoT pplications using the nrf0 So Revision History Function escription Page Rev. escription Title Sheet V.0 The First Release Power Supply US.0 Hub PLink
CONTENTS: REVISION HISTORY: NOTES:
ONTENTS: PGE - ONTENTS PGE - POWER, XOS PGE - SI, SI, JTG PGE - S/eMM, US, HMI, GPIO, OMPOSITE PGE - SOIMM REVISION HISTORY: V.0 - /0/0 NOTES: These reduced schematics omit core SMPS and LPR circuitry
X-USBPD-C-SHIELD. 2 Block Diagram 3 Type-C Connector 4 USB3/USB2 5 PTN5110 PD TCPC 6 Shield Headers 7 PD Source and Sink LS 8 3V3, 5V0, 1V8 Supplies
Table of ontents lock iagram Type- onnector US/US PTN0 P TP Shield Headers P Source and Sink LS V, V0, V Supplies Rev escription ate pproved Prototype Release -Mar- K ring up to NL and make updates requested
Virtex 5 FF1738 DUT. Single Ended Socket Clocks 2X. Differential SMA Clocks 2X. Differential SMA MGT Clocks 2X D. Upstream Connector.
PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE 0- Power us and Switches
3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This
USBF USBF.prj. Title: Section: USBF-01. B Designer: Brian Ashelin Date: COMMUNICATIONS COMMUNICATIONS ADC ADC INPUT VCA 4 PAGE 7 PAGE 1 PAGE 5 PAGE 2
INPUT V INPUT V PGE PGE OMMUNITIONS OMMUNITIONS PGE INPUT V INPUT V PGE INPUT V INPUT V PGE POWER ISTRIUTION POWER ISTRIUTION PGE INPUT V INPUT V PGE LOK ISTRIUTION LOK ISTRIUTION PGE USF USF.prj 0th ve.
PCBA Rev 80.L9581G001 PCBA P/N: PCB P/N: PCB Rev 00.L9581G001. Title Content Size Document Number Rev C. A Date: Tuesday, December 15, 2009 FLD1.
ontent : P0_ontent P0_lock_iagram P0_FPG_I/O_ P0_FPG_I/O_ P0_FPG_Power&Memory P0_External_onnector P0_M_REG P0_I_Level_Shift P0_MU P0_Power pprover Jim esigner enson rawer enson P P/N: P Rev 0.LG00 P P/N:
S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.
Title Page lock iagram MU & rduino Headers OSM & Power Supply On-board Peripherials Revisions Rev escription ate -Jun- V.0 -Feb- pproved Microcontroller Product Group 0 William annon rive West ustin, T
Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0
Fiber LE RJ M RYSTL EEPROM SRM & FLSH POWER PWRJK Jumper for GPIOs URT Realtek Semiconductor orp. RTL(M)_FHG_V.0 Size ocument Number Rev lock diagram.0 ate: Tuesday, November, 00 Sheet of ,, /ISGPIOSTP
FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13
Table of ontents Title lock iagram KEZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Initial raft Revisions. Remove Motor ontrol onnector J. Remap J, J, J, J pinout. dd one series resister
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V
PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE -0 Power us and Switches V OR V JK RIK VINT VINT JK
SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:
R 0K0 RST U S_ PF/0V PF/0V 0FS FS T T 0SLK N SOT N SOT Y mhz U LS0 debug port 0 do not stuff R WR S PS X/Y IN/IN IR 0IR MO J R M R 0K0 R0 K00 R 0K0 dsck dr dsi dso / G 0 U LS0 R 0K0 SI_RX SI_TX SI_LK TFS
Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA
Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:
Table of ontents Notes lock iagram FXL000L / MU ircuit Power and attery harger ircuit Rev escription Revisions Original Release Remove signal line U- pin and add additional signal line between J-pin0 and
Generated by Foxit PDF Creator Foxit Software For evaluation only.
I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software
Virtex 5 FF1136 DUT. Single Ended Socket Clocks 2X. Differential SMA MGT Clocks 2X D. Differential SMA Clocks 2X. Upstream Connector.
PGE System Monitor ux PGE System Monitor PGE System ce Upstream PGE Upstream onnector PGE Single Ended Socket locks X PGE ifferential SM locks X PGE ifferential SM MGT locks X PGE - Power us and Switches
L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE
LX UGHTER RS TLE OF ONTENTS SL NO. ONTENTS PGE NO REV TLE OF ONTENTS VERSION HISTORY VERSION.0.. LOK IGRM URT-0 INTERFE N US INTERFE URT INTERFE PROFI US & SOFT IR INTERFE SOFT URTS REV NO. NTURE OF HNGE
P50V +IN 4 -VS AD8065AR. Cap Semi SH_CLEAR. C19 Cap Semi 0.1uF R210. Res3 15K, 1% P50V U VS -IN P50V. Vout +IN -VS AD8065AR SUB_TO_ADC
P0V PV J00 R_R R0 Res 00.uF JP0 Header R0 Res 0k 0 ode T 0.uF P0V R0 U0 Res.0K SH_UF 0R U0 OM V+ SH_MIN NO IN SH_SWITH SH_SWITH IN OM R0 GN NO Res 0 PI_ P0V R0 SH_MIN Res 0 0 pf mca SH_LER SH_LER U0 0R
EDP-AM-DIO54 Digital IO Module User Manual. This document contains information on the DIO54 digital IO module for the RS EDP system.
P-M-IO igital IO Module User Manual This document contains information on the IO digital IO module for the RS P system. Version v.0, 0/0/00 P-M-IO Manual ontents. igital IO Module. igital Outputs.... Using
VCC R4 10K ANA1 EXT-A1 EXT-A2 ANA2 C10 10NF/50V C11. DispKey.sch EXT-DATA EXT-SCK LCD-E KEY-E LCD-E. U_SpiUsb SpiUsb.
Title Number Revision Size A Date: 0..00 Sheet of File: C:\Altium00\..\Board.sch Drawn By: SW SW-D-B-0 RESET + C 00UF/V C 00NF/0V C 00NF/0V VIN VOUT IC LMM0 + C 0UF/V X NG-DC0A D N00 D N00 D N00 D N00
PCB NO. DM205A SOM-128-EX VER:0.6
V. M0 M M M M M M M MQM0 MQS0N MQS0P M M M0 M M M M M MQM MQSN MQSP U RM R0 Q00 M0 U Q0 M T Q0 M R Q0 M U Q0 M U Q0 M T Q0 M T Q0 M T M0 M U QS0N M U QS0P M0 M W0 Q0 M W Q0 M V0 Q0 M U0 Q M W Q W Q 0 V
C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.
Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P
INDEX/ RESET& EEPROM JINPIN ELECTRICAL COMPANY LTD.ZHUHAI.S.E.Z SF_CE SF_SO SF_CLK SF_SI SF_CE SF_SO SF_CLK SF_SI PC_SCL PC_SDA SCL SDA RST
N Updata /N P. R.K R 00 R 00 R.K P_SL P_S V R K SF_E U PMVF00 E SO WP VSS V HOL SK SI SF_LK V 0.UF/V SF_E SF_LK P_SL P_S SL S V SL' S' SF_E SF_LK P_SL P_S SL S V SL' S' U T 0 V WP SL S SL' S' 0.UF/V R
JP8 3 PIN BERG 3 PIN BERG 3 PIN CONNECTOR MIC JP4 JP5 MIC BIAS JP6 3 PIN BERG PTT PTT_IN R103 R85 1K R121 R130 CW_DOT CW_DASH
0uF FL PIN ONNETOR 0 0uF JP USROUT0 USROUT USROUT USROUT USROUT USROUT USROUT U 0 O0 O O O O O O OREF MOSI SSK ns MOE IN OUT LK LRIN LROUT MLK U RLINEIN SIN LLINEIN 0 SLK S ROUT MOE LOUT 0 IN RHPOUT OUT
Xilinx Virtex -E Evaluation Kit
Xilinx Virtex -E Evaluation Kit November, 000 (Version.) RFT Features FPG Xilinx Virtex-E XV00E-PQ0 SPROM Xilinx XV0SO0 oard I/O onnectors Two 0-pin, 0. Header connector Pads for three MITOR connectors
SNRgain ( d) log( Oversample Ratio) REVISIONS REV ESCRIPTION TE PPROVE VRV+ LU POWER SUPPLIES FPG SUPPLIES NLOG SUPPLIES R LO JUSTE TO.V PRZ-R U V REGULTES FPG VIO SUPPLIES TO.V P VIO -V GN +V +V -V
+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V
U1-1 R5F72115D160FPV
pf R NF_ X MHz, pf ON_XTL ON_EXTL R R NF_,,,, R NF_ R NF_ R R,,,, M M M_LK M_LK SEMn TI TMS TK TRSTn K R K R K R K R EXTL XTL M M M_LK M_LK TESTM SEMn TI TMS_WTX TK_WSK TRSTn_WRX U- RFFPV VREF VREFVSS
SVS 5V & 3V. isplsi_2032lv
PU 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 000pF 0 000pF 000pF 000pF 000pF 000pF 000pF 000pF FLSH.0uF.0uF.0uF 0.0uF ata uffer.0uf.0uf.0uf.0uf SVS V & V.0uF.0uF.0uF isplsi_0lv.0uf.0uf
2.5V 1.2V / 1.5V CORE 3.3V I/O MOUNTING HOLES GROUND TESTPOINTS +5.0V DC IN. SoC Solutions FB2 R K C12 15 PF FERRITE_BEAD C14 C C13 2.
+.0V IN J PJ-0 _ONN VUS JP JUMPERT VUS_FP 00 F FERRITE_E..V U TPS0 GN F TGN PF R.K % VP. R K %.V /.V ORE.V I/O U TPS0 JP VP JP HR VP_GL U TPS0 R.K LM0EM -. JP HR VORE_GL VORE. GN F TGN 0 PF R.K % R K %.
NOTE: please place R8 close to J1
Sheets, & /M_RESET PST T T0 +.V_MU R 0K /M_RESET PST T T0 +.V_MU 0.uF NOTE: please place J close to the edge of the P so that the debug cable is clear of the P when attached to the board J 0 0 M Header
All use SMD component if possible
R0 0K MF SW0 NEXT R0 0R LE0 STNY & POWER ON GN R0 SW0 PREV R 0 MF R 0 MF R 0K MF R0 K MF SW0 FF GN SNP OFF OR GN Q0 S Q0 S LE R k R k 00n R 0K MF M0 R0 K MF SW0 FR +V() Q0 R 0K MF GN R0 0 R 0 GN VF_on_off
Power USB I/F. USB->Uart AX309. Power LED :25:33 I:\AX\AX309\2.0\1_POWER.SchDoc VBUS VBUS D- D+ Fuse VCC GND D3V3 U
X0.0 0-- :: I:\X\X0\.0\_POWER.Schoc ate: R K Power LE LE SW SW V P P P V V F Fuse U SRV0- VUS P M RX TX LE RX LE TX R K R K VUS - I J US->Uart US I/F E 00uF/V OUT IN = U -. V E 00uF/V OUT IN = U -. V E
DO NOT POPULATE FOR 721A-B ASSY TYPE
V R 0 R 0 R 0 R 0 R 0 R 0 TP TP pf 000pF 000pF 000pF R R R R R K % 0.0uF R.0K % 000pF IFFOUT pf R K % R 0 0 UVJ R K % U LTUH PLLIN PLLFLTR F IFF IFFOUT SENSE SENSE SENSE RUN/ UVJ SGN LKOUT OOST TG G OOST
MUSIC. California Institute of Technology. HEMT Power Supply Precision Voltage Source. D. Miller 8/17/2011 REVISION RECORD LTR DATED: C31 5V_ID 10K
REVISION REOR EO NO: PPROVE: TE: V_I R 0K.V_REF V 0.uF _SHN V_IN GN GN U GN V_OUT_F V_OUT_S GN LT 0uF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT.V_REF R 0k 0uF IN IN VOS_TRIM VOS_TRIM U N OPE OUT 9 00pF
D28 D28 1N4001 1N4001 R301 R375 R k. 10k R82 R82. 47k. 47k USB_IN. 20k. 20k R87 R87 +3V. C uF. C uF GND +1V8. C uF.
POWER_KEY POWER_OFF US_IN WKEUP H_ET HG_STTUS PLYKEY +VRT VT VUS +VRT LI_.V LI_.V VUS VT VTT VTT VTT +V +V +V +V VTT V +V T uf uf R k R k uf uf R k R k VIN VOUT U XPM U XPM Vbat ON ON ON ON KW ON/OFF KW
Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.
PGE PGE X00 & X00 hip H/W onfiguration Pins MHz rystal RJ- onnector o H ebugger onnector I onfiguration EEPROM (T0) Power and y-pass apacitors Serial us Schematic: I : I EEPROM SPI : T EEPROM (optional)
Sheet_Symbol_Overspeed. HA_Vel_Feedback Dec_Vel_Feedback. HA_Overspeed_N Dec_Overspeed_N
NOTES: ISION LOK. Unless otherwise stated: Resistors are mw, % tolerance. apacitors are V, % tolerance.... J Port and Net Name scopes for this project are: Port NOT Global (connected via Sheet Symbols)
Service Information. Service. Service. Service FW-V220. Product Service Group CE Audio A02-160
Service Service Service W-V0 0-0 Product Service Group udio Service Information lready published Service Informations: ORRTION TO SRVI MNUL elow are corrections to the circuit diagram parts list: OMI OR
DOCUMENT NUMBER PAGE SECRET
OUMENT NUMER PGE SERET / SERET OUMENT NUMER PGE / Spartan onfiguration SPI Flash Q S V W/VPP HOL VSS U MPVME R 0 R.K 0.U 9 IO_LP 0 IO_LN VREF_ G IO_L9P_ G IO_L9N_ F IO_L0P_ F IO_L0N_ IO_L9P_ IO_L9N_ 0
12V SMPS_1_2 SMPS_4/5 SMPS6 VDD_CORE VDD_MPU VDD_DSP 5V0 PS_3V3 VDD_3V3 5V0 .01, C2 5V0_SNS 10.2K,1% 100uF,10V 1.91K PS_3V3 .
V.7uF,0V.LESR.7uF,0V.LESR 0.uf,V,00 R 69K U- U- U- V TO V U OOT VIN EN SS TPS.nF,0V,00 9 P PH GN 7 OMP 6 VSNS U- U-6 R SKFL-TP V0_OMP L.7uH V0_SNS V0 R 0.K,% R + 00uF,0V V0_TP V0 R.0,06 V SMPS SMPS_/ SMPS6
MT9V128(SOC356) 63IBGA HB DEMO3 Card
MT9V(SO) IG H MO ard Page escription Page lock iagram Pinout Sensor Power Supply VideoOut_lock_Reset xternal Interface Rev Who ate escription Rev 0.0 jwrede 0/0/0 ase Schematic for ustom esign Rev 0. aralex
PTN3356 Evaluation and Applicaiton Board Rev. 0.10
E PTN Evaluation and pplicaiton oard Rev. 0.0 REVISION STORY : ------------------------------------- 0. June 0, 0 - ase on PTN_ONLY_REV.SN 0. July, 0 - OM changes due to long lead time items, LEs 0. July,
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014
ON V_US M P GN SH SH US _WURTH_ R ZERO.JTN R US US R n N.K_P.KLTN Q U_, V_N TP SISTETN INRUSH IRUIT x Header_KN n N R ZERO.JTN ZERO.JTN Notes: o not install R if URT Vcc_Reg is connected to V (Vcc_US),.Uf,.V,
+12V R17 100K +12V R18 100K R19 100K R20 100K AVPP BVPP. C21 0.1uF. C20 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V SHN 0
05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0
0 - limentacion 0 - onector Externo 0 - daptacion Puerto Serie 0 - Modem SIM00 TT_VOLTGE VN_ TX TX_U RX_GSM RX_GSM HRGE_STTUS P. RX RX_U TX_GSM TX_GSM ST_ ST_ P. P. P. P. R 0 R 0 TR_U RI_U TR_GSM TR_GSM
LED POWER STAGE1 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE2 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE3 NOT_EN LED+ PWM
MU LE POWER STGE MU MX LI LI_TX LI_RX THERMISTOR- MX_RX MX_TX MX_E MX_/RE EN_ EN_ EN_ EN _ V LE Power Stage LE POWER STGE LE+ LE- LE+ LE- R R 0 J 0 Way 0 LI_TX LI_RX MX_RX MX_TX MX_E MX_/RE V LE Power
LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND
R White R Red _TX_Q_P J 0-0 0 _TX_I_P _TX_I_N _TX_Q_P _TX_Q_N L _TX_I_P _TX_I_N.R -d ttenuator.r.r 00pF_0V JP SM _TX_Q_P _TX_Q_N _TX_Q_P _TX_Q_N GN VV VV VV_TX VV VV VV_TX Modulator L L PowerSupply J POWER
Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.
Project: ate Version Items V.0 RWN Y PORJET SIM800+SIM8M_VTS Reference ONTENT HEKE Y V.0 SHEET of 7 POWER POWER -0V F0 0 L0 VIN LO X0 SM0 SWRH07 uh T-PIN-X TVS0 Z0 + 0 VT U0 VZ=V,Pd=W SM7 00uF V GN VOUT
VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD
POWER ELETRONIS **- Switching Power Regulation** V and.v outputs are isolated from High Voltage, but not each other Isolated Power Supply power.sch FTI US URT FTI US URT ftdi_uart.sch Safety Loop Wiring
2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM
Table of ontents Notes MS0LGLK Touch Sensors Touch Sensors Power OSM US OM L Revisions Rev escription X First raft X Replaced, M RN with sigle resistors Updated Power section Swapped LE_ER, with ER, to
FREEDOM KL25Z. 1 Title 2 Block Diagram 3 KL25Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 04/10/12 M.
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev X escription Revisions Initial raft ate 0/0/ pproved M. NORMN Release to production 0/0/ M. NORMN X hanges made
CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H
V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H
J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET
GP0 GP0 GP0 P0 GP0 GP GP GP GP GP GP GP P GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP0 GP GP GP GP GP GP GP GP00 UINO ONE PIN EFINE GP0 GP GP GP GP GP GP GP GP0 GP GP
RTL8211DG-VB/8211EG-VB Schematic
RTL8G-V/8EG-V Schematic REV..8 Page Index. Page. PHY. MI. M. Power. History RTL8G/8EG Size ocument Number Rev.8 TITLE PGE ate: Sheet of External clock and rystal RTL8G/8EG GMII/RGMII Interface LK_M ENSWREG
R2 44.2K_1% 5DVCC 5DVCC GND COMP SS24 DW1. EC2 470uF/16V. 470uF/16V 内内内内内内 DW2; 去去 U103,L9 33V. 33V C15 NC/10uF 33V C17 D2 NC/UDZ33B-33V
JK_P JP V V L 0u/N F FUSE() FUSE E 0uF/V E. V L 0u/N V 00nF 00nF V, R 00K 00nF U MP IN EN SS OMP 0nF S SW F 0.nF R K SW L u R.K_% R 0K_% V E 0uF/V V,,, ST-V V 00nF.uF 00P SS W ST-V E 0uF/V E 00nF TO U
Desired Part Placement. Max current set to 3A (motor Drive is 2.5A) SCI-DRV8814-MVK Mike Claassen B1 Dawn Ritz 40V. VDC_In GND. Board Test Points TP1
SI_x_NLG_H_[:] P P SI_x_SPI_MISO SI_x_SPI_MOSI SI_x_SPI_LK SI_x_SPI_S FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ FE/SI_OM_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_ SI_x_NLG_H_
Revision History. EFR32 Mighty Gecko Dual PHY Radio Board. 2.4 GHz 13dBm / MHz 14 dbm, DCDC to PAVDD. Board Function Page. Rev.
EFR Mighty Gecko ual PHY Radio oard. GHz dm / 868-9 MHz dm, to PV oard Function Page Title Page History Rev. escription. GHz RF, ntenna & Power 00 Prototype version. SubGHz RF, ntenna & Power EFR, PRO
FREEDOM KL26Z. Table of Contents 1 Title 2 Block Diagram 3 KL26Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply FRDM-KL26Z.
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Rev Revisions & hange Log escription ate Initial raft Feb// pproved listair * MU Pin assignments changed for Feb// listair
XBee Interface Board XBIB-U-DEV TH/SMT Hybrid
0 ONI N RST V X_V P ONRVSM00 X_V Populate jumper to switch rf output to onboard RPSM P TSW00S SW T00Q SW T00Q R 0 X_V R0 TI TMS T TO R IN T R P TSW0 0 0 urrent Testing TSW00S P R OUT IO RSSI_PWM PWM TR/PIN_SP
FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
ALTERA Cyclone V SoC Development & Education Board (DE1-SoC)
LTER yclone V So evelopment & Education oard (E-So) PGE ONTENT PGE ONTENT over Page V VG 0 lock iagram PG NK, NK PG NK, NK PG NK, NK PG locks, PG onfiguration PG ecoupling PG Power US laster II JTG hain
V Player Main oard (MT/MTR & SONY ). IN. SRVO PIK-UP & RIVR. MT/MTR O. SRM & SH. UIO & VIO OUT. UIO V & SRT ON PH- p p Name Pin ardmi() G/G
www.ma.com 原理图 型号 : 客户 : VP-G 内销 编号 : 版本 : 拟制 : 庄森燃 审核 : 批准 : 受控状态 : 备注 : 生效日期以批准日期为准 www.ma.com V Player Main oard (MT/MTR & SONY ). IN. SRVO PIK-UP & RIVR. MT/MTR O. SRM & SH. UIO & VIO OUT. UIO V &
POWER Size Document Number Rev Date: Friday, December 13, 2002
R0 [ /W 0 0.00uF/00V - D0 KP0M L0 L D0 N 0 00uF/00V 0 0.uF R0 M [ /W R0 M [ /W R0 M [ /W R0 M [ /W 0 0.00uF/KV D0 PS0R 0 0uF R0 00K [ W D0 FR0 R0 0 [ /W O O T0 O,, POWER X'FMR 0, D0 DQ0 R [ /W 0.00uF/00V
DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.
R * SPIF output x Power LO R * R R SPIF input x POR Flash PWM LE x PM00 Lightning() P 0x0 0pin Type connector US 0pin For Lightning & P T0 RE PLY0 PLY H Sel Stereo T0 PLY0 T0 0x PLY 0x PM00 R Ext. MU H
5V_EXT J3-1 J3-1 5CSX_4A_IO39 5CSX_4A_IO37 5CSX_4A_IO40 UART0_CTS 5CSX_4A_IO32 UART0_RTS 5CSX_4A_IO29. 5CSX_IOp0 5CSX_IOn0. 5CSX_IOp1 5CSX_IOn1
JTG hain US to URT L RJ Socket PHY Micro S ard Socket HPS IO 空置 00-00 Soaseoard.(Final) PHY connect_.v V_EXT JTG_FPG_TO S_LK connect_.v SX IO N_RX connect_.v URT_TS URT_RTS RT_T S_ S_M S_T S_T S_T S_T0
SM XBEE MODULE XBEE SMT MODULE NC GND GND RF_SELECT VCC COMM/AD0/DIO0 AD1/DIO1 DOUT/DIO13 AD2/DIO2 DIN/CONFIG/DIO14 DIO12 AD3/DIO3 RESET RTS/DIO6
0 ONI N RST SW T00Q R 0 X_V R0 TI TMS T TO R IN T R V P TSW0 0 urrent Testing TSW00S P R OUT IO RSSI_PWM PWM X_V 0 0u/0V R R R R R R TR/PIN_SP 0u 00n p.p X_OUT X_IN X_IO X_RST X_PWM X_/MS_X X_TR/PIN_SP
01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES
Table of ontents 0 TITLE PGE 0 MU 0 EUG INTERFE 0 SUPPLY 0 POWER RIGE 0 MOSFET RIVERS / VI SENSING utomotive Product Group 0 William annon rive West ustin, T 9 esigner:. ZUZEK rawn by:. ZUZEK pproved: