Cyclone V GX Starter Kit SCHEMATIC

Transcription

1 yclone V GX Starter Kit SHEMTI ONTENT PGE over over Page lock iagram FPG Memory lock iagram FPG IO, lock, onfiguration and Power LPR ~ Memory Memory udio Video HSM SRM S ard udio OE HMI TX HSM Interface User Interface GPIO - x Header and rduino Interface User Interface Switch and Key User Interface LE and 'Segment URT URT to US ridge Power Power ~ opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev over Page ate: Wednesday, ugust, Sheet of

2 opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev lock iagram ate: Friday, November, Sheet of

3 U- U- YLONE V GX NK R YLONE V GX NK SW SW RLP_S_n RLP_S_n SW SW SW SW RLP_ RLP SO _SI T U W Y R T W Y ank VIO =.V ank VIO =.V V SW RLP_OT_RZQ E IO_/IFFIO_TX_P/Q IO_/IFFIO_TX_P/Q V IO_/RZQ_/IFFIO_TX_N IO_/IFFIO_TX_N/ IO_/IFFIO_TX_N/ IO_/IFFIO_RX_P/Q IO_/IFFIO_RX_P/Q E RLP_Q IO_/IFFIO_RX_N/Q IO_/IFFIO_RX_N/Q N RLP_K_p IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_RX_P/QS/_SN_ IO_/IFFIO_RX_P/QS/_K P RLP_K_n RLP_Q Y IO_/IFFIO_TX_N/ IO_/IFFIO_RX_N/QSN/_SN_ IO_/IFFIO_RX_N/QSN/_KN E RLP_ RLP_Q IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_TX_P IO_/IFFIO_TX_P/ F RLP_ RLP_QS_p V IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_TX_N/Q IO_/IFFIO_TX_N/Q/ RLP_QS_n W IO_/IFFIO_RX_P/QS/_QS_ IO_/IFFIO_RX_P/QS/_QS_ IO_/IFFIO_TX_P/Q SW IO_/IFFIO_RX_N/QSN/_QSN_ IO_/IFFIO_RX_N/QSN/_QSN_ IO_/IFFIO_TX_N/Q U RLP_ RLP_Q IO_/IFFIO_TX_P/_OT_ IO_/IFFIO_TX_P/_RESETN IO_/IFFIO_RX_P/Q/ IO_/IFFIO_RX_P/Q/ U RLP_ RLP_Q IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_RX_N/Q/ IO_/IFFIO_RX_N/Q/ SW E IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ RLP_Q W IO_/IFFIO_TX_N/Q/_OT_ IO_/IFFIO_TX_N/Q/ E RLP_ RLP_Q Y IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_TX_P/Q IO_/IFFIO_TX_P/Q/ F RLP_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_TX_N/Q IO_/IFFIO_TX_N/Q/ IO_/IFFIO_RX_P/ RLP_M F IO_/IFFIO_RX_N/ RLP_Q F IO_/IFFIO_TX_P/Q/_M_ IO_/IFFIO_TX_P/Q/_M_ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_N/Q/_Q_ V W E F F F T U E E RLP_Q RLP_Q RLP_Q RLP_QS_p RLP_QS_n SW RLP_Q RLP_Q RLP_Q RLP_Q RLP_M RLP_Q, GXFFN LPR Interface RLP_[..] RLP_K_p RLP_K_n RLP_KE[..] RLP_S_n[..] RLP_M[..] RLP_Q[..] RLP_QS_p[..] RLP_QS_n[..] SWITH -SEGMENT SW[..] Interface HEX_[..] HEX_[..] _ONVST _SK _SO _SI RLP_Q RLP_Q RLP_Q RLP_QS_p U RLP_QS_n V RLP_KE E RLP_Q F RLP_Q E RLP_KE F RLP_Q RLP_Q RLP_M RLP_Q E F IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_N/ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_P/QS/_QS_ IO_/IFFIO_RX_N/QSN/_QSN_ IO_/IFFIO_TX_P/_KE_ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_N/Q/_KE_ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_TX_P/Q/_M_ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_N/ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_P/QS/_QS_ IO_/IFFIO_RX_N/QSN/_QSN_ IO_/IFFIO_TX_P/ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_N/Q/ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_P/ IO_/IFFIO_RX_N/ IO_/IFFIO_TX_P/Q/_M_ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_N/ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_P/QS/_QS_ IO_/IFFIO_RX_N/QSN/_QSN_ IO_/IFFIO_TX_P/ IO_/IFFIO_TX_N/Q/_Q_ IO_/IFFIO_TX_P/Q/_Q_ IO_/IFFIO_TX_N/Q/ IO_/IFFIO_RX_P/Q/_Q_ IO_/IFFIO_RX_N/Q/_Q_ IO_/IFFIO_RX_P/ IO_/IFFIO_RX_N/ IO_/IFFIO_TX_P/Q/_M_ IO_/IFFIO_TX_N/Q/_Q_ E E W W E F F U U E F E F Y V V E Y Y V W RLP_Q RLP_Q RLP_Q RLP_QS_p RLP_QS_n RLP_Q RLP_Q RLP_Q RLP_Q RLP_M RLP_Q HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX ONVST _SK GXFFN opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev FPG NK & ate: Wednesday, ugust, Sheet of

4 U- U- YLONE V GX NK YLONE V GX NK GPIO GPIO GPIO GPIO GPIO GPIO GPIO W W Y Y T U VIO =.V ank IO_/RZQ_/IFFIO_TX_RP/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR ank VIO =.V IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QSR IO_/IFFIO_RX_RN/QSNR IO_/IFFIO_TX_RP IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_RX_RP/QSR IO_/IFFIO_RX_RN/QSNR IO_/IFFIO_TX_RP IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN V V T T R P R R U V T R P P W W N P U U HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_VS HMI_TX_HS SRM_ SRM_ SRM_ SRM_ SRM_E_n SRM_OE_n SRM_WE_n SRM_L_n SRM_U_n GPIO GPIO GPIO SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ J J IO_/IFFIO_TX_RP/QR N IO_/IFFIO_TX_RN/QR M IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR N M IO_/IFFIO_RX_RP/QSR G IO_/IFFIO_RX_RN/QSNR H IO_/IFFIO_TX_RP M IO_/IFFIO_TX_RN/QR M IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR E IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN E E IO_/IFFIO_TX_RP/QR K IO_/IFFIO_TX_RN/QR K IO_/IFFIO_RX_RP/QR F IO_/IFFIO_RX_RN/QR G IO_/IFFIO_TX_RP/QR L IO_/IFFIO_TX_RN/QR L IO_/IFFIO_RX_RP/QSR H IO_/IFFIO_RX_RN/QSNR H IO_/IFFIO_TX_RP H IO_/IFFIO_TX_RN/QR J IO_/IFFIO_RX_RP/QR F IO_/IFFIO_RX_RN/QR G IO_/IFFIO_TX_RP/QR L IO_/IFFIO_TX_RN K IO_/IFFIO_RX_RP IO_/IFFIO_RX_RN GXFFN ank VIO =.V IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QSR IO_/IFFIO_RX_RN/QSNR IO_/IFFIO_TX_RP IO_/IFFIO_TX_RN/QR IO_/IFFIO_RX_RP/QR IO_/IFFIO_RX_RN/QR IO_/IFFIO_TX_RP/QR IO_/IFFIO_TX_RN H H J J E G F E F SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ GXFFN HMI TX HMI_TX_[..] HMI_TX_VS HMI_TX_HS SRM SRM_[..] SRM_[..] SRM_E_n SRM_OE_n SRM_WE_n SRM_L_n SRM_U_n,,, GPIO GPIO[..] opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev FPG NK & ate: Wednesday, ugust, Sheet of

5 U- U- YLONE V GX NK YLONE V GX NK HSM_ HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n H J H H G G ank VIO =.V ank VIO =.V LEG IO_/RZQ_/IFFIO_TX_TN LEG IO_/IFFIO_TX_TP/QT/T IO_/IFFIO_TX_TP/QT LEG H IO_/IFFIO_TX_TN/QT/T IO_/IFFIO_TX_TN/QT LEG H IO_/IFFIO_RX_TP/QT/T IO_/IFFIO_RX_TP/QT/T IO_/IFFIO_RX_TN/QT/T IO_/IFFIO_RX_TN/QT/T IO_/IFFIO_RX_TP/ IO_/IFFIO_TX_TP/QT IO_/IFFIO_RX_TN/ HSM_TX_p URT_RX M IO_/IFFIO_TX_TN/QT IO_/IFFIO_TX_TP/QT/T_M_ IO_/IFFIO_TX_TP/QT/T_M_ HSM_TX_n URT_TX L IO_/IFFIO_RX_TP/QST/T_K IO_/IFFIO_RX_TP/QST/T_SN_ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_TX_TN/QT/T_Q_ E HSM_RX_p U_XK IO_/IFFIO_RX_TN/QSNT/T_KN IO_/IFFIO_RX_TN/QSNT/T_SN_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ F HSM_RX_n U_LK E IO_/IFFIO_TX_TP/T IO_/IFFIO_TX_TP IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ HSM_TX_p U_T H IO_/IFFIO_TX_TN/QT/T IO_/IFFIO_TX_TN/QT IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ HSM_TX_n U_LRK G IO_/IFFIO_RX_TP/QT IO_/IFFIO_RX_TP/QT IO_/IFFIO_TX_TN/QT/ IO_/IFFIO_TX_TN/QT/ L HSM_RX_p U_T IO_/IFFIO_RX_TN/QT IO_/IFFIO_RX_TN/QT IO_/IFFIO_RX_TP/QST/T_QS_ IO_/IFFIO_RX_TP/QST/T_QS_ K HSM_RX_n U_LRK IO_/IFFIO_TX_TP/QT IO_/IFFIO_TX_TP/QT IO_/IFFIO_RX_TN/QSNT/T_QSN_ IO_/IFFIO_RX_TN/QSNT/T_QSN_ HSM_TX_p IO_/IFFIO_TX_TN/ IO_/IFFIO_TX_TN/ IO_/IFFIO_TX_TP/ IO_/IFFIO_TX_TP/T_RESETN HSM_TX_n IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_TX_TN/QT/T_Q_ HSM_RX_p IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ HSM_RX_n GXFFN IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ HSM_TX_p IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ HSM_TX_n IO_/IFFIO_TX_TN/ IO_/IFFIO_TX_TN/ IO_/IFFIO_RX_TP/ IO_/IFFIO_RX_TN/ F G K J G F K J H J L K E LER LER LER LER LER LER LER LER LER LER LEG LEG LEG LEG HSM_TX_p HSM_TX_n HSM_RX_p E HSM_RX_n E HSM_TX_p HSM_TX_n HSM_RX_p J HSM_RX_n J HSM_LKOUT_p HSM_LKOUT_n HSM_RX_p HSM_RX_n HSM_LKOUT_p HSM_LKOUT_n HSM_ HSM_ H H IO_/IFFIO_TX_TP/QT/T_M_ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TN/QT/ IO_/IFFIO_RX_TP/QST/T_QS_ IO_/IFFIO_RX_TN/QSNT/T_QSN_ IO_/IFFIO_TX_TP/ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TN/ IO_/IFFIO_RX_TP/ IO_/IFFIO_RX_TN/ IO_/IFFIO_TX_TP/QT/T_M_ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TN/QT/T_KE_ IO_/IFFIO_RX_TP/QST/T_QS_ IO_/IFFIO_RX_TN/QSNT/T_QSN_ IO_/IFFIO_TX_TP/T_KE_ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TN/ E N M F E E E HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n IO_/IFFIO_TX_TP/QT/T_M_ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ IO_/IFFIO_TX_TN/QT/T_OT_ IO_/IFFIO_RX_TP/QST/T_QS_ IO_/IFFIO_RX_TN/QSNT/T_QSN_ IO_/IFFIO_TX_TP/T_OT_ IO_/IFFIO_TX_TN/QT/T_Q_ IO_/IFFIO_RX_TP/QT/T_Q_ IO_/IFFIO_RX_TN/QT/T_Q_ IO_/IFFIO_TX_TP/QT/T_Q_ G F M L E HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_TX_p HSM_TX_n HSM_RX_p HSM_RX_n HSM_ udio OE U_XK U_LK U_T U_LRK U_T U_LRK HSM Interface HSM_TX_p[..] HSM_TX_n[..] GXFFN LE LER[..] LEG[..] HSM_RX_p[..] HSM_RX_n[..] URT to US URT_RX HSM_[..] URT_TX HSM lock output HSM_LKOUT_p[..] HSM_LKOUT_n[..] opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev FPG NK & ate: Wednesday, ugust, Sheet of

6 XVR Reference lock REFLK_p[..] U- REFLK_n[..] YLONE V GX Transceiver HSM Transceiver HSM_GX_TX_p[..] HSM_GX_TX_n[..] HSM_GX_RX_p[..] HSM_GX_RX_n[..] HSM_GX_RX_p HSM_GX_RX_n HSM_GX_RX_p HSM_GX_RX_n HSM_GX_RX_p HSM_GX_RX_n REFLK_p REFLK_n Y Y V W GX_RX_LP,GX_REFLK_LP GX_RX_LN,GX_REFLK_LN GX_RX_LP,GX_REFLK_LP GX_RX_LN,GX_REFLK_LN GX_RX_LP,GX_REFLK_LP GX_RX_LN,GX_REFLK_LN REFLKLP REFLKLN GX_L GX_TX_LP GX_TX_LN GX_TX_LP GX_TX_LN GX_TX_LP GX_TX_LN E E HSM_GX_TX_p HSM_GX_TX_n HSM_GX_TX_p HSM_GX_TX_n HSM_GX_TX_p HSM_GX_TX_n R HSM_GX_RX_p HSM_GX_RX_n SM_GX_RX_p SM_GX_RX_n V V T T M M GX_RX_LP,GX_REFLK_LP GX_RX_LN,GX_REFLK_LN GX_RX_LP,GX_REFLK_LP GX_RX_LN,GX_REFLK_LN GX_RX_LP,GX_REFLK_LP GX_RX_LN,GX_REFLK_LN GX_L GX_TX_LP GX_TX_LN GX_TX_LP GX_TX_LN GX_TX_LP GX_TX_LN W W P P K K HSM_GX_TX_p HSM_GX_TX_n SM_GX_TX_p SM_GX_TX_n REFLK_p REFLK_n N P REFLKLP REFLKLN RREF_TL R K GX_L R H H F F GX_RX_Lp,GX_REFLK_Lp GX_RX_Ln,GX_REFLK_Ln GX_RX_Lp,GX_REFLK_Lp GX_RX_Ln,GX_REFLK_Ln GX_RX_Lp,GX_REFLK_Lp GX_RX_Ln,GX_REFLK_Ln GX_TX_Lp GX_TX_Ln GX_TX_Lp GX_TX_Ln GX_TX_Lp GX_TX_Ln G G E E R M L REFLKLp REFLKLn GX L is FPG only GXFFN J J.u SM_GX_RX_p SM_GX_TX_p SM SM J J.u SM_GX_RX_n SM_GX_TX_n SM SM opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev FPG NK Transceivers ate: Tuesday, ugust, Sheet of

7 LPR KEY RLP_ RLP_ KEY[..] GPIO (LOK IN/OUT) GPIO GPIO,,, HMI TX GPIO I Interface HMI_TX_LK HMI_TX_E HMI_TX_INT GPIO[..] I_S R K LOK HMI_TX_INT KEY KEY LOK p LOK n KEY KEY T T P P U V Y Y U- YLONE V GX lock ank VIO =.V IO_/LKP,FPLL_L_FP/IFFIO_RX_P IO_/FPLL_L_LKOUT,FPLL_L_LKOUTP,FPLL_L_F/IFFIO_TX_P/Q/ IO_/LKN,FPLL_L_FN/IFFIO_RX_N IO_/FPLL_L_LKOUT,FPLL_L_LKOUTN/IFFIO_TX_N/Q/ IO_/LKP/IFFIO_RX_P IO_/LKN/IFFIO_RX_N ank VIO =.V IO_/LKP/IFFIO_RX_P IO_/LKN/IFFIO_RX_N IO_/LKP/IFFIO_RX_P IO_/LKN/IFFIO_RX_N F F RLP_ RLP_ GPIO GPIO HSM lock HSM_LKOUT HSM_LKIN HSM_LKIN_p[..] HSM_LKIN_n[..] XVR Reference lock REFLK_p[..] REFLK_n[..] LOK p HSM_LKIN_p HSM_LKIN_p I_SL R R R LOK n HSM_LKIN_n HSM_LKIN_n LOK GPIO GPIO GPIO LOK GPIO GPIO GPIO LOK I_S HSM_LKIN_p HSM_LKIN_n R P T T N M K K H G G G IO_/LKP/IFFIO_RX_RP IO_/LKN/IFFIO_RX_RN IO_/LKP,FPLL_R_FP/IFFIO_RX_RP IO_/LKN,FPLL_R_FN/IFFIO_RX_RN IO_/LKP/IFFIO_RX_RP IO_/LKN/IFFIO_RX_RN IO_/LKP,FPLL_TR_FP/IFFIO_RX_RP IO_/LKN,FPLL_TR_FN/IFFIO_RX_RN IO_/LKP/IFFIO_RX_TP IO_/LKN/IFFIO_RX_TN IO_/LKP/IFFIO_RX_TP IO_/LKN/IFFIO_RX_TN ank VIO =.V IO_/FPLL_R_LKOUT,FPLL_R_LKOUTP,FPLL_R_F/IFFIO_TX_RP/QR IO_/FPLL_R_LKOUT,FPLL_R_LKOUTN/IFFIO_TX_RN/QR ank VIO =.V IO_/FPLL_TR_LKOUT,FPLL_TR_LKOUTP,FPLL_TR_F/IFFIO_TX_RP/QR IO_/FPLL_TR_LKOUT,FPLL_TR_LKOUTN/IFFIO_TX_RN/QR ank VIO =.V Y Y F G HMI_TX_LK HMI_TX_E GPIO GPIO VP VP VP VP VP HSM_LKIN_p HSM_LKIN_n HSM_LKIN LOK L K N M IO_/LKP,FPLL_TL_FP/IFFIO_RX_TP IO_/LKN,FPLL_TL_FN/IFFIO_RX_TN IO_/LKP/IFFIO_RX_TP IO_/LKN/IFFIO_RX_TN ank VIO =.V IO_/FPLL_TL_LKOUT,FPLL_TL_LKOUTP,FPLL_TL_F/IFFIO_TX_TP/QT/T IO_/FPLL_TL_LKOUT,FPLL_TL_LKOUTN/IFFIO_TX_TN/QT/T HSM_LKOUT I_SL.u V.u V.u V.u V.u V.u V GXFFN VP I_SL I_S p V R R p V Y.MHz VP VP R K R K SI_SL SI_S efault : I ddress xe/e U LKIN_P LKIN_N LKIN I_LS FK_P FK_N LK.V MOS LK LK.V LVS LK LK.V LVS LK LK.V LVS LK SL S SI V V VO VO VO VO INTR RSV_ EP VP VP VP VP VP SI_INTR PLL OUT PLL OUT LK n LK p LK n LK p LK n LK p VP R K R R R R TP LOK LOK LOK n LOK p.u V REFLK_n.u V REFLK_p.u V REFLK_n.u V REFLK_p VP R K X EN.u V MHz V OUT SNVT IR = Low : data to bus OS_ IR.u V VP VP U V V OS_ LOK R R LOK LOK VP opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved..u V yclone V GX Starter Kit Size ocument Number Rev FPG lock ate: Friday, November, Sheet of

8 ,,,, US laster PU_RESET Micro S ard GPIO HSM JTG ST_TK ST_TMS ST_TI ST_TO PU_RESET_n S_LK S_M S_T[..] GPIO[..] EPQ Interface HSM_JTG_TK HSM_JTG_TMS HSM_JTG_TI HSM_JTG_TO EPQ_S_T EPQ_S_T EPQ_LK EPQ_nSO FPG_ONF_ONE R p V esign Note: Optional termination resistor for LK Note: Place near FPG LK pin JTG_FPG_TK R K FPG_ONF_ONE FPG_nSTTUS FPG_nONFIG FPG_nE R p V VP VP VP R K R K VP R K RN K R K JTG_FPG_TK Y JTG_FPG_TMS JTG_FPG_TI R T JTG_FPG_TO V EPQ_LK EPQ_S_T EPQ_S_T EPQ_S_T EPQ_S_T N F U EPQ_nSO Y S_T U S_T T S_T V S_T T S_LK S_M W GPIO GPIO Y GPIO GPIO R GPIO Y GPIO R GPIO F U- YLONE V GX onfiguration ank ank TK TMS VIO =.V VIO =.V TI IO_/INIT_ONE/IFFIO_RX_RP TO IO_/EV_OE/IFFIO_TX_RP LK IO_/EV_LRN/IFFIO_TX_RN/QR S_T,SO/T S_T/T IO_/R_ERROR/IFFIO_RX_RN S_T/T S_T/T IO_/nEO/IFFIO_TX_RP/QR nso/t IO_/nPERSTL/IFFIO_RX_RP/QSR IO_/T/IFFIO_TX_N IO_/VP_ONFONE/IFFIO_TX_RN/QR IO_/T/IFFIO_RX_N/Q IO_/T/IFFIO_TX_P/Q IO_/nPERSTL/IFFIO_RX_RN/QSNR IO_/T/IFFIO_RX_P/Q IO_/T/IFFIO_TX_N/Q IO_/PR_REQUEST/IFFIO_TX_RN/QR IO_/T/IFFIO_RX_N/QSN IO_/T/IFFIO_TX_P IO_/T/IFFIO_RX_P/QS IO_/T/IFFIO_TX_N/Q IO_/PR_REY/IFFIO_TX_N/Q IO_/T/IFFIO_RX_N/Q IO_/T/IFFIO_TX_P/Q IO_/PR_ERROR/IFFIO_RX_P IO_/LKUSR/IFFIO_RX_P/Q IO_/PR_ONE/IFFIO_RX_N IO_/IFFIO_TX_P/Q ONF_ONE nsttus nonfig ne GXFFN ank MSEL MSEL MSEL MSEL MSEL U V V U P R M L K J GPIO GPIO PU_RESET_n GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MSEL MSEL MSEL MSEL MSEL MSEL Settings : MSEL[:] = ctive serial (S)(x and x), no compression, no security, fast POR R R R R VP R R R R R R FPG_nONFIG FPG_nE ST_TI ST_TO R R JTG_FPG_TO JTG_FPG_TI FPG R R HSM_JTG_TO HSM_JTG_TI HSM VP VP XJ Jumper-.mm VP R K ST_TMS ST_TK R R efault JP Jumper Short HEER HSM_ISLE JTG_FPG_TMS JP HSM JTG hain Enable / isable HSM JTG hain Select Open Enable HSM JTG hain Short isable HSM JTG hain JTG_FPG_TMS JTG_FPG_TK LOW --> N to/from OM = ON and NO to/from OM = OFF HIGH --> N to/from OM = OFF and NO to/from OM = ON Logic = pin <--> pin (HSM ypass) U Logic = pin <--> pin (HSM Enable) HSM_JTG_EN HSM_JTG_TO IN NO NO IN TS R R OM N V+ N OM HSM_JTG_TMS HSM_JTG_TK ST_TI HSM_JTG_TI JTG_FPG_TO -> JTG_HSM_TI VP R K HSM_JTG_TMS R VP K VP VP.u V VP.u V U N N N N N N N N V T T T T LK ns opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. EPQ EPQ_S_T EPQ_S_T EPQ_S_T EPQ_S_T EPQ_LK EPQ_nSO yclone V GX Starter Kit R K R K Size ocument Number Rev FPG onfiguration and JTG ate: Friday, November, Sheet of

9 U- U- U- E E E E E F F F F G G G G G H H H H H H J J J J J J K K K K K K K L L L L L L L L L M M M M M M M NU_ N NU_ N NU_ N NU_ N N N N N N P P P P P P P P P N_ N_ GXFFN R R R R R R R R T T T T T U U U U U V V V V V W W W W W Y Y Y Y E E E E E F F F F F F F VP VP J J J J K K K K L L L L N N N N M M M M P P P R R R R T T T E V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V VT YLONE V GX Power GXFFN VP VP VP VP VP VP VP VP VP VP VP VP VP VP VP VP VP VPGM VPGM VPGM V_UX V_UX V_UX V_UX V_UX V_UX V_FPLL V_FPLL V_FPLL V_FPLL VREF_P_VIO U N R J L F F F F F F W E G G G J W Y VP VP VP VUX_V_FPLL VP R K R K R K VREF_P_VIO VREF_P_VIO VP VREF_LPR VP VREF_P_VIO R K VP VE_GXL Y U V U W Y E E F V W N R T W P K M N P R U VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO YLONE V GX Power VREFN VREFN VREFN VREFN VREFN GXFFN U- VE_GXL VE_GXL VE_GXL VE_GXL VE_GXL VE_GXL GXFFN.V ank IO YLONE V GX XVR Power.V.V VIO VIO VIO VIO VIO VIO VREFN VIO VIO VIO VIO VIO VIO VIO VIO VIO VIO VREFN VIO VIO VIO VIO VREFN VL_GXL VL_GXL VL_GXL VH_GXL VH_GXL VH_GXL VL_GXL opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. E F H J M L E F G H G K J N U L R T VH_GXL VP VREF_P_VIO VP VREF_P_VIO yclone V GX Starter Kit Size ocument Number Rev FPG Power and ate: Friday, November, Sheet of

10 VP u.v u.v u.v u.v.u.v.u.v u V.u V.u V.u V.u V.u V.u V n V n V n V n V n V VP n V n V n V n V n V n V n V n V n V n V.u V.u V.u V.u V.u V.u V VL_GXL VH_GXL.V.V VUX_V_FPLL.V u.v.u V.u V n V n V n V.u V.n V.u V.u V.u.V.u.V.u V n V VE_GXL.V VP for VIO.V u.v n V n V n V.u V.u V.u.V u V.u V.u V.u V VREF_LPR VP for VIO_VP.V.u V.u V.u V.u V u.v u V.u V.u V n V n V.u V.u V.n V.n V.n V.n V VREF_P_VIO VP for VIO_VP.V.u V.u V u.v u V.u V.u V n V n V.u V.u V.n V.n V.n V.n V VREF_P_VIO.u V.u V.u V.u V opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev FPG ecoupling ate: Wednesday, ugust, Sheet of

11 E, LPR Interface RLP_[..] RLP_K_p RLP_K_n RLP_KE[..] RLP_S_n[..] RLP_M[..] RLP_Q[..] RLP_QS_p[..] RLP_QS_n[..] RLP_K_p R.K R.K R R place close to R chip R RLP_K_n LPR SRM (M X X banks x die) RLP_ RLP_ RLP_ RLP_ RLP_ RLP_ RLP_ RLP_ RLP_ RLP_ RLP_K_p RLP_K_n RLP_KE RLP_KE RLP_S_n RLP_S_n RLP_M RLP_M RLP_M RLP_M RLP_ZQ RLP_ZQ W V U T T Y Y N L P E E F G G H H J K K L L M N U K K# KE KE S# S# M M M M ZQ N/ZQ N N N N N N N N N N N N N N N N N N N N N N N N N N N N N QS QS# QS QS# QS QS# QS QS# Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q NU NU NU NU NU NU NU NU NU NU NU NU NU NU NU NU MTLMLF-WT R P J K Y W W V U T T H H G F E E RLP_QS_p RLP_QS_n RLP_QS_p RLP_QS_n RLP_QS_p RLP_QS_n RLP_QS_p RLP_QS_n RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q RLP_Q VP VP u V.u.V VP VP Note: Place decoupling caps near LPR power pins u V.u V.u.V.u V N N L R M M R F J U V V V V V V V V V V V V V V V /N /N /N /N /N MTLMLF-WT.u V.u V VREF VREFQ V V V VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ Q Q Q Q Q Q Q Q Q Q Q Q n V P M U W G K R V V F J P U Y VP n V RLP_VREF VREF_LPR.u V VP R.K Note: Place resistors and apacitor near LPR VREF and VREFQ pins.u V.u V.u V.n V R.K.n V R.K R.K.n V VREF_LPR.n V E opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev LPR SRM ate: Wednesday, September, Sheet of

12 SRM SRM_[..] VP SRM_[..] SRM_E_n SRM_OE_n SRM_WE_n SRM_L_n SRM_U_n VP R.K SRM_E_n SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_E_n SRM_OE_n SRM_WE_n SRM_L_n SRM_U_n U ne noe nwe nl nu V V.u V.u V SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM_ SRM Kx Micro S ard S_T[..] S_M S_LK VP_S RN K R K S_T S_T S_T S_T S_M VP_S J VP R K R K L ohm, Q PMOS V S G.u V R K u V VP_S.u V.u V K K U K K U K K U S_T S_T S_M S_LK S_T S_T S_ T T M V LK T T Micro S ard Socket S_ R K Q MMT ESVUU ESVUU ESVUU opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev SRM and S ard ate: Tuesday, ugust, Sheet of

13 udio OE U_XK U_LK U_T U_LRK U_T VP L ohm, VP L ohm, u V V_U.u V.u V VP L VP_U ohm, u V.u V.u V LINE IN J PHONE JK NL R NR L U_LRK u V R.K,, I Interface I_S_P I_SL_P U_XK V_U U XTI/MLK XTO V V VP_U HPV V RLINEIN LLINEIN u V R.K p V R.K R.K p V MI IN J PHONE JK P NL R NR L I_S_P I_SL_P V_U R K R R R K V_U R K R K U_LK U_T U_LRK U_T U_LRK U_MUTE U_I_ST U_I_SLK U_S efault : I ddress x/ LKOUT MIIN LK PT MIIS PLRK RET RELR MUTE SIN SLK S EP_ P L ohm, RHPOUT LHPOUT LOUT ROUT VMI SSM R R u.v.u V u V u.v u R K p V LINE OUT J PHONE JK G NL R NR L U_MUTE U_S.V R K R K R K p V R K p V opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev udio OE ate: Friday, November, Sheet of

14 ,, HMI TX From MX I Interface I_S_P I_SL_P HMI_TX_[..] HMI_TX_LK HMI_TX_HS HMI_TX_VS HMI_TX_E HMI_TX_INT LK_MHz I_S_P I_SL_P R R VP_V R K R K HMI_S HMI_SL R. R HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_ HMI_TX_LK HMI_TX_E HMI_TX_HS HMI_TX_VS HMI_HP HMI_SPIF HMI_MLK HMI_IS HMI_IS HMI_IS HMI_IS HMI_SLK HMI_LRLK U LK E HSYN VSYN R_EXT HP SPIF MLK IS IS IS IS SLK LRLK P - TX+ TX- TX+ TX- TX+ TX- TX+ TX- INT S SL S SL E E_LK V_V V V V V PV GV V V V VSWZ EP_ TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n HMI_INT_R HMI_S HMI_SL S SL E_IO E_LK VP_V VP_V VP_PV VP_V R efault : I ddress x/x VP_V R.u V LK_MHz R X EN V OUT MHZ R VP_V R K FLS- E_LK TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n V R R R RlampP TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n TMS_TX_p TMS_TX_n RlampP E K SL K S K Rlamp Rlamp SL E HMI_HP HMI_HP S HMI TX + + K- K E SL S +V HP SHELL J R K R K VP_V VP L uh VP_V TP SPIF HMI_SPIF Pull-high to FPG bank I/O power u.v.u V.u V.u V.u V TP MLK HMI_MLK VP VP_V Note: Place apacitor near V V pins TP IS TP IS TP IS TP IS TP SLK TP LRLK TP HMI_IS HMI_IS HMI_IS HMI_IS HMI_SLK HMI_LRLK HMI_TX_INT R K HMI_TX_INT IR = Low : data to bus HMI_INT_R VP VP VP_V VP_V.u V R Schottky U V V IR SNVT R K R K HMI_INT_R.u V VP VP VP L uh L uh L uh u.v u.v u.v.u V VP_V Note: Place apacitor near V V pins.u V VP_PV Note: Place apacitor near V PV and GV pin.u V.u V.u V.u V VP_V Note: Place apacitor near V V_V opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev HMI TX ate: Tuesday, ugust, Sheet of

15 J HSM Transceiver HSM_GX_TX_p[..] HSM_GX_TX_n[..] HSM_GX_RX_p[..] HSM_GX_RX_n[..] HSM Interface HSM_TX_p[..] HSM_TX_n[..] HSM_RX_p[..] HSM_RX_n[..] HSM_[..] HSM lock HSM_LKOUT HSM_LKIN HSM_GX_TX_p HSM_GX_TX_n HSM_GX_TX_p HSM_GX_TX_n HSM_GX_TX_p HSM_GX_TX_n HSM_GX_TX_p HSM_GX_TX_n R R R R R R R R NET_HSM_GX_TX_p NET_HSM_GX_TX_n NET_HSM_GX_TX_p NET_HSM_GX_TX_n NET_HSM_GX_TX_p NET_HSM_GX_TX_n NET_HSM_GX_TX_p NET_HSM_GX_TX_n HSM_S HSM_JTG_TK HSM_JTG_TO HSM_LKOUT HSM_GX_RX_p HSM_GX_RX_n HSM_GX_RX_p HSM_GX_RX_n HSM_GX_RX_p HSM_GX_RX_n HSM_GX_RX_p HSM_GX_RX_n HSM_SL HSM_JTG_TMS HSM_JTG_TI HSM_LKIN HSM_LKOUT_p[..] HSM_LKOUT_n[..] V_HSM VP_HSM VP_HSM V_HSM,, HSM_LKIN_p[..] HSM_LKIN_n[..] HSM JTG HSM_JTG_TK HSM_JTG_TMS HSM_JTG_TI HSM_JTG_TO I Interface I_S I_SL I_S_P I_SL_P u V V V_HSM JP HEER I_S I_SL XJ Jumper-.mm u V.u V efault Jumper Open TP ummy Pin R R HSM_S HSM_SL u.v VP.u V VP_HSM TX_p TX_n HSM_ HSM_ HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_LKOUT_p HSM_LKOUT_n HSM_ HSM_ HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_LKIN_p HSM_LKIN_n RX_p RX_n I_S I_SL VP R.K R.K VP Q FVN Q FVN R R VP R.K R.K I_S_P I_SL_P HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_TX_p HSM_TX_n HSM_LKOUT_p HSM_LKOUT_n HSM PORT HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_RX_p HSM_RX_n HSM_LKIN_p HSM_LKIN_n HSM_PSNT_n HSM_PSNT_n VP R LEG HSM_PSNT_n V_HSM LE HSM_V opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev ustom HSM Interface ate: Friday, November, Sheet of R.K

16 _ONVST _SK _SO _SI nalog input interface nalog_in[..] _SO R VP R VP U V _ONVST _SK _SI K IR IR IR IR VT V OE EXP VP ex ONVST ex SK ex SO ex SI VP nalog_vref V V_ L ohm, R V_ V_ u V.u V.u V u V.u V VP VP U.u V.u V V OV V V nalog_in nalog_in R. R. _IN _IN H H ONV ex ONVST nalog_in R. _IN H SO ex SO nalog_in nalog_in R. R. _IN _IN H H LTUF SK ex SK nalog_in R. _IN H SI ex SI nalog_in nalog_in R. R. _IN _IN H H REFOMP _REFOMP TP REFOMP OM VREF _VREF R.K n V n V n V n V n V n V n V n V R..u V TP VREF u V.u V R.K _IS u V _IN _IN _IN n V R R _IS nalog_vref _IN n V _IN _IN n V _IN _IN n V opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev - LT ate: Friday, November, Sheet of

17 VP VP VP VP VP VP VP VP VP GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ TS TS TS TS TS TS TS TS TS GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ TS TS TS TS TS TS TS TS TS GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ TS TS TS TS TS TS TS TS TS GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ TS TS TS TS TS TS TS TS TS,,,, GPIO nalog input interface PU_RESET GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO[..] nalog_in[..] nalog_vref PU_RESET_n RN RN RN RN RN GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ lock_in lock_in V lock_out lock_out VP GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO JP OX Header XM RN RN RN RN GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ GPIO_ PU_RESET_n GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO R RN RN RN RN rduino_io rduino_io rduino_reset_n rduino_reset_n rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io JP HEER x rduino_io rduino_io V VP rduino_io R.K R.K JP nalog / igital Path select nalog / igital Path select Open No Select - Short Use rduino nalog input - Short Use rduino S or igital IO nalog_in rduino IO rduino_io nalog_in rduino IO rduino_io JP nalog / igital Path select nalog / igital Path select Open No Select - Short Use rduino nalog input - Short Use rduino SL or igital IO rduino_reset_n VP V V nalog_in nalog_in nalog_in nalog_in rduino IO rduino IO nalog_in nalog_in nalog / igital Select JP XJ S Jumper-.mm HEER JP XJ SL Jumper-.mm HEER JP TP nalog_in TP nalog_in efault Jumper - Short efault Jumper - Short opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. HEER JP HEER rduino IO rduino IO nalog_vref rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io rduino_io TP TP rduino Pin out Pin. JP Pin. JP JP yclone V GX Starter Kit Pin. Pin. JP Pin. SL S SK MISO MOSI SS Size ocument Number Rev GPIO and rduino Interface JP HEER JP HEER JP ate: Friday, November, Sheet of

18 , KEY PU_RESET SWITH KEY[..] PU_RESET_n SW[..] KEY TT SW KEY TT SW VP RN K KEY TT SW KEY TT SW u V u V VP u V R u V TN TN TN TN.u V U V SNU ETP Y Y Y Y Y Y KEY KEY KEY KEY KEY TT SW VP R K PU_RESET_n u V TN TN TN TN UTTON UTTON UTTON UTTON TT SW TT SW TT SW TT SW Reserved xmm tact switch VP RN SW SLIE SW SW SLIE SW SW SLIE SW SW SLIE SW K RN SW SW SW SW VP RN VP RN SW SLIE SW SW SLIE SW SW SLIE SW SW SLIE SW K RN SW SW SW SW SW SLIE SW SW SLIE SW K RN SW SW opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev Slide Switch and Tact switch ate: Friday, November, Sheet of

19 -Segment HEX_[..] HEX_[..],, -Segment (share GPIO[..]) LE GPIO[..] LER[..] LEG[..] VP SM L ohm, u V.u V V_HEX.u V LEG LEG LEG LEG RN LEG LEG LEG LEG LEG LEG LEG LEG RN HEX_ HEX_ HEX_ HEX_ RN HEX_ HEX_ HEX_ HEX_ E F G HEX a b c d e f g dp Segment isplay V_HEX LEG LEG LEG LEG RN LEG LEG LEG LEG LEG LEG LEG LEG GPIO GPIO GPIO GPIO GPIO GPIO GPIO V_HEX GPIO GPIO GPIO GPIO GPIO GPIO GPIO V_HEX V_HEX S ON S ON SW IP- R SW IP- R R HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ V_HEX HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ HEX_ V_HEX V_HEX RN HEX_ HEX_ HEX_ HEX_ RN HEX_ HEX_ HEX_ HEX_ RN HEX_ HEX_ HEX_ HEX_ RN HEX_ HEX_ HEX_ HEX_ RN HEX_ HEX_ HEX_ HEX_ HEX a b c d E e F f G g dp E F G E F G HEX d e f g dp Segment isplay Segment isplay V_HEX V_HEX R k LER LER LER LER RN LER LER LER LER LER LER LER LER LER LER a b RN LER LER c LER d LER e R LER LER LER f k LER g dp LER LER Segment isplay LER LER HEX V_HEX RN LER LER a LER b LER c opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev -SEGMENTand LEs ate: Friday, November, Sheet of

20 URT URT_RX URT_TX URT_RESET_n US to URT Self Powered and Internal OS V L ohm, TP URT_TS TP URT_RTS URT_TS URT_RTS VP R VIO_URT.u V R.u.V VP_URT.u V.u.V V_US_URT L ohm,.u.v.u V VIO_URT V_URT R.K R k RX_LE LER R TX_LE LEG R R k URT_RESET_n URT_RX URT_TX URT_TS URT_RTS URT_RXLE URT_TXLE URT_PW_EN U RESET TEST TX RX RTS# TS# TR# SR# # RI# US US US US US EP_ VIO V VOUT FTR USP USM N N N N N N OSI OSO U IO V N IO TPERLR FT_P FT_M V_URT.u V R J US -TYPE - + VUS M.u V opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev URT to US ate: Friday, November, Sheet of

21 J _V V VP u V R K Q O R K.u V SW POWER SW V u V VP_INTV u V V VP_INTV V R K R p V u V.u V.n V R K n V VP_INTV R U SVIN PHMOE MOE RUN TRK/SS ITH LKIN PVIN PVIN S INTV P EP_P.u.V PGOO VON OOST SW SW SW SW SW SW F RT LKOUT MSH- LTEUF#PF VP_INTV R K R K VP_PGOO.u V L uh + u.v Tantalum p V.V / Ramp Time Tsoft-start =. msec XJ Jumper-.mm R.K R K JP HEER R. R. p V R.K VP VP ohm, L ohm, L VL_GXL VE_GXL R.K R LE LE V.V V VP_INTV.u.V VP_INTV VP_INTV u V VP_INTV VP_PGOO R p V u V.u V.n V R.K p V R U SVIN PHMOE MOE RUN TRK/SS ITH LKIN PVIN PVIN S INTV P EP_P PGOO VON OOST SW SW SW SW SW SW F MSH- R K VP_PGOO.u V L uh + u.v Tantalum p V RT R LKOUT R.K K LTEUF#PF.V / Ramp Time Tsoft-start =. msec XJ Jumper-.mm R.K JP HEER R. R. p V R.K VP VP opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev Power - VP & VP ate: Friday, November, Sheet of

22 V u V R u V K INTV_ R K R K INTV_.n V U VIN OOST RUN SW INTV MOE/SYN VOUT ITH PGF ISET PGOO RT LTE#TRPF.u V INTV_ R K VP XJ Jumper-.mm L.uH V /. Ramp Time Tsoft-start =. msec u.v JP HEER R. V V V u V VP u V Ramp Time =. msec R K U IN OUT IN OUT OUT V_ONTROL OUT SET N LT- R.K.n V XJ Jumper-.mm u V JP HEER R. VP.V /. VP VUX_V_FPLL L ohm, VH_GXL L ohm, VP u V VP u V Ramp Time =. msec U IN OUT IN OUT OUT V_ONTROL OUT SET N LT- u.v XJ Jumper-.mm.u V JP HEER R. VP VP.V /. P R K.n V MP-- MH MH MH MH MH MH MH MH VP u V Ramp Time =. msec VP u V REG IS IN SHN EP_ LT- OUT J R K u.v XJ Jumper-.mm.u V JP HEER R. R K.V /. VP VP R K FI FI FI FI FI FI FI FI FI FI FI FI opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved. yclone V GX Starter Kit Size ocument Number Rev Power - V & VP & VP & VP ate: Wednesday, September, Sheet of

23 V L V_UT ohm, VP J US -TYPE R K + - VUS R M.u V X EN V OUT MHz luster TO FPG ST_TK ST_TMS ST_TI V_US.u V US_P US_M VP V_US.u V OS_ L ohm, V_UT V_US TSW LK_MHz R R.K R.K R R V_US R p V.u V VP R K.u V n V R.K US_RESETn EEPT EEPLK EEPS U VOUT RSTOUT# USP USM XTIN XTOUT RESET# EET EESK EES TEST VIO V V V FTL R# WR TXE# RXF# LQFP- SI/WU PWREN#.u V U U U U U U U U UR UWR UTXE URXF SI_WU PWRON URT_RESET_n V_UT.u V u.v VP R K R UR UWR UTXE OS_ URXF ST_TK ST_TI ST_TMS PWRON ST_TO TRGLK TRGSO TRGNSO TRGNST TRGOE US_RESETn TRGNE TRGTO TRGTMS ISP_TK ISP_TMS ISP_TI ISP_TO E F E F G G F H H H L L K L K L K L L K J L K L K L K L K L J J K J J K U E G VINT VINT VP IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO--/GLK IO-- IO--/GLK IO--/GLK IO-- IO--/GLK IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- EPMMN IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO--/EV_OE IO-- IO--/EV_LRn IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- IO-- TK IO-- TMS IO-- TI IO-- TO IO-- INT INT E J J G VIO VIO VIO VIO VIO VIO IO IO IO IO IO IO K J J H H H G F F G F E E.u V LK_MHz SI_WU EEPT EEPLK EEPS LK_MHz ULE U U U U U U U U.u V.u V VP.u V ST_TO FPG_nE R TRGOE E G E H H G R For HMI E lock (MHz) EPQ Interface URT LK_MHz EPQ_S_T EPQ_S_T EPQ_LK EPQ_nSO FPG_ONF_ONE FPG_nONFIG FPG_nE URT_RESET_n PROG RUN JTG/S mode SW SLIE SW VP FPG_nE TRGOE R.K The direction of SW should be same as E board EPQ_S_T EPQ_S_T EPQ_LK EPQ_nSO FPG_ONF_ONE FPG_nONFIG FPG_nE lose to EPQ R K R R. R R lose to FPG R R R TRGSO TRGNST TRGLK TRGNSO TRGTO TRGTMS TRGNE VP VP R R R K K K ISP_TK ISP_TO ISP_TMS ISP_TI PL ISP J Header x VP opyright (c) by Terasic Technologies Inc. Taiwan. ll rights reserved..u V ULE ULE yclone V GX Starter Kit LEG Size ocument Number Rev US laster ate: Friday, November, Sheet of