June 8 th Riga, Latvia

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1 Laurent Fesquet June 8 th Riga, Latvia

2 Outline Asynchronous logic Non uniform sampling Asynchronous convolution product Asynchronous FIR filter Conclusion and prospects

3 Les travaux de thèse

4 Why asynchronous logic?! Asynchronous systems are only driven by the signal information No global clock No activity when no data to compute Low power consumption i(t) Analog A-ADC i k dti k Digital Asynchronous Digital Signal Processing o k dto k

5 Timing assumption Asynchronous Logic Basics request Sender Data Receiver acknowledge Handshake communication protocol 5 styles of asynchronous circuits: Delay insensitive circuits (DI). Quasi Delay insensitive circuits (QDI). Speed independent circuit (SI). Micropipeline. Huffman. Robustness & complexity

6 Asynchronous Logic Micropipline Asynchronous Micropipeline circuits : Timing assumption + Communication between different stages is based on Handshake model. Locally: worst case approach. Need a local timing assumption. Request req + Robustness & complexity Data Acknowledge Reg Reg Ctrl Log. Log. Ctrl ack Reg Ctrl

7 Asynchronous Logic Muller gate C-Element or Muller gate: X Y Symbol C Z Truth table X Y Z Z Z X Y Z Z = XY + Z(X+Y)

8 Outline Asynchronous logic Non uniform sampling Asynchronous convolution product Asynchronous FIR filter Conclusion and prospects

9 Les travaux de thèse

10 Magnitude Magnitude Non-uniform sampling Uniform sampling Non uniform sampling i k i(t) i k-1 i k i(t) Dual q t t T sample dti k Respect the Shannon theorem Instants exactly known Information: T sample, { i k } In an ADC: Amplitude quantization Many useless samples Level-crossing sampling Amplitudes exactly known Information: quantum, { dti k } In an A-ADC: Time quantization Only useful samples

11 Req. Acq. Acq. Req. Non-uniform sampling A-ADC Converter A-ADC: Asynchronous design for Non uniform sampling DAC V ref (t) i(t) Difference quantificator Req. Acq. up dwn Up/down counter i k +q/2 dti k -q/2 Timer If (i(t) Vref(t)) > q/2 up = 1 If (i(t) Vref(t)) < -q/2 dwn = 1 Else up = dwn = 0 dti k t

12 Outline Asynchronous logic Non uniform sampling Asynchronous convolution product Asynchronous FIR filter Conclusion and prospects

14 Convolution product synchronous approach o ( n ) = N-1 k = 0 h ( k ) i ( n - k ) i h n-n+1 n-3 n-2 n-1 n 3 2 The instants are synchronized Classical digital convolution product incompatible with non uniformly sampled signals N Find a digital equation using the information contained in the time intervals

15 Convolution product asynchronous approach Asynchronous convolution product: + + o ( t ) = h ( t ) i ( t - t ) d t o n - - n n ) Asynchronous convolution algorithm: o n = min( dti n - k, dth dto n = dti n, if min = dti n - k if min = dth j if min = dth = dti j n - k j ) i n - k h j ( t ) = h ˆ n ( t ) i ˆ ( t - t d t, then dth j = dth j - dti n - k ; k = k + 1, the n dti n - k = dti n - k - dth j = j + 1, then k = k + 1 ; j = j + 1. j ;

16 Convolution product asynchronous approach input n-5 n-4 n-4 n-3 n-2 n-2 n-2 n-1 n n Impulse response Break output n

17 Outline Asynchronous logic Non uniform sampling Asynchronous convolution product Asynchronous FIR filter Conclusion and prospects

19 Asynchronous F.I.R filter The architecture (i n ; dti n ) Architecture derived from the asynchronous convolution: dti n-k k j dth j DL ROM h j i n-k System triggered on signal events Test dt min MULT2 MULT1 ACC BUFF (o n ; dti n )

20 Mux Asynchronous F.I.R filter The conv. bloc Architecture of the convolution product boc: i n-k h j Mux reset Buff-En MULT ACC BUFF dt min Req_i n-k Req_h j Req_dt min C delay C Req_mult delay C Req_acc delay C Req_buff Ack_acc Ack_buff Ack_mult

21 Mux Asynchronous F.I.R filter The test bloc Architecture of the Test bloc: dth j dti n-k Mux i Update Min Add index j Req_dti n-k Req_dth j Ack_updt Req_updt Req_min Update_ctrl Min_ctrl Add_ctrl Ack_min Ack_add Req_add Ack_res

22 Outline Asynchronous logic Non uniform sampling Asynchronous convolution product Asynchronous FIR filter Conclusion and prospects

24 Conclusion and prospect Conclusion Asynchronous logic is a data driven logic suitable for nonuniform sampling implementation Asynchronous filtering is a more complex algorithm computed on a shorter set of samples We expect to gain at least one or two order of magnitudes This architecture is being implemented on an FPGA board for power measurement Prospects Implementation with non uniformly sampled filter response An automatic asynchronous filter generator tool should be developed based on non-uniform sampling

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003

Timing Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2