Chapter 18 FUNDAMENTAL MODE SEQUENTIAL CIRCUITS

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1 Chapter 18 FUNDAMENTAL MODE SEQUENTIAL CIRCUITS

2 Lesson 3 Races 2

3 Race condition Cycles of races Critical races Outline 3

4 Excitation Table for Y O = X. Q2 +Q1; Q1 =D and Q2 = Q n+1 = J. Q n + K. Q n State Excitation Inputs Y O (Q 1,Q 2) [D, (J, K)] X=0 [D, (J, K)] X=1 X=0 X =1 (0, 0) 0, (0, 0) 1, (0,1) 0 0 (0, 1) 0, (0, 0) 1, (0,1) 1 0 (1, 0) 0, (1, 0) 1, (1,1) 1 1 (1, 1) 0, (1, 0) 1, (1,1) 1 1 Y is present output state after the X inputs but before transition 4

5 Excitation-cum-Transition Table for Y = X. x q2 + x q1 ; x q1 =D and x q2 = x q n+1 = J. x q n + K. State x q n Transition Outputs Y (x q0, x q1) [x q0, x q1 ] X=0 [x q0, x q1 ] X=1 X=0 X =1 (0, 0) 0, 0 1, (0, 1) 0, 1 1, (1, 0) 0, 1 1, (1, 1) 0, 1 0,

6 Two-bit changes (in Qs) at the memory or delay sections (x, x ) and (x, x ) the present q0 q1 q0 q1 and past states are (0, 1) and (1, 0), respectively, in Column 3 row 2 (x, x ) and (x, x ) the present q0 q1 q0 q1 and past states are (1, 1) and (0, 0), respectively in Column 3 row 4 6

7 Number of Races during the flow There are two races at two entries of next state outputs for the present states in the transitions given Two races occur due to two different instances of the feedback cycle for next state variables 7

8 Number of Races during the flow Two instances don t occur simultaneously, when two bits are expected to change at the delay section during a transition when a state changes, due to small variations in propagation delays of two latches 8

9 Race 1 in State diagram row 2 for transitions through intermediate states to stable state S 0 S 1 S 2 1/1 1/0 S 3 S 1 races to S 3 and then S 3 transition is to S 0 and will reach S 2. If 0, 1 changes to 0, 0 first, then S 0 and the S 2 is directly obtained in next cycle When 0, 1 becomes 1, 0, it does not happen simultaneously. Assume that 0, 1 first changes to 1, 1 and then to 1, 0 9

10 Race 1 in given example of State Table Therefore, (0, 1) present state can change to (1,1) for some period [S1 can temporarily be S3 in place of S2, therefore, the S0 is obtained in a cycle. From intermediate S0, the transition will be to S0 and from S0 to S2. When (1,1) changes to (1, 0) the transition will be to S2. In next feedback cycle this happens. 10

11 Race 2 Case 1in State diagram row 4 for transitions through intermediate states to stable state S 2 S 0 1/1 1/1 S 3 S3 races to S2 and then S 2 transition may be again to S 3 and will reach S 0 in indefinite number of cycles. 1/1 When 1, 1 becomes 0, 0, it does not happen simultaneously. Assume that 1, 1 first changes to 1, 0 and then to 0, 0 11

12 Race 2 case 2 in State diagram row 4 for transitions through intermediate states to stable state 1/0 S S 1/ /1 S 2 S 3 S3 races to S1 and then to S 2 and transition will be again to S 3 and will reach S 0 in indefinite number of cycles. 1/1 When 1, 1 becomes 0, 0, it does not happen simultaneously. Assume that 1, 1 first changes to 0, 1 and then to 0, 0 12

13 Race 2 in given example of State Table Therefore, (1, 1) present state can change to (0,1) for some period [S3 can temporarily be S1, from S1 it will change to S2, from S2 to S3, therefore, the S0 is obtained in indefinite number of cycles. 13

14 Race condition A race is said to occur if between next set of states x q and present states x q, there are two or more bits change (ttwo or more latches undergoes change in Q output) at the memory or delay section, Race condition arises due to variable number of delays of different latches, which lead to intermediate states. 14

15 Race condition Cycles of races Critical races Outline 15

16 Non-Critical Race (Deterministic Number of Cycles of race) The state momentarily change can lead to a stable state with one or more additional feedback-cycles and the state eventually turns out to be the same as would have been expected had there been no race. Race condition is not permanent and the race returns to normal after calculatedly number of races. Asynchronous circuit is said to be deterministic when a non-critical race condition exists 16

17 Example Race 1 case (1) The present state (0, 1) if momentarily changes to (0, 0); the monetarily state will be S0. The S0 for X =1 gives the output (1,0) again and gives the state S2 in next feedback cycle 17

18 Example Race 1 case (2) The present state (0, 1) if momentarily changes to (1, 1), the monetarily state will be S3. The S3 for X =1 gives the output (0, 0) and sate S0 again in next feedback-cycle. S0 gives the state S2 in next feedback cycle 18

19 Non-critical Race Therefore after two state transitions, the same stable state is obtained in case (2) and after one more state transitions in case (1) as would have been had there been no race to case (1) or (2) above. The race is therefore not critical in its effect on the behavior, except additional delay. Flow table shall remain unaltered. 19

20 Outline Race condition Cycles of races Critical races 20

21 Critical Race (Indeterminate Number of Cycles of Races) The state momentarily changed can lead to a different stable state with any known number one or more additional feedback-cycles and the state will most often turn out never to be the same as would have been expected had there been no race 21

22 Critical Race (Indeterminate Number of Cycles of Races) Race is called critical race. Race condition is indefinite and the race returns to normal after indefinite number of races because when two propagation delays exactly match is never known or become greater than the other. Asynchronous circuit is probabilistic, not deterministic when a critical race condition exists. 22

23 Example Race 2 Case 1 S3 races to S2 and then S 2 transition may be again to S 3 and will reach S 0 in a number of cycles. The present state (1, 1) if momentarily changes to (1, 0), the monetarily state will be S2. The S2 for X =1 gives the state (1, 1) S3 again in next feedback cycle 23

24 Race 2 Case 1 When 1, 1 becomes 0, 0, it does not happen simultaneously. Assume that 1, 1 first changes to 1, 0 and then to 0, 0. S2 will again return back to S3. When the transition will be to S0, one never knows. It can only be when the propagation delay match. 24

25 Race 2 Case 2 The present state (1, 1) if momentarily changes to (0, 1); the monetarily state will be S1. The S1 for X =1 gives the stable state S3 back after two feedback cycles. When the transition will be to S0, one never knows. It can only be when the propagation delays match. 25

26 Critical race There may be the intermediate race through such that the path to return don t exists. Flow table is not deterministic, is probabilistic only 26

27 Summary

28 Race Race occurs due to different latches within memory section can have different propagation delays, the feedback inputs for next cycle transition is different than given by state table. Another state races though due to shorter delay in one latch. 28

29 Non Critical race: The state momentarily changed can lead to a stable state with one or more additional feedback-cycles and the state eventually turns out to be the same as would have been expected had there been no race. Race condition is not permanent and the race returns to normal after calculatedly number of races.

30 Critical race: The state momentarily change leads to a different stable state with any known number one or more additional feedback-cycles and the state will most often turn out never to be the same as would have been expected had there been no race. Such a race is called critical race. Race condition is indefinite and the race returns to normal after indefinite number of races

31 End of Lesson 3 Races

32 THANK YOU 32

Synchronous Sequential Circuit

Synchronous Sequential Circuit The change of internal state occurs in response to the synchronized clock pulses. Data are read during the clock pulse (e.g. rising-edge triggered) It is supposed to wait