HM534251B Series word 4-bit Multiport CMOS Video RAM

Transcription

1 word 4-bit Multiport CMOS Video RAM Description The HM534251B is a 1-Mbit multiport video RAM equipped with a 256-kword 4-bit dynamic RAM and a 512-word 4-bit SAM (serial access memory). Its RAM and SAM operate independently and asynchronously. It can transfer data between RAM and SAM and has write mask function. Features Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 256-kword 4-bit SAM: 512-word 4-bit Access time RAM: 60 ns/70 ns/80 ns/100 ns max SAM: 20 ns/22 ns/25 ns/25 ns max Cycle time RAM: 125 ns/135 ns/150 ns/180 ns min SAM: 25 ns/25 ns/30 ns/30 ns min Low power Active RAM: 413 mw max SAM: 275 mw max Standby 38.5 mw max High-speed page mode capability Mask write mode capability Bidirectional data transfer cycle between RAM and SAM capability Real time read transfer cycle capability 3 variations of refresh (8 ms/512 cycles) -only refresh -before- refresh Hidden refresh TTL compatible

2 Ordering Information Type No. Access Time Package HM534251BJ-6 60 ns 400-mil 28-pin plastic SOJ (CP-28D) HM534251BJ-7 HM534251BJ-8 HM534251BJ ns 80 ns 100 ns HM534251BZ-6 HM534251BZ-7 HM534251BZ-8 HM534251BZ ns 70 ns 80 ns 100 ns 400-mil 28-pin plastic ZIP (ZP-28) Pin Arrangement HM534251BJ Series HM534251BZ Series SC S0 S1 0 1 NC A8 A6 A5 A4 V CC (Top View) VSS S3 S2 SE 3 2 NC NC A0 A1 A2 A3 A7 2 SE S3 SC S1 0 A6 A4 A7 A2 A (Bottom View) NC 3 S2 VSS S0 1 NC A8 A5 VCC A3 A1 NC 2

3 Pin Description Pin Name A0 A8 0 3 S0 S3 SC SE V CC V SS NC Function inputs RAM port data inputs/outputs SAM port data inputs/outputs Row address strobe Column address strobe Write enable Data transfer/output enable Serial clock SAM port enable Power supply Ground No connection 3

4 Block Diagram A0 A8 Column Buffer Row Buffer Refresh Counter Row Decoder Serial Counter Column Decoder Sense Amplifier & Bus Input Data Control Serial Output Buffer Serial Input Buffer S0 S3 Input Buffer Output Buffer Timing Generator 0 3 SC SE Memory Array Data Register SAM Bus SAM Column Decoder Mask Register 4

5 Pin Functions (input pin): is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of. The input level of these signals determine the operation cycle of the HM534251B. Table 1. Operation Cycles of the HM534251B Input Level At The Falling Edge Of SE Operation Mode L X X X CBR refresh H L L L Write transfer H L L H Pseudo transfer H L H X Read transfer H H L X Read/mask write H H H X Read/write Note: X : Don t care. (input pin): Column address is fetched into chip at the falling edge of. controls output impedance of in RAM. A0 A8 (input pins): Row address is determined by A0 A8 level at the falling edge of. Column address is determined by A0-A8 level at the falling edge of. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. (input pin): pin has two functions at the falling edge of and after. When is low at the falling edge of, the HM534251B turns to mask write mode. According to the level at the time, write on each can be masked. ( level at the falling edge of is don t care in read cycle.) When is high at the falling edge of, a normal write cycle is executed. After that, switches read/write cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by level at the falling edge of. When is low, data is transferred from SAM to RAM (data is written into RAM), and when is high, data is transferred from RAM to SAM (data is read from RAM). 0 3 (input/output pins): pins function as mask data at the falling edge of (in mask write mode). Data is written only to high pins. Data on low pins are masked and internal data are retained. After that, they function as input/output pins as those of a standard DRAM. (input pin): pin functions as DT (data transfer) pin at the falling edge of and as OE (output enable) pin after that. When DT is low at the falling edge of, this cycle becomes a transfer cycle. When DT is high at the falling edge of, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an S pin synchronously with the rising edge of SC. In a serial write cycle, data on an S pin at the rising edge of SC is fetched into the SAM data register. 5

6 SE (input pin): SE pin activates SAM. When SE is high, S is in the high impedance state in serial read cycle and data on S is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because internal pointer is incremented at the rising edge of SC. S0-S3 (input/output pins): Ss are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, S outputs data. When it was a pseudo transfer cycle or write transfer cycle, S inputs data. Operation of HM534251B RAM Read Cycle ( high and high at the falling edge of ) Row address is entered at the falling edge and column address at the falling edge to the device as in standard DRAM. Then, when is high and is low while is low, the selected address data outputs through pin. At the falling edge of, and become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. access time (t AA ) and to column address delay time (t RAD ) specifications are added to enable high-speed page mode. RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) ( high and high at the falling edge of ) Normal Mode Write Cycle ( high at the falling edge of ) When and are set low after driving low, a write cycle is executed and data is written in the selected addresses. When all 4 s are written, should be high at the falling edge of to distinguish normal mode from mask write mode. If is set low before the falling edge, this cycle becomes an early write cycle and becomes in high impedance. Data is entered at the falling edge. If is set low after the falling edge, this cycle becomes a delalyed write cycle. Data is input at the falling. does not become high impedance in this cycle, so data should be entered with OE in high. If is set low after t CWD (min) and t AWD (min) after the falling edge, this cycle becomes a read-modifywrite cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid contention, data should be input after reading data and driving OE high. Mask Write Mode ( low at the falling edge of ) If is set low at the falling edge of, the cycle becomes a mask write mode cycle which writes only to selected. Whether or not an is written depends on level (mask data) at the falling edge of. Then the data is written in high pins and masked in low ones and internal data is retained. This mask data is effective during the cycle. So, in high-speed page mode cycle, the mask data is retained during the page access. 6

7 High-Speed Page Mode Cycle ( high and high at the falling edge of ) HM534251B Series High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling while is low. Its cycle time is one third of the random read/write cycle. Note that address access time (t AA ), to column address delay time (t RAD ), and access time from precharge (t ACP ) are added. In one cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within t P max (100 µs). Transfer Operation The HM534251B provides the read transfer cycle, pseudo transfer cycle and write transfer cycle as data transfer cycles. These transfer cycles are set by driving high and low at the falling edge of. They have following functions: (1) Transfer data between row address and SAM data register (except for pseudo transfer cycle) Read transfer cycle:ram to SAM Write transfer cycle:sam to RAM (2) Determine S state Read transfer cycle:s output Pseudo transfer cycle and write transfer cycle: S input (3) Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or pseudo transfer cycle after power on, and determined for each transfer cycle. Read Transfer Cycle ( high, low and high at the falling edge of ) This cycle becomes read transfer cycle by driving low and high at the falling edge of. The row address data (512 4-bit) determined by this cycle is transferred to SAM data register synchronously at the rising edge of. After the rising edge of, the new address data outputs from SAM start address determined by column address. In read transfer cycle, must be risen to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing t SDD (min) specified between the last SAM access before transfer and rising edge and t SDH (min) specified between the first SAM access and rising edge must be satisfied. (See figure 1.). 7

8 Xi Yj L t SDD t SDH SC S Yj Yj + 1 SAM Data before Transfer SAM Data after Transfer Figure 1. Real Time Read Transfer When read transfer cycle is executed, S becomes output state by first SAM access. Input must be set high impedance before t SZS (min) of the first SAM access to avoid data contention. Pseudo Transfer Cycle ( high, low, low and SE high at the falling edge of ) Pseudo transfer cycle switches S to input state and set SAM start address without data transfer to RAM. This cycle starts when is high, low, low and SE high at the falling edge of. Data should be input to S later than t SID (min) after becomes low to avoid data contention. SAM access becomes enabled after t SRD (min) after becomes high. In this cycle, SAM access is inhibited during low, therefore, SC must not be risen. Write Transfer Cycle ( high, low, low and SE low at the falling edge of ) Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the falling edge of. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after t SRD (min) after becomes high. SAM access is inhibited during low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle can be written to other address of RAM by write transfer cycle. However, the address to write data must be the same MSB of row address (AX8) as that of the read transfer cycle. 8

9 SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is synchronized with SC rising, and SAM data is output from S. When SE is set high, S becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Serial Write Cycle If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode. In this cycle, S data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is high, S data isn t fetched into data register. Internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) R AS -only refresh cycle, (2) -before- (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) -Only Refresh Cycle: -only refresh cycle is executed by activating only R AS cycle with fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from data transfer cycle, must be high at the falling edge of. (2) CBR Refresh Cycle: CBR refresh cycle is set by activating before. In this cycle, refresh address need not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because circuits don t operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating when and keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift register and selector), organized as fully static circuitry, require no refresh. 9

10 Absolute Maximum Ratings Parameter Symbol Value Unit Terminal voltage *1 V T 1.0 to +7.0 V Power supply voltage *1 V CC 0.5 to +7.0 V Short circuit output current Iout 50 ma Power dissipation P T 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg 55 to +125 C Note: 1. Relative to V SS. Recommended DC Operating Conditions (Ta = 0 to +70 C) Parameter Symbol Min Typ Max Unit Supply voltage *1 V CC V Input high voltage *1 V IH V Input low voltage *1 V IL 0.5 *2 0.8 V Notes: 1. All voltages referred to V SS V for pulse width 10 ns. DC Characteristics (Ta = 0 to +70 C, V CC = 5 V ± 10%, V SS = 0 V) HM534251B Test Conditions Parameter Symbol Min Max Min Max Min Max Min Max Unit RAM Port SAM Port Operating current I CC ma, cycling t RC = min SC = V IL, SE = V IH I CC ma SE = V IL, SC cycling t SCC = min Standby current I CC ma, = V IH SC = V IL, SE = V IH I CC ma SE = V IL, SC cycling t SCC = min 10

11 DC Characteristics (Ta = 0 to +70 C, V CC = 5 V ± 10%, V SS = 0 V) (cont) HM534251B Series HM534251B Test Conditions Parameter Symbol Min Max Min Max Min Max Min Max Unit RAM Port SAM Port -only refresh current Page mode current -before- refresh current Data transfer current Input leakage current Output leakage current Output high voltage I CC ma cycling = V IH t RC = min SC = V IL, SE = V IH I CC ma SE = V IL, SC cycling t SCC = min I CC ma cycling = V IL t PC = min SC = V IL, SE = V IH I CC ma SE = V IL, SC cycling t SCC = min I CC ma cycling t RC = min SC = V IL, SE = V IH I CC ma SE = V IL, SC cycling t SCC = min I CC ma, cycling t RC = min SC = V IL, SE = V IH I CC ma SE = V IL, SC cycling t SCC = min I LI µa I LO µa V OH V I OH = 2 ma Output low voltage V OL V I OL = 4.2 ma Notes: 1. I CC depends on output loading condition when the device is selected. I CC max is specified at the output open condition. 2. can be changed once while is low and is high. 11

12 Capacitance (Ta = 25 C, V CC = 5 V, f = 1 MHz, Bias: Clock, = V CC, address = V SS ) Parameter Symbol Min Typ Max Unit C I1 5 pf Clock C I2 5 pf, S C 7 pf *1, *16 AC Characteristics (Ta = 0 to +70 C, V CC = 5 V ±10%, V SS = 0 V) Test Conditions Input rise and fall time: 5 ns Input pulse levels : V SS to 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: See figures I OH= 2 ma + 5 V I OH= 2 ma + 5 V I OL = 4.2 ma I OL = 4.2 ma I / O * pf SI / O * 1 50 pf Output Load (A) Output Load (B) Note: 1. Including scope & jig. 12

13 Common Parameter HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC ns precharge time t RP ns pulse width t ns pulse width t ns Row address setup time t ASR ns Row address hold time t RAH ns Column address setup time t ASC ns Column address hold time t CAH ns to delay time t RCD ns 2 hold time referred to t RSH ns hold time referred to t CSH ns to precharge time t CRP ns Transition time (rise to fall) t T ns 3 Refresh period t REF ms DT to setup time t DTS ns DT to hold time t DTH ns Data-in to delay time t DZC ns 4 Data-in to OE delay time t DZO ns 4 Output buffer turn-off delay referred to Output buffer turn-off delay referred to OE t OFF ns 5 t OFF ns 5 13

14 Read Cycle (RAM), Page Mode Read Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Access time from t RAC ns 6, 7 Access time from t CAC ns 7, 8 Access time from OE t OAC ns 7 access time t AA ns 7, 9 Read command setup time t RCS ns Read command hold time t RCH ns 10 Read command hold time referred to to column address delay time Column address to lead time Column address to lead time t RRH ns 10 t RAD ns 2 t RAL ns t CAL ns Page mode cycle time t PC ns precharge time t CP ns Access time from precharge Page mode pulse width t ACP ns t P ns 14

15 Write Cycle (RAM), Page Mode Write Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write command setup time t WCS ns 11 Write command hold time t WCH ns Write command pulse width Write command to lead time Write command to lead time t WP ns t RWL ns t CWL ns Data-in setup time t DS ns 12 Data-in hold time t DH ns 12 to setup time t WS ns to hold time t WH ns Mask data to setup time Mask data to hold time OE hold time referred to t MS ns t MH ns t OEH ns Page mode cycle time t PC ns precharge time t CP ns to data-in delay time t CDD ns 13 Page mode pulse width t P ns 15

16 Read-Modify-Write Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC ns pulse width (read-modify-write cycle) t RWS ns to delay time t CWD ns 14 Column address to delay time t AWD ns 14 OE to data-in delay time t ODD ns 12 Access time from t RAC ns 6, 7 Access time form t CAC ns 7, 8 Access time from OE t OAC ns 7 access time t AA ns 7, 9 to column address delay time Read command setup time Write command to lead time Write command to lead time Write command pulse width t RAD ns t RCS ns t RWL ns t CWL ns t WP ns Data-in setup time t DS ns 12 Data-in hold time t DH ns 12 OE hold time referred to t OEH ns 16

17 Refresh Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes setup time (-before- refresh) t CSR ns hold time (-before- refresh) precharge to hold time t CHR ns t RPC ns 17

18 Read Transfer Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes DT hold time referred to t RDH ns DT hold time referred to DT hold time referred to column address t CDH ns t ADH ns DT precharge time t DTP ns DT to delay time t DRD ns SC to setup time t SRS ns 1st SC to hold time t SRH ns 1st SC to hold time t SCH ns 1st SC to column address hold time t SAH ns Last SC to DT delay time t SDD ns 1st SC to DT hold time t SDH ns Serial data-in to 1st SC delay time t SZS ns Serial clock cycle time t SCC ns SC pulse width t SC ns SC precharge time t SCP ns SC access time t SCA ns 15 Serial data-out hold time t SOH ns Serial data-in setup time t SIS ns Serial data-in hold time t SIH ns to column address delay time Column address to lead time DT high hold time from precharge t RAD ns t RAL ns t DTHH ns 18

19 Pseudo Transfer Cycle, Write Transfer Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes SE setup time referred to t ES ns SE hold time referred to SC setup time referred to t EH ns t SRS ns to SC delay time t SRD ns Serial output buffer turn-off time referenced to to serial data-in delay time t SRZ ns t SID ns Serial clock cycle time t SCC ns SC pulse width t SC ns SC precharge time t SCP ns SC access time t SCA ns 15 SE access time t SEA ns 15 Serial data-out hold time t SOH ns Serial write enable setup time t SWS ns Serial data-in setup time t SIS ns Serial data-in hold time t SIH ns 19

20 Serial Read Cycle, Serial Write Cycle HM534251B Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Serial clock cycle time t SCC ns SC pulse width t SC ns SC precharge width t SCP ns Access time from SC t SCA ns 15 Access time from SE t SEA ns 15 Serial data-out hold time t SOH ns Serial output buffer turn-off time referred to SE t SEZ ns 5 Serial data-in setup time t SIS ns Serial data-in hold time t SIH ns Serial write enable setup time Serial write enable hold time Serial write disable setup time t SWS ns t SWH ns t SWIS ns Serial write disable hold t SWIH ns time Notes: 1. AC measurements assume t T = 5 ns. 2. When t RCD > t RCD (max) or t RAD > t RAD (max), access time is specified by t CAC or t AA. 3. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition time t T is measured between V IH and V IL. 4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either t DZC (min) or t DZO (min) must be satisfied. 5. t OFF1 (max), t OFF2 (max) and t SEZ (max) are defined as the time at which the output acheives the open circuit condition (V OH 100 mv, V OL +100 mv). 6. Assume that t RCD t RCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pf. 8. When t RCD t RCD (max) and t RAD t RAD (max), access time is specified by t CAC. 9. When t RCD t RCD (max) and t RAD t RAD (max), access time is specified by t AA. 10. If either t RCH of t RRH is satisfied, operation is guaranteed. 11. When t WCS t WCS (min), the cycle is an early write cycle, and pins remain in an open circuit (high impedance) condition. 12. These parameters are specified by the later falling edge of or. 13. Either t CDD (min) or t ODD (min) must be satisfied because output buffer must be turned off by or OE prior to applying data to the device when output buffer is on. 20

21 14. When t AWD t AWD (min) and t CWD t CWD (min) in read-modify-write cycle, the data of the selected address outputs to an pin and input data is written into the selected address. t ODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. 15. Measured with a load circuit equivalent to 2 TTL loads and 50 pf. 16. After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17. XXX: H or L (H: V IH (min) V IN V IH (max), L: V IL (min) V IN V IL (max)) ///////: Invalid Dout Timing Waveforms * 17 Read Cycle t RC t t RP t RCD t CSH t RSH t t CRP t RAD t ASR t RAH Row t ASC Column t CAH t RAL t CAL t RCS t RRH t RCH (Input) t DZC t DZO t CAC t AA t RAC t OAC t OFF1 Valid Dout t OFF2 t CDD t DTS t DTH 21

22 Early Write Cycle t RC t t RP tcsh t CRP t ASR t RAH t RCD t ASC t CAH t RSH t Row Column t WS t WH twcs t WCH (Input) *1 t MS t MH tds t DH Mask Data Valid Din t DTS t DTH High-Z Note: 1. This cycle becomes a normal mode write cycle when is high and a mask write cycle when is low. Delayed Write Cycle t RC t t RP t RCD t ASR t RAH t ASC t CAH t CSH t RSH t t CRP Row Columun t WS t WH t RWL t CWL *1 t WP (Input) t MS t MH t DS t DZC t DH Mask Data Valid Din t OFF2 t DTS t DTH t t OEH ODD Note: 1. This cycle becomes a normal mode write cycle when is high and a mask write cycle when is low. 22

23 Read-Modify-Write Cycle t RWC t RWS t RP t RAD t RCD t ASR trah tasc t CAH t CRP (Input) Row Mask Data t DZO t DTS t DTH Columun t WS t WH trcs *1 tcac t AA t RAC t MS t MH tdzc t OAC t AWD t CWD Valid Dout t OFF2 t ODD t DS t DH Valid Din t RWL t CWL t WP t OEH Note: 1. This cycle becomes a normal mode write cycle when is high and a mask write cycle when is low. Page Mode Read Cycle t RC t P t RP (Input) t ASR tdts t RCD t CSH t RAD t RAH t ASC t t CAL t CAH t PC t CP t t CP t CAL t ASC t CAH t ASC t RAL Row Columun Columun Columun t RCS t t RCS t RCS RCH t RCH t DZC t DZO t DTH t RAC t OFF1 t AA t CAC Valid Dout t CDD t OAC t OFF2 t AA toff1 t ACP t CAC Valid Dout t DZC t CDD t DZC t OAC t OFF2 t RSH t t CAL t CAH t AA t ACP t CAC t OAC t RRH t RCH Valid Dout t CRP t OFF1 t CDD 23

24 Page Mode Write Cycle (Early Write) t P t RC t RP t CSH t PC t RCD t t t t CP RSH CP t t t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Row Column Column Column t WS t WH t WCS t WCH t WCS twch t WCS t WCH t CRP (Input) Note: t MS *1 Mask Data t DTS t MH t DS t DTH t DH t DS t DH High-Z t DS t DH Valid Din Valid Din Valid Din 1. This cycle becomes a normal mode write cycle when is high and a mask write cycle when is low. Page Mode Write Cycle (Delayed Write) t RC t P t CSH t RCD t t PC t CP t t CP t RSH t t ASR t RAH t ASC t CAH t ASC t CAH t ASC Row Column Column Column t CWL t CWL t WS t WH t WP t WP t MS *1 t MH t DS t DH t DS t DH t DS t CAH t RWL t DH t WP t RP t CWL t CRP (Input) t DTS Mask Data Valid Din Valid Din Valid Din t OEH Note: 1. This cycle becomes a normal mode write cycle when is high and a mask write cycle when is low. 24

25 -Only Refresh Cycle t RC t t RP t CRP t RPC t ASR t RAH Row t OFF1 t CDD (Input) t OFF2 t ODD t DTS t DTH -Before- Refresh Cycle t RP t t RC t RP t RPC t CP t CSR t CHR t RPC tcsr Inhibit Falling Transition t OFF1 High-Z 25

26 Hidden Refresh Cycle t RC t RC t t RP t t RP t RCD t RSH t CHR t CRP t RAD t t RAL ASR t RAH t ASC t CAH Row Column t RCS t RRH t CAC (Input) t DZC t DZO t AA t RAC t OAC Valid Dout t OFF1 t OFF2 t DTS t DTH Read Transfer Cycle (1) trc t t RP t ASR t RCD t RAD trah t ASC t CAH t CSH t RSH t t RAL t CRP Row SAM Start t WS t WH SC S S (Input) t DTS t SCA t SOH Valid Sout t RDH t CDH t ADH t DTP t DRD t DTHH t SCC t SCC t SCC t SCC t SDD t SDH t SC t SCP t SCA t SOH t SCA t SOH High-Z Previous Row t SCA t SOH t SOH Valid Sout Valid Sout Valid Sout Valid Sout New Row 26

27 Read Transfer Cycle (2) t RC t t RP t RCD t RAD t ASR t RAH t ASC t CAH Row Sam Start t CSH t RSH t t RAL t CRP t WS t WH SC S S (Input) t SIS Valid Sin t DTS t DRD t DTP t SCH t t SAH SRS t t SCC SDH t SC t SC t SCP Inhibit Rising Transition t SCA t SRH t SIH t DTH High-Z t SZS t DTHH t SCP t SOH Valid Sout tsca 27

28 Pseudo Transfer Cycle trc t trp tcsh tcrp trcd trsh t tasr trah tasc tcah Row SAM Start tws twh tdts tdth High - Z tes tsez teh tsws SE tsrs tsc tsrd tscp tsc tscc tscp SC S Valid Sout tsca tsoh tsrz Valid Sout Inhibit Rising Transition tsid tsis tsih tsis tsih S (Input) Valid Sin Valid Sin 28

29 Write Transfer Cycle trc t trp tcsh tcrp trcd trsh t tasr trah tasc tcah Row SAM Start tws twh tdts tdth High-Z tes teh tsws SE tsrs tsws tsc tscp tsrd tsc tscc tscp SC Inhibit Rising Transition S tsis tsih tsis tsih tsis tsih S (Input) Valid Sin Valid Sin Valid Sin 29

30 Serial Read Cycle SE SC S t SCC t SC t SCA t SOH t SCP t SEZ t SCC t SC t SCP t SC t SEA t SCA t SCP t SCC t SC t SCA t SOH Valid Sout Valid Sout Valid Sout Valid Sout Serial Write Cycle SE t SWH t SWIS t SWIH t SWS SC S (Input) t SIS t SC t SIH t SCC tscp t SCC t SC t SCP t SIS t SCC t SC t SCP Valid Sin Valid Sin Valid Sin t SIH t SIS t SIH t SC 30

31 Package Dimensions HM534251BJ Series (CP-28D) Unit: mm Max ± ± Max 3.50 ± ± ±

32 HM534251BZ Series (ZP-28) Unit: mm Max Max Max 2.80 Min M