4-Mbit (256K x 16) Static RAM

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4-Mbit (256K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to +85 C Automotive-A: 40 C to +85 C Automotive-E: 40 C to +125 C Very high speed: 45 ns Wide voltage range: 2.20V 3.

1 4-Mbit (256K x 16) Static RAM Features Temperature Ranges Industrial: 40 C to +85 C Automotive-A: 40 C to +85 C Automotive-E: 40 C to +125 C Very high speed: 45 ns Wide voltage range: 2.20V 3.60V Pin-compatible with CY62147CV25, CY62147CV30, and CY62147CV33 Ultra-low active power Typical active current: 1.5 f = 1 MHz Typical active current: 8 f = f max Ultra low standby power Easy memory expansion with, and OE features Automatic power-down when deselected CMOS for optimum speed/power Available in Pb-free and non Pb-free 48-ball VFBGA and non Pb-free 44-pin TSOPII Byte power-down feature Functional Description [1] The is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL ) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode reducing power consumption by more than 99% when deselected ( HIGH or both BLE and BHE are HIGH). The input/output pins (I/O 0 through I/O 15 ) are placed in a high-impedance state when: deselected ( HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation ( LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable () and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O 7 ), is written into the location specified on the address pins (A 0 through A 17 ). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O 15 ) is written into the location specified on the address pins (A 0 through A 17 ). Reading from the device is accomplished by taking Chip Enable () and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O 0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O 15. See the truth table at the back of this data sheet for a complete description of read and write modes. The is available in a 48-ball VFBGA, 44 Pin TSOPII packages. Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 A 5 A 4 256K x 16 RAM Array I/O 0 I/O 7 A 2 I/O 8 I/O 15 A 3 A 1 A 0 ROW DECODER SENSE AMPS COLUMN DECODER Power -Down Circuit A 11 A 12 A 13 A 14 A 15 A 16 A 17 Note: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on BHE BLE BHE WE OE BLE Cypress Semiconductor Corporation 198 Champion Court San Jose, CA Document #: Rev. *F Revised August 31, 2006

Pin Configuration [2, 3, 4] VFBGA (Top View) 44 TSOP II (Top View) 1 2 3 4 5 6 BLE I/O 8 I/O 9 V SS I/O 14 I/O 15 NC OE BHE I/O 10 I/O 11 I/O 12 I/O 13 NC A 8 A 0 A 3 A 5 A 17 DNU A 14 A 12 A 9 A 1 A

2 Pin Configuration [2, 3, 4] VFBGA (Top View) 44 TSOP II (Top View) BLE I/O 8 I/O 9 V SS I/O 14 I/O 15 NC OE BHE I/O 10 I/O 11 I/O 12 I/O 13 NC A 8 A 0 A 3 A 5 A 17 DNU A 14 A 12 A 9 A 1 A 4 A 6 A 7 A 16 A 15 A 13 A 10 A 2 NC I/O 0 I/O 1 I/O 2 I/O 3 Vcc I/O 4 Vss I/O 5 I/O 6 WE I/O 7 A 11 NC A B C D E F G H A 4 A 3 A 2 A 1 A 0 I/O 0 I/O 1 I/O 2 I/O 3 V SS I/O 4 I/O 5 I/O 6 I/O 7 WE A 17 A 16 A 15 A 14 A A 5 A 6 A 7 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 V SS I/O 11 I/O 10 I/O 9 I/O 8 NC A 8 A 9 A 10 A 11 A12 Product Portfolio Product Power Dissipation Operating I Speed CC (ma) Standby I SB2 Range Range (V) (ns) f = 1MHz f = f max (µa) Min. Typ. [5] Max. Typ. [5] Max. Typ. [5] Max. Typ. [5] Max. LL Industrial 2.2V LL Industrial 2.2V L Auto-E 25 LL Industrial 2.2V LL Auto-A 8 Notes: 2. NC pins are not internally connected on the die. 3. DNU pins have to be left floating or tied to V SS to ensure proper application. 4. Pins H1, G2, and H6 in the VFBGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at = (typ.), T A = 25 C. Document #: Rev. *F Page 2 of 12

3 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature C to +150 C Ambient Temperature with Power Applied C to +125 C Supply Voltage to Ground Potential V to + (MAX) + 0.3V DC Voltage Applied to Outputs in High-Z State [6,7] V to (MAX) + 0.3V DC Input Voltage [6,7] V to (MAX) + 0.3V Output Current into Outputs (LOW) ma Static Discharge Voltage... >2001V (per MIL-STD-883, Method 3015) Latch-up Current... >200 ma Operating Range Device Range Ambient Temperature [T A ] [9] L Automotive-E 40 C to +125 C 2.20V LL Industrial 40 C to +85 C to 3.60V Automotive-A 40 C to +85 C Electrical Characteristics (Over the Operating Range) 45 55/ 70 Parameter Description Test Conditions Min. Typ. [5] Max. Min. Typ. [5] Max. Unit V OH Output HIGH I OH = 0.1 ma = 2.20V V Voltage I OH = 1.0 ma = 2.70V V V OL Output LOW I OL = 0.1 ma = 2.20V V Voltage I OL = 2.1 ma = 2.70V V V IH Input HIGH = 2.2V to 2.7V V V V Voltage = 2.7V to 3.6V V V V V IL Input LOW = 2.2V to 2.7V V Voltage = 2.7V to 3.6V V I IX Input Leakage GND < V I < Ind l µa Current Auto-A [9] 1 +1 µa Auto-E [9] 4 +4 µa I OZ Output GND < V O <, Ind l µa Leakage Output Disabled Current Auto-A [9] 1 +1 µa Auto-E [9] 4 +4 µa I CC Operating f = f MAX = 1/t RC = max ma Supply I OUT = 0 ma f = 1 MHz Current CMOS levels ma I SB1 Automatic > 0.2V, Ind l LL 8 8 µa Power-Down Current V IN > 0.2V, V IN <0.2V) Auto-A f = f MAX (Address and LL 8 CMOS Inputs Data Only), f = 0 (OE, WE, BHE and BLE), = 3.60V Auto-E [9] L 25 I SB2 Automatic > 0.2V, Ind l LL 8 8 µa Power-Down Current V IN > 0.2V or V IN < 0.2V, Auto-A [9] LL 8 CMOS Inputs f = 0, = 3.60V Auto-E [9] L 25 Notes: 6. V IL(min.) = 2.0V for pulse durations less than 20 ns. 7. V IH(max.) = V for pulse durations less than 20 ns. 8. Full device AC operation assumes a 100-µs ramp time from 0 to (min) and 200-µs wait time after stabilization. 9. Auto-A is available in 70 and Auto-E is available in 55. Document #: Rev. *F Page 3 of 12

4 Capacitance (for all packages) [10] Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 10 pf C OUT Output Capacitance = (typ) 10 pf Thermal Resistance [10] Parameter Description Test Conditions VFBGA TSOP II Unit Θ JA Thermal Resistance Still Air, soldered on a inch, four-layer C/W (Junction to Ambient) printed circuit board Θ JC Thermal Resistance (Junction to Case) C/W AC Test Loads and Waveforms [10] OUTPUT 50 pf R1 R2 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉ VENIN EQUIVALENT R TH OUTPUT V Parameters 2.50V 3.0V Unit R Ω R Ω R TH Ω V TH V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min. Typ. [5] Max. Unit V DR for Data Retention 1.5 V I CCDR Data Retention Current = 1.5V L (Auto-E) 15 µa > 0.2V, V IN > 0.2V or V IN < 0.2V LL (Ind l/auto-a) 6 t [10] CDR Chip Deselect to Data Retention 0 ns Time t [12] R Operation Recovery Time t RC ns Data Retention Waveform [13] (min) DATA RETENTION MODE V DR > 1.5 V (min) or BHE.BLE t CDR t R Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. Test condition for the 45-ns part is a load capacitance of 30 pf. 12. Full device operation requires linear ramp from V DR to (min.) > 100 µs or stable at (min.) > 100 µs. 13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: Rev. *F Page 4 of 12

5 Switching Characteristics Over the Operating Range [14] 45 ns [11] 55 ns 70 ns Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t RC Read Cycle Time ns t AA Address to Data Valid ns t OHA Data Hold from Address Change ns t A LOW to Data Valid ns t DOE OE LOW to Data Valid ns t LZOE OE LOW to LOW Z [15] ns t HZOE OE HIGH to High Z [15, 16] ns t LZ LOW to Low Z [15] ns t HZ HIGH to High Z [15, 16] ns t PU LOW to Power-Up ns t PD HIGH to Power-Down ns t DBE BLE/BHE LOW to Data Valid ns t LZBE BLE/BHE LOW to Low Z [15] ns t HZBE BLE/BHE HIGH to HIGH Z [15, 16] ns Write Cycle [17] t WC Write Cycle Time ns t S LOW to Write End ns t AW Address Set-up to Write End ns t HA Address Hold from Write End ns t SA Address Set-up to Write Start ns t PWE WE Pulse Width ns t BW BLE/BHE LOW to Write End ns t SD Data Set-up to Write End ns t HD Data Hold from Write End ns t HZWE WE LOW to High-Z [15, 16] ns t LZWE WE HIGH to Low-Z [15] ns Notes: 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of (typ) /2, input pulse levels of 0 to (typ.), and output loading of the specified I OL /I OH as shown in the AC Test Loads and Waveforms section. 15. At any given temperature and voltage condition, t HZ is less than t LZ, t HZBE is less than t LZBE, t HZOE is less than t LZOE, and t HZWE is less than t LZWE for any given device. 16. t HZOE, t HZ, t HZBE, and t HZWE transitions are measured when the outputs enter a high impedence state. 17. The internal Write time of the memory is defined by the overlap of WE, = V IL, BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: Rev. *F Page 5 of 12

6 Switching Waveforms Read Cycle 1 (Address Transition Controlled) [18, 19] t RC ADDRESS t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [19, 20] ADDRESS t RC OE t A t PD t HZ BHE/BLE t LZOE t DOE t HZOE t HZBE t DBE DATA OUT t LZBE HIGH IMPEDAN DATA VALID HIGH IMPEDAN t LZ SUPPLY CURRENT t PU 50% 50% I CC I SB Notes: 18. The device is continuously selected. OE, = V IL, BHE and/or BLE = V IL. 19. WE is HIGH for read cycle. 20. Address valid prior to or coincident with and BHE, BLE transition LOW. Document #: Rev. *F Page 6 of 12

7 Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) [17, 21, 22] t WC ADDRESS t S t AW t HA WE t SA t PWE BHE/BLE t BW OE t SD t HD DATA I/O NOTE23 DATA IN t HZOE Write Cycle No. 2 ( Controlled) [17, 21, 22] t WC ADDRESS t S t SA t AW t HA WE t PWE BHE/BLE t BW OE t SD t HD DATA I/O NOTE 23 DATA IN t HZOE Notes: 21. Data I/O is high impedance if OE = V IH. 22. If goes HIGH simultaneously with WE = V IH, the output remains in a high-impedance state. 23. During this period, the I/Os are in output state and input signals should not be applied. Document #: Rev. *F Page 7 of 12

8 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [22] t WC ADDRESS t S BHE/BLE t BW t AW t HA t SA t PWE WE t SD t HD DATAI/O NOTE 23 DATA IN t HZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [22] t LZWE t WC ADDRESS t S t AW t HA BHE/BLE t BW t SA WE t PWE t HZWE t SD t HD DATA I/O NOTE 23 DATA IN t LZWE Document #: Rev. *F Page 8 of 12

9 Truth Table WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (I SB ) X X X H H High Z Deselect/Power-Down Standby (I SB ) L H L L L Data Out (I/O O I/O 15 ) Read Active (I CC ) L H L H L Data Out (I/O O I/O 7 ); I/O 8 I/O 15 in High Z L H L L H Data Out (I/O 8 I/O 15 ); I/O 0 I/O 7 in High Z Read Active (I CC ) Read Active (I CC ) L H H L L High Z Output Disabled Active (I CC ) L H H H L High Z Output Disabled Active (I CC ) L H H L H High Z Output Disabled Active (I CC ) L L X L L Data In (I/O O I/O 15 ) Write Active (I CC ) L L X H L Data In (I/O O I/O 7 ); I/O 8 I/O 15 in High Z L L X L H Data In (I/O 8 I/O 15 ); I/O 0 I/O 7 in High Z Ordering Information Speed (ns) Ordering Code Package Diagram Write Active (I CC ) Write Active (I CC ) Package Type Operating Range 45 LL-45BVXI ball (6 mm 8mm 1 mm) VFBGA (Pb-free) Industrial LL-45ZSXI pin TSOP II (Pb-free) 55 LL-55BVI ball (6 mm 8mm 1 mm) VFBGA Industrial LL-55BVXI 48-ball (6 mm 8mm 1 mm) VFBGA (Pb-free) LL-55ZSXI pin TSOP II (Pb-free) L-55BVXE ball (6 mm 8mm 1 mm) VFBGA (Pb-free) Automotive-E L-55ZSXE pin TSOP II (Pb-free) 70 LL-70BVI ball (6 mm 8mm 1 mm) VFBGA Industrial LL-70BVXA 48-ball (6 mm 8mm 1 mm) VFBGA (Pb-free) Automotive-A Document #: Rev. *F Page 9 of 12

10 Package Diagram 48-ball VFBGA (6 x 8 x 1 mm) ( ) TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C A1 CORNER Ø0.25 M C A B Ø0.30±0.05(48X) A A B B C C 8.00±0.10 D E F G 8.00± D E F G H H A A B 6.00± B 6.00± C 0.55 MAX. 0.21± C 0.15(4X) *D SEATING PLANE 0.26 MAX. C 1.00 MAX Document #: Rev. *F Page 10 of 12

11 Package Diagram (continued) 44-Pin TSOP II ( ) *A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: Rev. *F Page 11 of 12 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

12 Document History Page Document Title: MoBL 4-Mbit (256K x 16) Static RAM Document Number: REV. ECN NO. Issue Date Orig. of Change ** /17/03 HRT New Data Sheet Description of Change *A /23/04 CBD Changed from Advance to Preliminary *B See ECN AJU Changed from Preliminary to Final Added 70 ns speed bin Modified footnote 7 to include ramp time and wait time Modified input and output capacitance values to 10 pf Modified Thermal Resistance values on page 4 Added Byte power-down feature in the features section Modified Ordering Information for Pb-free parts *C See ECN PCI Modified ordering information for 70-ns Speed Bin *D See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #10 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-lead TSOP-II package name on page 11 from Z44 to ZS44 Standardized Icc values across L and LL bins *E See ECN AJU Added Automotive product information *F See ECN NXR Added Automotive-A range Added note# 9 on page# 3 Updated ordering information table Document #: Rev. *F Page 12 of 12

16-Mbit (1M x 16) Static RAM

16-Mbit (1M x 16) Static RAM Features Very high speed: 55 ns Wide voltage range: 1.65V 1.95V Ultra low active power Typical active current: 1.5 ma @ f = 1 MHz Typical active current: 15 ma @ f = f max