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2 3.3V 256 K x 16-Bit Dynamic RAM 3.3V ow Power 256 K x 16-Bit Dynamic RAM with Self Refresh YB BJ-50/-60/-70 YB BJ-50/-60/ words by 16-bit organization 0 to 70 C operating temperature Fast access and cycle time access time: 50 ns (-50 version) 60 ns (-60 version) 70 ns (-70 version) CAS access time: 15ns (-50,-60 version) 20 ns (-70 version) Cycle time: 95 ns (-50 version) 110 ns (-60 version) 130 ns (-70 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) 45 ns (-70 version) Single V (± 0.3 V) supply with a builtin VBB generator ow Power dissipation max. 450 mw active (-50 version) max. 378 mw active (-60 version) max. 306 mw active (-70 version) Standby power dissipation 7.2 mw standby (TT) 3.6 mw max. standby (CMOS) 0.72 mw max. standby (CMOS) for ow Power Version Output unlatched at cycle end allows twodimensional chip selection Read, write, read-modify write, CASbefore- refresh, -only refresh, hidden-refresh and fast page mode capability 2 CAS / 1 control Self Refresh (-Version) All inputs and outputs TT-compatible 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms ow Power Version only Plastic Packages: P-SOJ mil width The YB BJ/BJ is a 4 MBit dynamic RAM organized as words by 16-bit. The YB BJ/BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the YB BJ/BJ to be packed in a standard plastic 400mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include Self Refresh (-Version), single V (± 0.3 V) power supply, direct interfacing with high performance logic device families. Semiconductor Group

3 Ordering Information Type Ordering Code Package Description YB BJ-50 P-SOJ V 50ns 256 K x 16 DRAM YB BJ-60 P-SOJ V 60 ns 256 K x 16 DRAM YB BJ-70 P-SOJ V 70 ns 256 K x 16 DRAM YB BJ-50 P-SOJ V 50 ns 256 K x 16 DRAM YB BJ-60 P-SOJ V 60 ns 256 K x 16 DRAM YB BJ-70 P-SOJ V 70 ns 256 K x 16 DRAM Truth Table CAS Operation igh-z igh-z Standby igh-z igh-z Refresh Dout igh-z ower byte read igh-z Dout Upper byte read Dout Dout Word read Din Don't care ower byte write Don't care Din Upper byte write Din Din Word write igh-z igh-z Pin Names A0-A8 Address Inputs Address Strobe, CAS Address Strobe Read/Write Input Output Enable 1 16 Data Input/Output V CC Power Supply (+ 3.3 V) V SS Ground (0 V) N.C. No Connection Semiconductor Group 2

4 Semiconductor Group 3 Pin Configuration P-SOJ Vcc Vcc N.C. N.C. N.C. A0 A1 A2 A3 Vcc Vss Vss N.C. CAS A8 A7 A6 A5 A4 Vss 22 21

5 Block Diagram CAS.. & Data in Buffer Data out Buffer No. 2 Clock Generator A0 A1 A2 A3 A4 A5 A6 A7 A8 9 Address Buffer(9) Refresh Controller Refresh Counter (9) 9 Decoder Sense Amplifier Gating 512 x Address 9 Buffers(9) Decoder 512 Memory Array 512 x 512 x 16 No. 1 Clock Generator Substrate Bias Generator VCC VSS Semiconductor Group 4

6 Absolute Maximum Ratings Operating temperature range...0 to + 70 C Storage temperature range to C Input/output voltage... 1 to (Vcc+0.5, 4.6) V Power supply voltage... 1 to +4.6 V Data out current (short circuit) ma Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics lv T A = 0 to 70 C; V SS = 0 V; V CC = 3.3 V ± 0.3 V, t T = 5 ns Parameter Symbol imit Values Unit Notes min. max. Input high voltage 2.0 Vcc+0.5 V 1 Input low voltage V 1 VTT Output high voltage (I OUT = 2.0 ma) V O 2.4 V 1 VTT Output low voltage (I OUT = 2 ma) V O 0.4 V 1 Input leakage current, any input (0 V < V IN < Vcc+0.3 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < V OUT < V CC V ) Average V CC supply current: -50 version -60 version -70 version I I() µa 1 I O() µa 1 I CC ma 2, 3, 4 Standby V CC supply current ( = CAS = = = ) Average V CC supply current during -only refresh cycles: -50 version -60 version -70 version I CC2 2 ma I CC ma 2, 4 Semiconductor Group 5

7 DC Characteristics (cont d) Parameter Symbol imit Values Unit Notes Average V CC supply current during fast page mode operation: -50 version -60 version -70 version min. max. I CC ma 2, 3, 4 Standby V CC supply current ( = CAS = = = V CC 0.2 V) Average V CC supply current during CAS-before- refresh mode: -50 version -60 version -70 version I CC5 1 ma 1 I CC ma 2, 4 Standby V CC current (-version) ( = CAS = = = V CC 0.2 V) Self Refresh Current (-version) (, CAS, = 0.2V A0 A8= V CC 0.2V or 0.2V) I CC5 200 µa I CCS 250 µa Capacitance T A = 0 to 70 C; V CC = 3.3 V ± 0.3 V, f = 1 Mz Parameter Symbol imit Values Unit min. max. Input capacitance (A0 to A8) C I1 6 pf Input capacitance (,, CAS,, ) C I2 7 pf Output capacitance (l/o1 to l/o16) C IO 7 pf Semiconductor Group 6

8 AC Characteristics 5)6) T A = 0 to 70 C; V SS = 0 V; V CC = 3.3 V ± 0.3 V, t T = 5 ns Parameter Symbol imit Values Unit Note common parameters min. max. min. max. min. max. Random read or write cycle time t RC ns precharge time t RP ns pulse width t 50 10k 60 10k 70 10k ns CAS pulse width t CAS 15 10k 15 10k 20 10k ns address setup time t ASR ns address hold time t RA ns address setup time t ASC ns address hold time t CA ns to CAS delay time t RCD ns to column address delay time t RAD ns hold time t RS ns CAS hold time t CS ns CAS to precharge time t CRP ns Transition time (rise and fall) t T ns 7 Refresh period t REF ms Refresh period (-version) t REF ms Read Cycle Access time from t RAC ns 8, 9 Access time from CAS t CAC ns 8, 9 Access time from column address t AA ns 8,10 access time t A ns address to lead time t RA ns Read command setup time t RCS ns Read command hold time t RC ns 11 Read command hold time ref. to t RR ns 11 CAS to output inlow-z t CZ ns 8 Semiconductor Group 7

9 Parameter Symbol imit Values Unit Note Output buffer turn-off delay from CAS Output buffer turn-off delay from min. max. min. max. min. max. t OFF ns 12 t Z ns 12 Data to low delay t DZO ns 13 CAS high to datadelay t CDD ns 14 high to data delay t ODD ns 14 Write Cycle Write command hold time t WC ns Write command pulse width t WP ns Write command setup time t WCS ns 15 Write command to lead time t RW ns Write command to CAS lead time t CW ns Data setup time t DS ns 16 Data hold time t D ns 16 Data to CAS lowdelay t DZC ns 13 Read-modify-Write Cycle Read-write cycle time t RWC ns to delay time t RWD ns 15 CAS to delay time t CWD ns 15 address to delay time t AWD ns 15 command hold time t ns Fast Page Mode Cycle Fast page mode cycle time t PC ns CAS precharge time t CP ns Access time from CAS precharge t CPA ns 7 pulse width t P k k k ns hold time from CAS precharge t RCP ns Semiconductor Group 8

10 Parameter Symbol imit Values Unit Note min. max. min. max. min. max. Fast Page Mode Read Modify Write Cycle Fast page mode read/write cycle time t PRWC ns CAS precharge to delay time t CPWD ns CAS before refresh Cycle CAS setup time t CSR ns CAS hold tim t CR ns to CAS precharge time t RPC ns Write to precharge time t WRP ns Write to hold time t WR ns CAS-before counter test cycle CAS precharge time t CPT ns Self Refresh Cycle (-Version only) pulse width t S µs precharge time t RPS ns CAS hold time Self Refresh t CS ns Semiconductor Group 9

11 Notes: 1) All voltages are referenced to V SS. 2) I CC1, I CC3, I CC4 and I CC6 depend on cycle rate. 3) I CC1 and I CC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while = Vil. In case of ICC4 it can be changed once or less during a page mode cycle 5) An initial pause of 200 µs is required after power-up followed by 8 cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before- initialization cycles instead of 8 cycles are required. 6) AC measurements assume t T = 5 ns. 7) (min.) and (max.) are reference levels for measuring timing of input signals. Transition times are also measured between and. 8) Measured with a load equivalent to 100 pf and at Voh=2.0V (Ioh=-2mA), Vol=0.8V (Iol=2mA). 9) Operation within the t RCD (max.) limit ensures that t RAC (max.) can be met. t RCD (max.) is specified as a reference point only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled by t CAC. 10) Operation within the t RAD (max.) limit ensures that t RAC (max.) can be met. t RAD (max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled by t AA. 11) Either t RC or t RR must be satisfied for a read cycle. 12) t OFF (max.), t Z (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 13) Either t DZC or t DZO must be satisfied. 43) Either t CDD or t ODD must be satisfied. 15) t WCS, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS > t WCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t RWD > t RWD (min.), t CWD > t CWD (min.) and t AWD > t AWD (min.), the cycle is a read-write cycle and will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the leading edge in read-write cycles. Semiconductor Group 10

12 trc t trcd tcs trs tcrp tcas CAS trad tasc tca tra Address trc t RA trcs trr taa ta tdzc tcdd tdzo todd (Inputs) tcac toff (Outputs) V O V O i Z tcz tz Valid Data Out i Z trac or W1 Read Cycle Semiconductor Group 11

13 trc t trcd tcs trs tcrp CAS trad tcas t RA Address tasc tca. t RA twcs tcw twp twc trw tds td (Inputs) Valid Data In (Outputs) V O V O i Z or W2 Write Cycle (Early Write) Semiconductor Group 12

14 trc t trcd tcs trs tcrp CAS Address trad tasc tcas tra tca tcw. t RA trw twp t tdzo todd tds td tdzc tz (Inputs) tcz Valid Data ta (Outputs) V O V O i-z i-z or W3 Write Cycle ( Controlled Write) Semiconductor Group 13

15 trwc t trcd tcs trs tcas tcrp CAS t RA tasc tca Address trad tawd trwd tcwd tcw trw twp taa trcs ta t tdzo tds tdzc td (Inputs) tcz todd Valid Data in tcac tz V O (Outputs) V O Data Out trac or W4 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 14

16 tp tpc trcp trcd tcas tcp tcas trs t CAS tcrp CAS tcs Address tra tasc tca trad tca tasc tca tasc trc trcs trc trcs trcs taa tcpa taa tcpa taa trr (Inputs) V O (Outputs) V O ta ta ta tdzc tdzc tdzc tcdd tdzo tdzo tdzo todd todd todd tcac tcac toff tcac toff toff trac tz tz tz tcz tcz tcz Valid Valid Valid Data Out Data Out Data Out or FPM1 Fast Page Mode Read Cycle Semiconductor Group 15

17 t tpc t RS trcd tcas tcp tcas tcas tcrp CAS Address tra trad twcs tca tasc tcw twc twp tasc twcs tca tcw twc twp tasc twcs tra tca tcw trw twc twp td td td tds tds tds (Inputs) Valid Data In Valid Data In Valid Data In V O (Outputs) V O I-Z or FPM2 Fast Page Mode Early Write Cycle Semiconductor Group 16

18 CAS Address (Inputs) (Outputs) V O V O t tcs tprwc trs trcd tcas tcp tcas tcas trad tra tasc tca tasc tca tasc tca tra Address trwd tcpwd tcpwd trw trcs tcwd tcw tcwd tcwd tcw tcw tawd taa twp ta tawd tawd twp twp ta ta tdzc tcpa tcpa tcz tdzc todd tdzc todd tdzo Data In Data In Data In tcz tcz todd t t t tcac tcac trac taa tz td tz td taa tz td Data Out tds tds Data Data Out Out tds or tcrp Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 17

19 trc t tcrp C CAS tra Address V O (Outputs) V O I-Z or W9 -Only Refresh Cycle Semiconductor Group 18

20 trc t C tcsr tcrp CAS tcp twrp tcr C twr tz tcdd (Inputs) todd V O (Outputs) V O I-Z toff or W10 CAS-Before- Refresh Cycle Semiconductor Group 19

21 ts S C tcsr tcs tcrp CAS tcp twrp twr tcdd (Inputs) todd tz (Outputs) V O V O I-Z toff or W13 CAS before Self Refresh Cycle Semiconductor Group 20

22 trc trc t t trcd trs tcr tcrp CAS trad tasc twrp tra tca twr Address trcs trr taa ta tdzc tcdd tdzo todd (Inputs) tcac toff trac tcz tz (Outputs) V O V O Valid Data Out I-Z or W11 idden Refresh Cycle (Read) Semiconductor Group 21

23 trc trc t t trcd trs tcr tcrp CAS tra trad tasc tca Address twcs twc twrp twr twp tds td (Input) V I Valid Data (Output) V O V O I-Z or W12 idden Refresh Cycle (Early Write) Semiconductor Group 22

24 Read Cycle: t tcsr tcr tcp trs tcas CAS tasc tca tra Address twrp twr trcs taa tcac ta trr trc (Inputs) tdzc tdzo tcdd todd toff (Outputs) V O V O tcz Data Out tz Write Cycle: twrp twcs trw tcw twc twr (Inputs) tds td Data In (Outputs) I-Z CAS/-Before- Refresh Counter Test Cycle Semiconductor Group 23

25 Plastic Package, P-SOJ (SMD) (Plastic small outline J-lead) GPJ09018(W) Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Dimensions in mm Package Outline Semiconductor Group 24

26 REVISION CANGES: REV CMOS OUTPUT EVES REMOVED Semiconductor Group 25

HM514400B/BL Series HM514400C/CL Series

ADE-203-269A (Z) HM514400B/BL Series HM514400C/CL Series 1,048,576-word 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576-