LH NMOS 256K (256K 1) Dynamic RAM DESCRIPTION

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1 LH2256 NMOS 256K (256K ) Dynamic RAM FEATURES 262,44 bit organization Access times: 00/20/50 ns (MAX.) Cycle times: 200/230/260 ns (MIN.) Page mode operation Power supply: +5 V ± 0% Power consumption: Operating: 467.5/440/385 mw (MAX.) Standby: 27.5 mw (MAX.) TTL compatible I/O Built-in gated function Separate I/O allows Early-Write action Available for read modify write, only refresh, hidden refresh, before refresh 256 refresh cycle (refreshing time 4 ms) Built-in high output bias generator circuit DESCRIPTION The LH2256 is a 262,44 word bit dynamic RAM fabricated using N-channel 2-layer polysilicon gate process technology. With mulitiplexed address inputs and standard 6-pin DIP/ZIP packages, it is easy to comprise memory systems with high speed, low power consumption and large memory capacity. The LH2256 operates on a single +5 V power supply. The built-in high output substrate bias generator circuit eliminates sensitivity to undershoot on the input signals. PIN CONNECTIONS 6-PIN DIP 6-PIN ZIP A 8 D IN A 0 A 2 A V CC V SS A 6 A 3 A 4 A 5 A 7 TOP VIEW Packages: 6-pin, 300-mil DIP 6-pin, 325-mil ZIP A 6 3 A A 0 9 A A 7 3 A V SS 6 D IN 8 0 A 2 2 V CC 4 A 5 6 A 3 Figure. Pin Connections for DIP and ZIP Packages

2 LH2256 NMOS 256K (256K ) Dynamic RAM 4 5 CLOCK GENERATOR CLOCK GENERATOR 2 INPUT COLUMN BUFFER ROW BUFFER REFRESH COUNTER EXT/INT MUX. ROW DECODER COLUMN DECODER SENSE AMPLIFIERS MEMORY ARRAY WRITE CLOCKS I/O SELECTOR DATA IN BUFFER DATA OUT BUFFER D IN V CC 8 V SS 6 V BB GENERATOR NOTE: Pin numbers apply to 6-pin DIP Figure 2. LH2256 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME Address input Row address strobe Column address strobe Write enable SIGNAL PIN NAME D IN Data input Data output V CC Power supply (+5 V) V SS Power supply (0 V) ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Supply voltage V T -.0 to 7.0 V Output short-circuit current I O 50 ma Power consumption P D.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +50 C NOTE:. Referenced to V SS 2-2

3 NMOS 256K (256K ) Dynamic RAM LH2256 RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70 C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE Supply voltage Input voltage NOTE:. Referenced to V SS V CC V SS V V CAPACITANCE (V CC = 5 V ± 0%, T A = 0 to +70 C, f = MHz) PARAMETER SYMBOL MIN. TYPICAL MAX. UNIT, Input capacitance D IN, C IN 7 pf, C IN2 0 pf Output capacitance C OUT 8 pf DC CHARACTERISTICS (V CC = 5 V ± 0%, T A = 0 to +70 C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE 65 LH Average supply current I in normal operation LH CC 80 ma, 2 LH Average supply current in standby mode I CC2 5.0 ma LH Average supply current in only refresh time LH I CC3 60 ma, 2 LH LH Average supply current I in page mode LH CC4 45 ma, 2 LH before LH average supply current LH I CC5 60 ma, 2 in refresh cycle LH Input leakage current 0 V V IN 6.5 V 0 V on all other pins I I(L) -0 0 µa Output leakage current 0 V V OUT 6.5 V Output in high-impedance state I O(L) -0 0 µa Output High voltage I OUT = -5 ma 2.4 V Output Low voltage I OUT = 4.2 ma 0.4 V NOTES:. The output pins are in high-impedance state. 2. I CC, I CC3, I CC4, and I CC5 depend on the cycle time. 2-3

4 LH2256 NMOS 256K (256K ) Dynamic RAM AC CHARACTERISTICS, 2, 3 (V CC = 5 V ± 0%, T A = 0 to 70 C) PARAMETER SYMBOL LH LH LH MIN. MAX. MIN. MAX. MIN. MAX. UNIT NOTE Random read/write cycle time t RC ns Read write cycle time t RWC ns Access time from t RAC ns 4, 6 Access time from tcac ns 5, 6 Output turn-off delay time t OFF ns Rise and fall time tt ns 3 precharge time trp ns pulse width t 00 0, , ,000 ns hold time t RSH ns precharge time t CPN ns pulse width t 50 0, , ,000 ns hold time tcsh ns hold time ( before ) tfch ns set up time ( before ) t FCS ns / delay time trcd ns 7, 8 / precharge time tcrp ns Row address setup time tasr ns Row address hold time trah ns Column address setup time tasc ns Column address hold time ns Column address hold time from t AR ns Read command setup time t RCS ns Read command hold time t RCH ns Read command hold time from t RRH ns Write command setup time t WC S ns 0 Write command hold time t WCH ns Write command hold time from twcr ns Write command pulse width twp ns Write command lead time trwl ns Write command lead time tcwl ns write command delay time trwd ns write command delay time tcwd ns Data input setup time tds ns 9 Data input hold time t DH ns 9 Data input hold time from t DHR ns Refresh time t REF ms precharge hold time C ns NOTES:. For proper operation, at least 500 µs of pause time after power-on followed by several initialization cycles (usually 8 ordinary refresh cycles) should be given. 2. AC characteristics assume t T = 5 ns. 3. Timing measurements are referenced to (MIN.) and (MAX.). (t T refers to the transition time between and.) 4. Only when t RCD t RCD (MAX.). If t RCD > t RCD (MAX.), t RAC will increase by (t RCD - t RCD (MAX.)) 5. When t RCD t RCD (MAX.). 6. Load condition for 2TTL + 00 pf. 7. t RCD (MAX.) is the maximum point for t RCD where t RAC (MAX.) is ensured, and does not represent a limit of operation. If t RCD (MAX.) t RCD, the access time is controlled by t CAC. 8. t RCD (MIN.) = t RAH (MIN.) + 2t T + (MIN.). 9. t DS and t DH are given with respect to the fall of in the Early-Write cycle and the fall of in the read/write cycle and the Read-Modify-Write cycle. 0. t WCS, t CWD and t RWD are the specified points of the operating mode, and do not represent a limit of operation. When t WCS t WCS (MIN.), it comes into early write cycle with pin coming into high-impedance state. When t CWD t CWD (MIN.) and t RWD t RWD (MIN.), it comes into the read/write cycle with the output data becoming the information for the selection cell. Timing other than the above-mentions will give undefined value of output.. The operation is ensured when either t RCH or t RRH is satisfied. 2-4

5 NMOS 256K (256K ) Dynamic RAM LH2256 t RC t t CSH t RCD t RSH t CRP t t AR t CPN t ASR t RAH ROW COLUMN t RCS t RRH t RCH t CAC t RAC t OFF DATA VALID Figure 3. Read Cycle 2-5

6 LH2256 NMOS 256K (256K ) Dynamic RAM t RC t t RSH t CSH t CRP t RCD t t AR t CPN t ASR t RAH ROW COLUMN t WCR t CWL t WCS t WCH t WP t RWL t DS t DH D IN DATA VALID t DHR Figure 4. Write Cycle (Early Write) 2-6

7 NMOS 256K (256K ) Dynamic RAM LH2256 t RWC t t AR t RSH t CSH t CRP t RCD t t RAH t CPN t ASR ROW COLUMN t RCS t CWL t CWD t RWL t RWD t WP t CAC t OFF DATA VALID t RAC t DS t DH D IN DATA VALID Figure 5. Read-Write/Read-Modify-Write Cycle 2-7

8 LH2256 NMOS 256K (256K ) Dynamic RAM t RC t t RAH t ASR A 0 - A 7 ROW NOTE: = Figure 6. Only Refresh Cycle t RC t t AR t t t RCD t RSH t CRP t t RAH t CPN t ASR 2 t RCS t RRH t RCH t CAC t OFF t RAC DATA VALID NOTES:. Row address 2. Column address Figure 7. Hidden Refresh Cycle 2-8

9 NMOS 256K (256K ) Dynamic RAM LH2256 t RC t t FCS t FCH C Figure 8. Before Refresh Cycle

10 LH2256 NMOS 256K (256K ) Dynamic RAM PAGE MODE CHARACTERISTICS (V CC = 5 V ± 0%, T A = 0 to +70 C) PARAMETER SYMBOL LH LH LH UNIT MIN. MAX. MIN. MAX. MIN. MAX. Page mode cycle time t PC ns precharge time t CP ns NOTE t t AR t CSH t PC t RSH t RCD t t CP t t t CRP t RAH t CPN t ASR t CAC t RAC t OFF t CAC t OFF t CAC t OFF t RCS t RCS t RCS t RCH trch t RRH NOTES:. Row address 2. Column address t RCH Figure 9. Page Mode Read Cycle 2-0

11 NMOS 256K (256K ) Dynamic RAM LH2256 t t AR t CSH t PC t RSH t RCD t t CP t t t CRP t RAH t CPN t ASR V A IH 0 - A 8 V IL t WCH t WCH t WCH t WCR t CWL t CWL t CWL t WP t WP t WP t DH t DH t RWL t DS t DS t DS t DH D IN DATA VALID DATA VALID DATA VALID NOTES:. Row address 2. Column address t DHR Figure 0. Page Mode Write Cycle

12 LH2256 NMOS 256K (256K ) Dynamic RAM PACKAGE DIAGRAMS 6DIP (DIP06-P-0300B) DETAIL [0.262] 6.25 [0.246] 9.50 [0.768] 9.00 [0.748] [0.02] 0.20 [0.008] 0 TO [0.44] 3.25 [0.28] 7.62 [0.300] TYP [0.00] TYP [0.022] 0.36 [0.04] 0.5 [0.020] MIN 4.40 [0.73] 4.00 [0.57] 3.40 [0.34] 3.00 [0.8] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 6DIP 6-pin, 300-mil DIP 6ZIP (ZIP06-P-0325).30 [0.05] 3.05 [0.20] 2.65 [0.04] 6.90 [0.272] 6.50 [0.256] 8.50 [0.335] 7.70 [0.303] [0.02] 0.20 [0.008] 3.60 [0.42] 3.00 [0.8].27 [0.050] TYP [0.024] 0.40 [0.06] 2.54 [0.00] TYP [0.805] 9.95 [0.785] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 6ZIP 6-pin, 325-mil ZIP 2-2

13 NMOS 256K (256K ) Dynamic RAM LH2256 ORDERING INFORMATION LH2256 Device Type X Package - ## Speed Access Time (ns) Blank 6-pin, 300-mil DIP (DIP6-P-300) Z 6-pin, 325-mil ZIP (ZIP6-P-325) NMOS 256K (256K x ) Dynamic RAM Example: LH (NMOS 256K (256K x ) Dynamic RAM, 00 ns, 6-pin, 300-mil DIP, Page Mode)

HM514400B/BL Series HM514400C/CL Series

ADE-203-269A (Z) HM514400B/BL Series HM514400C/CL Series 1,048,576-word 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576-