HB56A1636B/SB-6B/7B/8B

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Norah Eugenia Jordan
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1 16,777,216-word 36-bit High-Density Dynamic RAM Module ADE A(Z) Rev /10/96 Description The HB56A1636 is a 16-Mbit 36 dynamic RAM module, consisting of Mbit DRAMs (HM BS) sealed in an SOJ package. The HB56A1636 enclosed in a 72-pin single in-line package. Therefore, the HB56A1636 makes highdensity mounting possible without surface mount technology. The HB56A1636 provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ on the module board. Features 72-pin single in-line package Lead pitch: 1.27 mm Single 5 V (±5%) supply High speed Access time: t RAC = 60/70/80 ns (max) Access time: t CAC = 15/18/20 ns (max) Low power dissipation Active mode: 15.2/13.3/12.3 W (max) Standby mode (TTL): 378 mw (max) Standby mode (CMOS): 189 mw (max) Fast page mode capability 4,096 refresh cycles: 64 ms 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh TTL compatible

2 Ordering Information Type No. Access time Package Contact pad HB56A1636B-6B 60 ns 72-pin SIP socket type Gold HB56A1636B-7B 70 ns 72-pin SIP socket type Gold HB56A1636B-8B 80 ns 72-pin SIP socket type Gold HB56A1636SB-6B 60 ns 72-pin SIP socket type Solder HB56A1636SB-7B 70 ns 72-pin SIP socket type Solder HB56A1636SB-8B 80 ns 72-pin SIP socket type Solder Pin Arrangement 1Pin 36Pin 37Pin 72Pin 2

3 Pin Arrangement Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 V SS 19 A10 37 DQ17 55 DQ12 2 DQ0 20 DQ4 38 DQ35 56 DQ30 3 DQ18 21 DQ22 39 V SS 57 DQ13 4 DQ1 22 DQ5 40 CAS0 58 DQ31 5 DQ19 23 DQ23 41 CAS2 59 V CC 6 DQ2 24 DQ6 42 CAS3 60 DQ32 7 DQ20 25 DQ24 43 CAS1 61 DQ14 8 DQ3 26 DQ7 44 RAS0 62 DQ33 9 DQ21 27 DQ25 45 NC 63 DQ15 10 V CC 28 A7 46 NC 64 DQ34 11 NC 29 A11 47 WE 65 DQ16 12 A0 30 V CC 48 NC 66 NC 13 A1 31 A8 49 DQ9 67 PD1 14 A2 32 A9 50 DQ27 68 PD2 15 A3 33 NC 51 DQ10 69 PD3 16 A4 34 RAS2 52 DQ28 70 PD4 17 A5 35 DQ26 53 DQ11 71 NC 18 A6 36 DQ8 54 DQ29 72 V SS 3

4 Pin Description Pin Name Function A0 to A11 Address input: A0 to A11 Row address: A0 to A11 Column address: A0 to A11 Refresh address: A0 to A11 DQ0 to DQ35 Data-in/data-out RAS0, RAS2 Row address strobe CAS0 to CAS3 Column address strobe WE Read/write enable V CC Power supply (+5 V) V SS PD1 to PD4 NC Ground Presence detect pin Non-connection Presence Detect Pin Arrangement Pin No. Pin Name 60 ns 70 ns 80 ns 67 PD1 V SS V SS V SS 68 PD2 V SS V SS V SS 69 PD3 NC V SS NC 70 PD4 NC NC V SS 4

5 Block Diagram CAS0 RAS0 CAS2 RAS2 DQ0 D0 DQ18 D18 DQ1 D1 DQ19 D19 DQ7 D7 DQ25 D25 DQ8 D8 DQ26 D26 CAS1 CAS3 DQ9 D9 DQ27 D27 DQ10 D10 DQ28 D28 DQ16 D16 DQ34 D34 DQ17 D17 DQ35 D35 A0 to A11 WE 12 D0 to D35 D0 to D35 * D0 to D35 : HM V CC V SS C0 to C35 D0 to D35 D0 to D35 5

6 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS V T 1.0 to +7.0 V Supply voltage relative to V SS V CC 1.0 to +7.0 V Short circuit output current Iout 50 ma Power dissipation Pt 36 W Operating temperature Topr 0 to +70 C Storage temperature Tstg 55 to +125 C Recommended DC Operating Conditions (Ta = 0 to 70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage V SS V Supply voltage V CC V 1 Input high voltage V IH V 1 Input low voltage V IL V 1 Note: 1. All voltage referenced to V SS. 6

7 DC Characteristics (Ta = 0 to 70 C, V CC = 5 V ± 5%, V SS = 0 V) HB56A1636B/SB-6B/7B/8B 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Test condition Note Operating current I CC ma t RC = min 1, 2 Standby current I CC ma TTL interface RAS, CAS = V IH = High-Z Standby current I CC ma CMOS interface RAS, CAS V CC 0.2 V = High-Z RAS-only refresh current I CC ma t RC = min 2 Standby current I CC ma RAS = V IH CAS = V IL = enable CAS-before-RAS refresh current Fast page mode current I CC ma t RC = min I CC ma t PC = min 1, 3 Input leakage current I LI µa 0 V Vin 7.0 V Output leakage current I LO µa 0 V Vout 7.0 V = disable Output high voltage V OH 2.4 V CC 2.4 V CC 2.4 V CC V High Iout = 5 ma Output low voltage V OL V Low Iout = 4.2 ma Notes: 1. I CC depends on output load condition when the device is selected; I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = V IL. 3. Address can be changed once or less while CAS = V IH. 1 Capacitance (Ta = 25 C, V CC = 5 V ± 5%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) C I1 195 pf 1 Input capacitance (WE) C I2 267 pf 1 Input capacitance (RAS) C I3 146 pf 1 Input capacitance (CAS) C I4 83 pf 1 I/O capacitance (DQ) C I/O 25 pf 1, 2 Notes: 1. Capacitance measured with Boonton Meter or other effective capacitance measuring method. 2. CAS = V IH to disable. 7

8 *1, *2 AC Characteristics (Ta = 0 to 70 C, V CC = 5 V ± 5%, V SS = 0 V) Test Conditions Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output load: 2 TTL gate + C L (100 pf) (Including scope and jig) Read, Write and Refresh Cycles (Common parameters) 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC ns RAS precharge time ns CAS precharge time t CP ns RAS pulse width t RAS ns CAS pulse width t CAS ns Row address setup time t ASR ns Row address hold time t RAH ns Column address setup time t ASC ns Column address hold time t CAH ns RAS to CAS delay time t RCD ns 3 RAS to column address delay time t RAD ns 4 RAS hold time t RSH ns CAS hold time t CSH ns CAS to RAS precharge time t CRP ns CAS delay time from t DZC ns Transition time (rise and fall) t T ns 5 Refresh period (4,096 cycles) t REF ms 8

9 Read Cycle 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC ns 6, 7 Access time from CAS t CAC ns 7, 8, 15 Access time from address t AA ns 7, 9, 15 Read command setup time t RCS ns Read command hold time to CAS t RCH ns 10 Read command hold time to RAS t RRH ns 10 Column address to RAS lead time t RAL ns Column address to CAS lead time t CAL ns CAS to output in low-z t CLZ ns Output data hold time t OH ns Output buffer turn-off time t OFF ns 11 CAS to delay time t CDD ns Write Cycle 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS ns 12 Write command hold time t WCH ns Write command pulse width t WP ns Data-in setup time t DS ns 13 Data-in hold time t DH ns 13 9

10 Refresh Cycle 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR ns CAS hold time (CBR refresh cycle) t CHR ns WE setup time (CBR refresh cycle) t WRP ns WE hold time (CBR refresh cycle) t WRH ns RAS precharge to CAS hold time C ns Fast Page Mode Cycle 60 ns 70 ns 80 ns Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC ns Fast page mode RAS pulse width t RASP ns 14 Access time from CAS precharge t CPA ns 7, 15 RAS hold time from CAS precharge t CPRH ns 10

11 Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by t CAC. 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA. 5. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and V IL (max). 6. Assumes that t RCD t RCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 7. Measured with a load circuit equivalent to 2 TTL loads and 100 pf. 8. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 9. Assumes that t RCD t RCD (max) and t RAD t RAD (max). 10. Either t RCH or t RRH must be satisfied for a read cycles. 11. t OFF (max) defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 12. t WCS is not restrictive operating parameters. It is included in the data sheet as electrical characteristics only; if t WCS t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. 13. These parameters are referenced to CAS leading edge in early write cycles. 14. t RASP defines RAS pulse width in fast page mode cycles. 15. Access time is determined by the longest among t AA or t CAC and t CPA. 11

12 Timing Waveforms Read Cycle t RC t RAS RAS t CSH t CRP t RCD t RSH t T t CAS CAS t RAD t RAL t CAL t ASR t RAH t ASC t CAH Address Row Column t RCS trch t RRH WE t DZC tcdd High-Z t CAC t AA t RAC t CLZ t OFF t OH Note : : H or L (H: V IH (min) Vin V IH (max), L: V IL (min) Vin V IL (max)) : Invalid 12

13 Early Write Cycle t RC t RAS RAS t CSH t CRP t RCD t RSH t T t CAS CAS t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH High-Z <= * t WCS t WCS (min) 13

14 RAS-Only Refresh Cycle t RC t RAS RAS t T t CRP C t CRP CAS t ASR t RAH Address Row t OFF High-Z * WE : H or L 14

15 CAS-Before-RAS Refresh Cycle t RC t RC t RAS t RAS RAS t T C C tcsr t CHR t CRP t CP t CSR t CHR tcp CAS t WRH t WRH t WRP t WRP WE Address t OFF High-Z 15

16 Hidden Refresh Cycle t RAS t RC t RC t RC t RAS t RAS RAS t CRP t RCD t RSH t CHR t T CAS t RAD t RAL t ASR t RAH t ASC t CAH Address Row Column t RCS t WRP t WRP t RRH t WRH t WRH WE t DZC t CDD High-Z t CAC t RAC t AA t CLZ t OFF t OH 16

17 Fast Page Mode Read Cycle t RASP t CPRH RAS t CSH t PC t t RCD RSH t T t CAS t CP t CAS t CP t CAS t CRP CAS t ASR t RAD t RAL t CAL t CAL tcal t RAH t ASC t CAH tasc t CAH t ASC t CAH Address Row Column 1 Column 2 Column 3 t RCS t RCH t RCS t RCS t RRH t RCH t RCH WE t DZC t CDD t DZC t DZC t CDD tcdd High-Z High-Z High-Z t RAC t CPA t CPA t t t taa t OH OH AA t OH AA t CAC t OFF t CAC t OFF t CAC t OFF t CLZ t CLZ t CLZ 1 2 N 17

18 Fast Page Mode Eary Write Cycle t RASP RAS t RCD t CSH t PC t RSH t CRP t T t CAS t CP t CAS t CP t CAS CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH 1 2 N High-Z * t WCS > = t WCS (min.) 18

19 Physical Outline Unit : mm inch 9.10 max 0.35 max R157 R φ max max R1.57 R A typ 0.05 typ Deteil A 2.54 min max max Note : Following the specification of the contact pads. Part No. Contact pad HB56A1636B-XX gold HB56A1636SB-XX solder 19

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