MCU PINS U1-4 OSCIN OSCIN K1 KELVIN_GND L2 OSCOUT L1 TCK TCK KELVIN_GND OSCOUT TCK RTCK TDI TDO TMS TRST A16 TDI TDI A17 TDO TDO C18 TMS TMS
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- Isabella Jacobs
- 5 years ago
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1 Power-Ground on MU MU PINS.V.V P P0 M0 L K K K K J H0 F0 F P P P P P P P N N M M L J H H G G F F F F F F F W U- V V V V V V V V_PLL V_SRM V_SRM V_SRM V 0LSx VP_P V H H H H J J J0 J J K K0 K L L L0 L L M M M M V W W V W W V W OSIN K KELVIN_ L OSOUT L TK TK RTK_ISO TI TI TO TO TRST_ TRST_ OSIN KELVIN_ 0p OSOUT 0p U- OSIN KELVIN_ OSOUT TK RTK TI TO TRST 0LSx PORRST W RST ELK FLTP J FLTP H TEST U ERROR R S Y k MHz RYSTL igikey no: N.V EMU_ISO nerror R ENRV k EMU0_ISO RST_ 0 ELK R 0.V U V OE OE OE OE SNLVPWR Y Y Y Y 00pF nerror Yellow R 0 Yellow RE.V EMU_ontrol R 0 R k.v.v.v R k RST_ 00pF S TEXS INSTRUMENTS MU V//JTG Size ocument Number Rev 0LSx ontrol ard <.0> ate: Wednesday, ugust 0, 0 Sheet of
2 MU PINS R 0 R R R 0.V IN IN IN IN IN IN IN IN0 RMII_RXER IN IN IN IN IN IN0 IN IN IN0 EP EP EQEP ISL_nTZ IS_nTZ RMII_MLK EQEPI EQEP MISPISOMI MISPISIMO EP MISPIS RMII_MIO EQEPS EP MISPILK RMII_TXEN RMII_TX[] RMII_TX[0] P 00nF U-.V ETPWM F R 0 J G lue G W0 F K M M H GIO E GIO V W LINTX LINRX M M H H 0 0 NTX K HET0/ETPWM EQEP V HET/EQEP GIO ETPWM W HET/ETPWM GIO GIO EQEP U HET/EQEP GIO GIO ETPWM HET/ETPWM GIO GIO ETPWM V HET/ETPWM GIO GIO ETPWM W HET/ETPWM GIO GIO ETPWM T HET/ETPWM GIO GIO NHET_0 E HET GIO0 ETPWM V HET/ETPWM GIO0 ntz HET0/TZ GIO/INT/ETPWM ETPWM NHET_ E HET/NHET[] GIO/INT/ETPWM ETPWM ETPWM_GIO RMII_RS_V HET GIO/INT/ETPWM ETPWM N HET/ETPWM GIO/INT NHET_ HET GIO/INT/NHET[] EP N HET/EP 0LSx GIO/INT/EQEPI NHET_ HET GIO/INT EQEPI GIO NHET_ HET GIO0/INT0 GIO0 ETPWM J HET/ETPWM NHET_ HET _SITX ETPWM P HET0/ETPWM _SIRX NHET_ H HET/EMIF_WIT NHET_ HET LINTX NHET_ J HET LINRX RMII_RX[0] P HET NHET_ M HET RMII_RX[] HET NRX NHET_ HET NTX RMII_REFLK K HET NHET_ HET NRX EQEPS HET0/EQEPS NTX NHET_ J HET NRX NRX FRYRX NTX No onnects FRYTX FRYTXEN Unused Pins FRYRX FRYTX U- FRYTXEN EMIFS EMIFS EMIFS EMIFS0 MISPISOMI/EP MISPISIMO/EP MISPIEN/EQEP MISPIS/TZ MISPIS/TZ MISPIS MISPIS0/EQEPI MISPILK/EQEP MISPISIMO F MISPISOMI G MISPIEN/EP MISPIS MISPIS MISPIS/EQEPS MISPIS0/EP MISPILK V W W V V0 V G J G F R F V _RTPT0 ETMT0 R U _RTPT ETMT R T0 _RTPT ETMT J U0 _RTPT ETMT H T _RTPT ETMT G U _RTPT ETMT F U _RTPT ETMT E U _RTPT ETMT E U _RTPT ETMT E U _RTPT ETMT E U _RTPT0 ETMT0 E T _RTPT 0LSx ETMT E V _RTPT ETMT E U- U _RTPT ETMT E T _RTPT ETMT E T _RTPT ETMT E0 SPILK E SPILK P ETMT K SPISIMO SPISIMO P U _RTPEN ETMT L SPISOMI SPISOMI P T _RTPSY ETMT M SPIS EMIF_RS R W _RTPLK ETMT N N EMIF_S R ETMT0 E R EMIF-WIT P L MMT0 ETMT F R R L MMT ETMT G T EMIF_KE L W MMT/MISPIS ETMT K T EMIF_LK K T MMT/MISPIS ETMT L W SPIS0 N SPIS0 ETMT M ETPWM E MMT/MISPIS0/ETPWM ETMT N MMT/MISPIS ETMT P EP H MMT/MISPIEN/EP ETMT R 0LSx ETMT R ETPWM ETPWM ETPWM E H MMT/MISPISIMO ETMT0 R ETMT R MMT0/MISPISIMO R0 R R G MMT/MISPISIMO.k.k.k ETMTRETL R E MMT/MISPISOMI ETMTRELKOUT R0 H G MMT/MISPISOMI ETMTRELKIN R MMT/MISPISOMI TEXS INSTRUMENTS 0 T T T T P N M L K G F E N M L K 0 M K L N EMIF EMIF0 EMIF EMIF EMIF EMIF EMIF EMIF EMIF EMIF EMIF EMIF0 EMIF EMIF EMIF EMIF EMIF EMIF EMIF EMIF EMIF EMIF0 EMIFT EMIFT EMIFT EMIFT EMIFT EMIFT0 EMIFT EMIFT EMIFT EMIFT EMIFT EMIFT EMIFT EMIFT EMIFT EMIFT0 EMIF EMIF0 EMIFQM EMIFQM0 EMIFOE EMIFWE EVT EVTMII_RX_ER/RMII_RX_ER IN/IN IN/IN IN/IN IN/IN IN/IN IN0/IN0 IN/IN IN/IN IN/IN IN/IN IN/IN IN0/IN IN/IN IN/IN IN/IN IN/IN0 IN IN IN IN IN IN IN IN0 W N REFLO V REFHI V P R T T U U W P R R T U U U U V V T R U T V V W MISPILK/MM_T/RMII_TXEN H MISPISIMO0/MM_T/RMII_TX[] J MISPISOMI0/MM_T/RMII_TX[0] J F J F MMEN MMSY MMLK 0LSx P Size ocument Number Rev 0LSx ontrol ard.0 ate: Wednesday, ugust 0, 0 Sheet of
3 U IN0 IN IN IN IN IN IN IN 0 0 P V_ISO RX_ISO _ISO _0 _L H _ - _ GPIO/MLKR/X/EPWM _ GPIO0/MLKR/X/EPWM _ GPIO/SIRX/X/EPWM IN0 IN IN IN IN IN IN IN R0 0_ R0 0_ R 0 NHET_0 ETPWM ETPWM GPIO0/EPWM GPIO/EPWM/EP/MFSR ETPWM ETPWM=NHET00 NHET0=ETPWM ETPWM GPIO/EPWM GPIO/EPWM/EP/MLKR ETPWM ETPWM R 0 NHET_ NHET_ R00 0 ETPWM ETPWM GPIO/EPWM GPIO/EPWM/MFSR/EP ETPWM ETPWM=NHET0 NHET=ETPWM ETPWM GPIO/EPWM/EPWMSYI/EPWMSYO GPIO/EPWM/MLKR/EP ETPWM ETPWM=NHET0 EXTSO V V ETPWM_GIO R0 0 NHET0=ETPWM ETPWM GPIO/EPWM/NTX/SOOn GPIO/EPWM/SITX/EP ETPWM ETPWM=NHET R 0 NHET_ ETPWM ETPWM R 0 GPIO0/EPWM/NRX/SOOn GPIO/EPWM/SIRX/EP NHET_ R 0 EP ETPWM NHET0= ETPWM 0 ETPWMNHET0 ETPWM R 0 GPIO/EP/X/SPISIMO GPIO/EP/X0/SPISOMI 0 EP GIO GIO V GPIO/X GPIO/X GIO GPIO/X V GIO R 0 ISL_nTZ GPIO/TZn/NTX/MX GPIO/TZn/NRX/MR IS_nTZ R 0 GIO GIO0 ntz GIO GPIO_ GPIO/TZn/XHOLn/SIRX/MFSX GPIO/TZn/XHOLn/SITX/MLKX R0 0 GPIO_ GPIO_ GPIO/EP/EQEP/MX GPIO/EP/EQEP/MR GPIO_ V GPIO/EP/EQEPI/MLKX GPIO/EP/EQEPS/MFSX EXTSO V MISPISIMO GPIO/SPISIMO/NTX/TZn GPIO/SPISOMI/NRX/TZn MISPISOMI MISPILK MISPIS R 0 GPIO/SPILK/SITX/NRX GPIO/SPISTE/SIRX/NTX NHET_ EQEP EQEP 0 EQEP EQEP=NHET0 GPIO0/EQEP/MX/NTX GPIO/EQEP/MR/NRX 0 NHET0=EQEPS EQEPS GPIO/EQEPS/MLKX/SITX GPIO/EQEPI/MFSX/SIRX EQEPI EQEPI R 0 NHET_ GIO GPIO/X V V SIRX_ase GPIO/SIRX/XZSn GPIO/SITX/X SITX_ase NRX GPIO0/NRX/X GPIO/NTX/X NTX GIO0 GPIO/S/EPWMSYI /SOOnGPIO/SL/EPWMSYO/SOOn GIO ELK V GPIO/EP/XREY V TI TI_ase TK_ase TK TO TO_ase _ase TRSTn TRSTn_ase 0 EMU EMU0 00 IMM-00 V_ISO TX_ISO _ISO _0 _L _ 0 _H _ - _ GPIO/MFSR/X0/EPWM _ GPIO/MFSR/X/EPWM 0 _ GPIO/SITX/X/EPWM R0 0_ NHET_ NHET_ NHET_ IN IN IN0 IN IN IN IN IN IN0 IN IN IN IN IN IN IN IN IN IN IN0 IN IN IN IN IO IO IO IO TPE00 U IO IO IO IO TPE00 U IO IO IO IO TPE00 U IO IO IO IO TPE00 RN ohm rray RN ohm rray RN ohm rray RN ohm rray IN0 IN IN IN IN IN IN IN IN IN0 IN IN IN IN IN IN IN IN0 IN IN IN IN IN IN R-R0 will be assambled to use NHET rather than the emodules. ENRV SWF SWG GIO0 GIO NHET_ R 0 EP GIO=0 GIO= GPIO_(SIMO) EQEP, EP, HET EP(SIMO), HET GPIO_(SOMI) EP(SOMI), EQEP,HET EP(SOMI), EQEP,HET GPIO_(SLK) EQEPI, EP(HET) EQEP (SLK), EP(HET) GPIO_(SS) EQEPS, EP,HET EQEPS, EQEPI (SS) IMM Pin GIO GIO, EP,HET SW SW SW IS_nTZ GIO0 ntz IN0 IN IN IN SLK SS GIO GPIO_ GPIO_ SLK EQEP GPIO_ GPIO_ SS EQEPI SNTLV_TSSOP U.V S V OE GPIO_ GIO EP 0 EP=SPISOMI EP=SPISIMO EQEPI=SPIS0 EQEP=SPILK ETPWM_GIO riving GIO to only when use this control card with RV0x development kit. So that, the control card can talk the RV 0x through SPI and connect P to IMM Pin Make sure no other pin drives the same net at the same time. X=Y above means that the u multiplexer allows either function X or Y on the pin SW ISL_nTZ These capacitors is for input channel noise. No Pop. 0 IN IN IN IN IN IN IN0 IN NHET=EP EP EP EQEP NHET_ EP NHET_ EQEPS R GPIO_ 0 R GPIO_ 0 R 0 R 0 R GPIO_ 0 R 0 R GPIO_ 0 SLK SOMI SIMO SS TEXS INSTRUMENTS 0 IMM 00 onnector IN IN IN IN Size ocument Number Rev 0LSx ontrol ard <.0> ate: Wednesday, ugust 0, 0 Sheet of
4 V P JP R 0_ ENRV R k.v 0nF SWE R 0 IN0 SPIS0 S SPISIMO Push button digikey #: KNT-N SPISOMI SPILK R0 00 R k nerror 00nF P P P 0 VR VT_SFING ENRV VP SEL_V/ P IGN 0 P VTP SN NRES V IG_OUT V_G/SN S P SI V_SENSE SO /OMP SLK VIO RSTEXT V/ ERROR V 0 NWU VSF VTRK VSIN VSOUT TPS P P + 0uF 00nF 00nF IGN.uF V R 0.uF.V R 00k MRS0T L uh V Q F WHITE R R.k + uf.v EMU_ontrol IN0 0nF.V R 00 R 0. uf ENRV.V + 0uF 00nF 00nF 00nF 00nF 0 00nF 00nF R 0k Simulate IGN Pulse 0nF U T SENSE R 0 R 0k IGN 0 0nF.V R0 0k TL00 V S + 0 0uF 00nF 00nF 00nF 00nF 00nF 00nF 00nF 00nF TEXS INSTRUMENTS POWER Size ocument Number 0LSx ontrol ard Rev ustom.0 ate: Thursday, September 0, 0 Sheet of
5 Ethernet PHY REF_LK RMII_MLK.V.V R 00 R 0 LUE RMII_MIO LE_LINK LE_T.V R.k 0MHz OSI Y OE OUT V SV-0.000MHZ-E-T R R 0 RMII_REFLK 0 REF_LK 0 L.V Ferrite 00nF.V R R.k.k RMII_RXER RMII_RS_V.V RMII_RX[] RMII_RX[0].V R.k 0 U GPIO RX_LK RX_V RS/RS_V RX_ER OL RX_ RX_ RX_ RX_0 IO_ IO_V GPIO IO_ORE_ X X IO_V M MIO 0 _N LE_LINK LE_SPEE P0 TX_LK TX_EN TX_0 TX_ TX_ TX_ POWROWN TK TO TRST# TI LE_T GPIO 0 P T+ T T- R+ T R- L-LE THOE 0 L-LE NOE R-LE NOE R-LE THOE LK_OUT GPIO GPIO GPIO VREF 0 NV N T+ T- _ R+ R- TP R.k T-.V R 0 T+ R 0 R 0 R 0 00nF.V.V.V.V.V 00nF T+ R+ R- T- R+ R 0 R0 0 R.k LE_LINK R.k LE_T R 0 RJ- Jack R- J00NL RMII_TXEN RMII_TX[0] RMII_TX[] R0.k R.k.V + 0uF 00nF 00nF 00nF.V TEXS INSTRUMENTS Ethernet Size ocument Number Rev ustom.0 0LSx ontrol ard ate: Wednesday, ugust 0, 0 Sheet of
6 V_US V_EUG + 0UF 0 00nF U0 VIN EN TPS0 Vout NR 00nF.V_EUG 0UF 0 R0 00 LUE.V_EUG T0 IRLML0 FTI_TI.V_EUG.V_EUG Ferrite ead: LUE R0 00 L0 Ferrite L0 Ferrite.uF 00nF.uF 00nF.V_EUG.V_US.uF 00nF 00nF 00nF 00nF 00nF 00nF 00nF J0 V T(-) T(+) I SHL SHL SHL SHL US--mini-smt igikey no: MINISM00FT-N igikey no: WM.V_EUG R0 0 U0 V R V_US 0k 0 pf 0 pf V_EUG S SK IN OUT XTIN U0 V IO IO TPE00 EES EESK EET R.k Y0 R.V_EUG.V_EUG XTIN XTOUT R k 0k 0 R R 0k 0k VREGIN VREGOUT # REF USM USP EES EESK EET OSI OSO VPHY VPLL U0 US0/TX/TK US/RX/TI US/RTS#/TO US/TS#/ US/TR#/GPIOL0 US/SR#/GPIOL US/#/GPIOL US/RI#/GPIOL VORE VORE VORE 0 US0/TXEN/GPIOH0 US/WRST#/GPIOH US/RST#/GPIOH US/RXLE#/GPIOH US/TXLE#/GPIOH 0 US/-/GPIOH US/-/GPIOH US/-/GPIOH US0/TX/TK US/RX/TI US/RTS#/TO 0 US/TS#/ US/TR#/GPIOL0 US/SR#/GPIOL US/#/GPIOL US/RI#/GPIOL US0/TXEN/GPIOH0 US/WRST#/GPIOH US/RST#/GPIOH US/RXLE#/GPIOH US/TXLE#/GPIOH US/-/GPIOH US/-/GPIOH US/-/GPIOH PWREN# 0 SUSPEN# TEST FTI_TK FTI_TI FTI_TO FTI_ GPIOL0 GPIOL GPIOL GPIOL GPIOH0 GPIOH OE GPIOH FTI_SIRX FTI_SITX PL_TK PL_TI PL_TO PL_ PWREN# SUSPEN#.V_EUG R R R R k k k k SPRE0 SPRE SPRE SPRE V_EUG V_EUG 0 LUE R k 0 LUE R k R k GPIOL EMU0, default pull up to disable the PORRST control. XTOUT 0 FTH MHz RYSTL igikey no: XT-N Manufactor no: ES TR TEXS INSTRUMENTS XS00v - JTG Size ocument Number Rev ustom 0LSx ontrol ard.0 ate: Wednesday, ugust 0, 0 Sheet of
7 .V_EUG SUSPEN# GPIOH OE PWREN# GPIOH GPIOH0 SPRE0 SPRE SPRE SPRE.V SWH JTG_ R.k U0 0 GPIOL GPIOL GPIOL GPIOL0 FTI_ FTI_TO FTI_TI FTI_TK PL_TI PL_ PL_TK SHN_N.V_EUG 0 X_VQ.V_US IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ IO_ VUX IO_ IO_ IO_ IO_ IO_0 IO_ IO_ TI TK IO_ IO_ IO_ V IO_ I_ IO_ IO_ IO_ IO_ 0 IO_ IO_ IO_ IO_ 0 IO_ IO_0 IO_ TO IO_ R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0.V_EUG PL_TO T_SRST T_EMU0 T_EMU T_RTK T_ T_TRST_N T_TI T_IS T_TO R 0 R 0 T_TK JTG_ SITX_ISO SITX_ase LINTX SIRX_ISO SIRX_ase LINRX JTG_ TK_ISO TK_ase TK TRSTn_ISO TRSTn_ase TRST_ SNTLV_TSSOP U.V S V OE TI_ISO TI_ase TI TO_ISO 0 TO_ase TO SNTLV_TSSOP U.V S V OE _ISO 0 _ase 00nF R0 0 PowGood PowGood_INV U OE V Y SNHG.V_EUG PowGood.V_EUG U 00nF V T_ T_TK IN T_TRST_N IN T_TI I IN V OUT OUT OUT OUT EN 0.V _ISO TK_ISO TRSTn_ISO TI_ISO 00nF R R k_ k.v ISO0 R k_.v_eug R0 k FTI_SITX PowGood_INV T_TO T_RTK.V_EUG 00nF U 0 EN OUT OUT OUT OUT V ISO0 IN I IN IN V SITX_ISO TO_ISO RTK_ISO.V 0 00nF RTK_ISO U V Reset TLV0SZR.V FTI_SIRX.V_EUG 00nF T_SRST T_EMU0 T_EMU U V IN IN I IN ISO0 V OUT OUT OUT OUT EN 0.V 00nF P SRST_ISO EMU0_ISO EMU0_ISO EMU_ISO EMU_ISO R SIRX_ISO k_ R k.v TEXS INSTRUMENTS XS00v - JTG Size ocument Number Rev ustom 0LSx ontrol ard <.0> ate: Wednesday, ugust 0, 0 Sheet of
CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2
VUS R V_IN V TO.V SETION.V SI_RX SI_TX 0E R PINOUT HEK MINISM00F- Resettable Fuse F 00m WHITE 00nF U GN EN IN IN TPS PG nc OUT OUT 0k R 0.V 00nF Power_Good MIRO US IS INITE S ON TX RX 0.uF VUS TR RI GN
Note:"DNP" mean the component is not populated by default. Title: Version: Embest. Drawn By: Ambient. sensor Sheet 5 Sheet 6 Sheet 6
Ambient uttons light LEDS sensor Sheet Sheet Sheet Power management oosterpack Connector Sheet RM\TMS0LS Sheet Expand Connector Sheet Sheet Sheet Micro US type XDS00v Sheet Sheet Sheet Note:"" mean the
Quickfilter Development Board, QF4A512 - DK
Quickfilter evelopment oard, QF - K nalog Inputs - U +.V +.V J N hannel J N hannel J N hannel J N hannel U +.V +.V U +.V U +.V Prototyping rea J J Optional +V External Power x Header 0." US onnector U
8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1
isclaimer: IT is providing this schematic for reference purposes only. lthough the schematic was taken from a known working design, it is being provided "as is" without any express or implied warranty
AML7266-H. Feature table. Block Thursday, February 12, 2009 AMLOGIC AML7266-H. Main Chip: Internal: Video: Audio: Interfaces: UART USB HOST RJ45
ON Y Pb Pr is(smk,sk,slrk,s) MP U V V pin con to Mainboard IR MI MI U WM SMK,SK,SLRK MII_(ST) URT JTG con U ML-H SPI FLSH U MXL-G U NN FLSH KFGU Gb SL +.V/. POR LO U +.V RJ RMII Eth PHY U LN US HOST RMII
RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7
Place as close to pins of U as possible. RS HIP 0-00 RS-x emo/evaluation oard: RS-000 Thursday, ecember, 00 Size ocument Number Rev ate: Sheet of P XI P0 P0 P0 P0 P00 PN P0 P0 P0 P0 P0 P0 P0 P0 P XO -XM
REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK
REVISION HISTORY Notes - Unless otherwise noted. Resistances values in Ohms. apacitance values in micrarads (uf). ll 0.uF and 0.0uF capactors are decoupling and should be placed near the I they are shown
NOTE: please place R8 close to J1
Sheets, & /M_RESET PST T T0 +.V_MU R 0K /M_RESET PST T T0 +.V_MU 0.uF NOTE: please place J close to the edge of the P so that the debug cable is clear of the P when attached to the board J 0 0 M Header
Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.
lock iagram Ethernet PoE Level Translators SPI HNSHKE URT tmega U US ISP MHz User button Leds Wi-Fi Module U GPIO Headers micros US US Host MHz lock iagram Size ocument Number Rev Yun ate: Thursday, January,
CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H
V N N V N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_TX N_TX U TX V 00nF N_H R 0 J JUMPER N_H N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H N_L N_L J ON N_RX N_RX V NP R RX Vref VSS N_L Rs 0K MP R N_H
Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header
esign Overview Page Power,Flash,Scard User switch,reset switch. Page Ethernet Page udio Page US Page JTG,OOTSW,LE,Header isclaimer: Schematic's are for reference only. provides no warranty for the use
AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%
K POWER SW JP EXTERNL POWER FUSE 0. uf VT 0 uf R SM or LMMPX-J VIN VOUT U 0.0K % J R.K % 0uF REG_V 0 0.uF REG_V J PV PV_US_TGT V_M0X POWER_SELET R0 0Ohm V to V ENTER POSITIVE.
AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index
XM0-EV-RTLE- SMK0 emo oard Schematic Index Page : Schematic Index (This Page) Page : RTLE GigaPHY MHz rystal RJ- Transformer Page : Host Interface onnector Power Page : History Page : X0 EEPROM Note:.Please
Generated by Foxit PDF Creator Foxit Software For evaluation only.
I_ST I_SLK K_% R K_% R L_0 L_ L_ L_ KEY TON_STHL /F NN_ NN_ P M VS OUTL P OUTR VR MIIN VREF V HOSI LOSI R X pf LOSO.KHZ M_% pf HOSO X pf MHz HOSI 0 pf POWER Generated by Foxit PF reator Foxit Software
PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]
![PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]](/thumbs/87/96361917.jpg "PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]")
V. V. V. V. PI_RX URT LK URT TX PI_RX _TS_EXPHR _RX_EXPHR _RX_EXPHR Uarts URT TS URT RTS URT TX URT RX PS LOK PS T PS LOK PS T URT TX URT RX URT TX URT RX V. V. Ethernet ETH RX[0:] ETH RXV ETH RXER ETH
Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz
V V Way type onnector US Type onnector x.v.v Regulators Headers for all pins sorted by pin no. (unpopulated) Prototyping area with power and GNs (unpopulated) RS Transceiver US to Serial onverter Expansion
Block Diagram SGTL5000 PG. 3. Power PG. 8. Communication PG.6. I2S Signals PG.7. Analog Inputs PG.4. Analog Outputs PG.5.
lock iagram I R Select I/SPI Mode Select MLK Source ommunication PG. US to I/SPI IS Signals PG. nalog Inputs PG. IS Interface Line-In / Microphone nalog Outputs PG. Headphone SGTL PG. igital Header P PSI
XO2 DPHY RX Resistor Networks
PHY_0_P_RX PHY_0_N_RX [] [] R R LP_0_P_RX HS_0_P_RX HS_0_N_RX LP_0_N_RX PHY_LK0_P_RX PHY_LK0_N_RX PHY_LK_P_RX PHY_LK_N_RX [] [] [] [] R R6 R8 R0 LP_LK0_P_RX HS_LK0_P_RX HS_LK0_N_RX LP_LK0_N_RX LP_LK_P_RX
LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3
MU THERMISTOR- MU LI_RX LI_TX LI_RX LI_TX MX_TX MX_RX MX_/RE MX_E MX_TX MX_RX MX_/RE MX_E MX_LI +.V_MU R 0K R 0K R R R R LE_POWER_STGE - Out GN J LE- -V LE Power Stage LE_POWER_STGE - Out GN J LE- -V LE
AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115
PL ENOER OUNTER / PWM MOTOR ONTROL / GLUE LOGI PL YPSS PITORS LE0 LE LE LE ESTOP_U ESTOP_IRQ _USY _IN _OUT _/S _/S _OUT _IN _SLK 0.uF +.V 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF P0.[0:] [0:] 0 P0. P0. P0. P0.
J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET
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Table of ontents Title Page Notes Rev X escription Original Release Revisions ate Nov--0 pproved Production Release ec--0 Production Release Feb--0 Microcontroller Solutions Group 0 William annon rive
ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B
IS_IRQ V._0._0._0 O NOT IS_IRQ R K_0._0.0_0 J J.0_0 0 RV_RESET V RV_RESET V TP J IS TEST._0 TP V X [0..] [0..] GN GN -I/O H K RESRV V 0 IRQ V -V REQ -V U 0WS 0 0 V 0 -IO_HRY._0 GN -I/O H RY 0 -SMEMW EN
ADMtek Incorporated Title EASY 5120P-ATA Size Document Number Rev Top Schematics 1.1.2
_PE_TQFP _PEEL_G LI- - RJ- connectors ( for FX ) P - RJ- connectors ( for FXO ) V V IT_P RELY FXO IO IO IO IO P N IT_P FXO RELY P V N P V N IT IL IT IT_P RELY P N FXO P N IT IL IO IT IO IO VM IO _LI-_PE_TQFP
+12V R16 100K +12V R17 100K R19 R18 100K 100K AVPP BVPP C21. C20 0.1uF. 0.1uF NOTES:
+V +V R 00K U S S G G SI.V +V V _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 R0 00K R 00K + 0uF _VPPEN _VPPEN0 _VEN _VEN0 _VPPEN _VPPEN0 _VEN _VEN0 V 0.uF U VIN VPPIN VPP0 VPP V0 V VPP0 VPP V0 V
ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board
ZRMZN0000KITG rimzon evelopment oard Kit PUG000-0 Product User Guide Introduction Zilog s ZRMZN0000KITG rimzon evelopment oard Kit is designed for use as a target with the rimzon In-ircuit Emulator (ZRMZNIE0ZEMG).
C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.
Size FSM No. WG No. Rev of 9 Galen Street Floor M 0 US MP0EMO Schematic -- MU and Symbol V V P P P P P 9 P0 0 P P P P0 VE V REFYP V P PK P P P 9 P 0 P0 P P P V P P P P9 P P P0 P P 9 P 0 P P P9 P P P P
PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.
R SPIF output Power LO R SPIF input x Flash POR PWM LE x R* Lightning() P x pin Type connector US pin For Lightning & P T QFN RE PLY H Sel T PLY x PM Ext. MU H Sel T RE x S NE OP R* Size ocument
Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09
Table of ontents Notes F & PL MRM, S & SFLSH OPTIONL PORT Rev X0 escription onvert into FSL template Revisions X ll parts FL //0 X Replaced U with the correct part //0 X X Replaced some components with
CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10
I U N R 00K RSIN* RST S N.0u Y LK TP RP K L TP USY INT0 INT RISMINT P.0 P. P. P. P. P. P. RY OL RX0 TX0 T P.0 P. P. P. S* S* S* S* RROR* SLK U LKIN LKOUT LKOUT LKIN LKOUT OSOUT 0 OSOUT L L RSIN* L 0 0
DB30 Top Level DB30 - Daughter Board Spartan3
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3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)
NXP VKIT-SZV Table of ontents 0 LOK IGRM N NOTS 0 I/O Headers 0 Power/MU 0 Peripherals 0 US/OSM Revisions Rev escription esigner ate X Initial raft 00 Release 0/0/ X hanged MU to SZV 0// U T I O N : This
ALEX +12VBUS PTC 1A J17 PTT U1B. 126 IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR. IO_VB1N1_9/DIFFIO_L7p/DQS2L/CQ3L/CDPCLK0 RUP3
F PT VUS J J HEER X V_LEX V LEX LEX_SPI_SO LEX_SPI_SO R R LEX_SPI_SK LEX_SPI_SK LEX_SPI_RX_LO LEX_SPI_RX_LO R LEX_SPI_TX_LO LEX_SPI_TX_LO R FW_PWR REV_PWR 0 LEX HR 0P LEX J HR P R PWR IN THRU FW_PWR REV_PWR
HOSCO HOSCI AS M AS M C1 18P C2 18P C1 18P C2 18P GND VCC3 GPIOK7 R82 R82 10K A20 10K. #OffHook. FmHook #TRANSLED. VxBP 0.1U 0.
0 #E0 GPIOK #MWR #MR #FWE HOSI KEYI0 GPIO0 HOSO V V VREFI KEYI GPIO GPIO_ V KEYO GPIO #E OUTR MIIN VMI GPIO_0 #LON V #HOL 0 0 #E KEYO GPIO 0 KEYO0 GPIO GPIO_ GPIO_0 #MR #MWR V V V V TSEL #E #E0 V HOSI
FTDI_SPI_SCLK FTDI_SPI_MOSI FTDI_SPI_CS FTDI_SPI_MISO FTDI_SPI_SCLK FTDI_SPI_MOSI FTDI_SPI_MISO FTDI_SPI_CS FTDI_GPIO2 3V3_USB FTDI_SPI_SCLK
IOLTION RRIER P POWER-OMIN NI NI IO-LINK POWER-OMIN NI HEET OF MXREFE MXREFE# //..K U MXTT+.UF FTHQ FTI_PI_MIO R.UF LE ML-PPT FT_M FT_P K VV MHZ U UF VU K V_U FTI_PI_MIO FTI_PI_ FTI_PI_MOI
FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved
Table of ontents Title lock iagram KLZ MU OpenS INTERFE I/O Headers and Power Supply Revisions Rev escription ate pproved X Initial draft July, Release July, J, J, J, J, J, J, J, J, J, T, TP and TP Populate
core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103
core Tiny0.sch M000 M000-etc.sch -etc.sch US HU US-HU.sch Tiny0SK 0 M_ VV V V V V V V V V V VN VSYN VLK VUS OTGI OTGM OTGP IN0 S_LK S_n S_T0 S_T OUT0 INT INT INT RST ( 红色 ) Tiny0 Tiny0 P Power Supply S
FUNCTION. Write/Read RAM: Access to PRAM, CRAM, OFFRAM and Registers Digital Audio Interface - Test pin header. Regulator 1.2V.
[K-] K- K Evaluation oard Rev.0 GENERL ESRIPTION The K- is an evaluation kit for the K; a digital signal processor (SP) with channels digital data interface. It realizes an easy evaluation of the audio
3.3V_MCU D N5 D N2 BAV99 D N4 BAV99 D N13 3 BAV99. ESD solution 0.01U TP1 TP2 R4 75 R3 75 R5 75 TP3 TP4 TP6 TP8 R+ G+ B+ R 35 TP11. A-detect C 77 0.
.V_MU.V_MU N V0LT P V N V N V N V N V 0.0U ES solution 0 0.0U J 0.0U J 0.0U J PV TP 0.U U 0 V WP SL VSS S T0 R 0 0 R R.K.K _WP_ R.K SU_SL SU_S SU_S R.V TP TP TP TP0 G J 0 00 TP TP TP TP TP TP R R R R R+
DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2
SEGMENT LE ISPLY R MUX MUX MUX MUX R nf SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ U R xt P P P P P P P P MX MX ss SL S P P P P P P P P nf S SEG_SL SEG_S SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_ SEG_I_SL_