Beyond-CMOS Device Concepts Enabled by 2D Materials

Transcription

1 Beyond-CMOS Device Concepts Enabled by 2D Materials Working Dinner Remarks at NSF US EU Workshop on 2D Materials April 23, 2015 Thomas N Theis Executive Director SRC Nanoelectronics Research Initiative thomas.theis@src.org

2 Topics Why semiconductor manufacturers are investing in beyond-cmos device research NRI and STARnet private-public partnerships funding university research Some new device concepts enabled by 2D materials. 2

3 Computer clock frequencies have been stagnant since Transistor Count (still growing) Clock Frequency (flat since 2003) Power (flat since 2003) Architectural Innovation (ILP) (also flagging!) 3

4 Energy The FET has reached its voltage scaling limit. For charge transport controlled by thermal emission over a barrier, the leakage current is an exponential function of the voltage swing; I ~ exp[-y s (e/kt)] This determines the maximum nonlinearity of the switch, which determines the minimum allowable voltage swing, which determines the minimum power dissipation. (Active power ~ V 2.) Log Current I on Sub-threshold Slope 0 I off V dd Voltage distance With voltage swing already reduced to ~ 1V, The FET is close to its fundamental voltage limit for operation at ambient temperatures.

5 Briefly summarizing the last 10 years To keep areal power density and total power within economically acceptable limits, industry froze clock speed and slowed the deployment of multiple cores. To escape this new status quo, we ve begun to explore devices with switching mechanisms that are fundamentally different from that of the conventional FET, and architectures than are fundamentally different from the von Neumann architecture. 5

6 University research funded by industry and government in recent years has given us a broader picture of what is possible. 6

7 The Nanoelectronics Research Initiative Founded in 2005, NRI is a consortium of leading semiconductor companies (IBM, Intel, Micron, and Texas Instruments) working with the National Science Foundation (NSF) and the National Institute of Standards and Technology (NIST) to collaboratively fund university research. Three multidisciplinary, multi-university research centers Twelve Nanoelectronics for Beyond 2020 (NEB2020) projects NRI s Mission: Demonstrate non-conventional, low-energy technologies for computation which can outperform CMOS on critical applications in ten years and beyond. 7

8 NRI Research Centers In Partnership with NIST SRC Executive Director: Thomas N. Theis 6 Universities CNFD Evgeny Tsymbal, Director The mission of CNFD is to develop low-energy memory and logic devices based on materials, structures, and phenomena non-traditional for existing technologies, such as magnetoelectricity, ferroelectricity, and spin dynamics, to advance the information technology beyond current limits. 8 Universities INDEX Michael Liehr, Executive Director The mission of INDEX is to discover and demonstrate nanoscale computing devices to extend Moore s law beyond CMOS limits, organized around spin and graphene p-n junction logic devices and implemented in an advanced semiconducting fabrication facility. 7 Universities SWAN Sanjay Banerjee, Director The South West Academy for Nanoelectronics seeks to develop ultra-low power transistors based on novel single particle and collective tunneling effects in 2D materials such as graphene and transition metal dichalcogenides, as well as magnetoelectric switching on topological insulators. 8

9 NEB2020 Projects Co-funding 12 Projects at 12 NSF Centers Pittsburgh MIT UC-Riverside Drexel Virginia Commonwealth UC-Riverside Cornell Notre Dame Minnesota Notre Dame Columbia UC-Santa Barbara Scalable Sensing, Storage and Computation with a Rewritable Oxide Nanoelectronics Platform Integrated Biological and Electronic Computation at the Nanoscale Developing a Graphene Spin Computer: Materials, Nano-Devices, Modeling, and Circuits Meta-Capacitance and Spatially Periodic Electronic Excitation Devices (MC-SPEEDs) Hybrid Spintronics and Straintronics: Technology for Ultra-Low Energy Computing and Signal Processing Beyond 2020 Charge-Density-Wave Computational Fabric: New State Variables and Alternative Material Implementation Ultimate Electronic Device Scaling Using Structurally Precise Graphene Nanoribbons Nanoelectronics with Mixed-valence Molecular QCA Scalable Perpendicular All-Spin Non-Volatile Logic Devices and Circuits with Hybrid Interconnection Physics-Inspired Non-Boolean Computation based on Spatial- Temporal Wave Excitations Novel Quantum Switches Using Heterogeneous Atomically Layered Nanostructures Superlattice-FETs, Gamma-L-FETs, and Tunnel-FETs: Materials, Devices and Circuits for Fast Ultra-Lower-Power ICs

10 A Fruitful Partnership with NSF : Annual partnership for joint funding of projects at NSF Nanoscience Centers (NSECs/MRSECs/NCN) 2011: Launched 12 NRI-NSF NEB2020 projects. NRI-NSF exploratory programs are feeding the more-focused center programs in NRI and STARnet. Prof. Evgeny Tsymbal, funded through former MRSEC grant, now Director, NRI CNFD center. Prof. Jian-Ping Wang, funded through NEB2020 since 2012, now Director, STARnet C-SPIN center. 10

11 Growing Research Investment Since 2013, NRI has been joined in the focused exploration of beyond-cmos devices, by the former Focus Center Research Program, completely refreshed as STARnet. Jointly funded by Globalfoundries, IBM, Intel, Micron, Raytheon, TI, United Technologies, and DARPA. Funding six multidisciplinary, multi-university centers 11

12 STARnet Research Centers In Partnership with DARPA 12 SRC Executive Director: Gilroy Vandentop Beyond-CMOS Devices FAME Jane Pei-Chen Chang, Director The mission of FAME is to create and investigate new nonconventional atomic scale engineered materials and structures of multi-function oxides, metals and semiconductors to accelerate innovations in analog, logic and memory devices for revolutionary impact on the semiconductor and defense industries. New Architectures 16 Universities 10 Universities TerraSwarm Edward A. Lee, Director The TerraSwarm Research Center aims to enable the simple, reliable, and secure deployment of a multiplicity of advanced distributed sense controlactuate applications on shared, massively distributed, heterogeneous, and mostly uncoordinated swarm platforms through an open and universal systems architecture. Applied Materials Novellus C-SPIN Jian-Ping Wang, Director The Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN) seeks to overcome barriers to realizing practical spin-based memory and logic technology by assembling experts in magnetic materials, spin transport, novel spin-transport materials, spintronic devices, circuits, and novel architectures. LEAST Alan Seabaugh, Director 14 Universities 10 Universities The Center for Low Energy Systems Technology (LEAST) explores the physics of new materials and devices to enable more energy-efficient integrated circuits and systems. SONIC Naresh Shanbhag, Director SONIC will be guided by the following mission: To enable equivalent scaling in beyond-cmos nanoscale fabrics by embracing their statistical attributes within statistical-inference-based applications, architectures, and circuits, to achieve unprecedented levels of robustness and energy efficiency. C-FAR Todd Austin, Director 8 Universities 15 Universities The center's research agenda is guided by three initial technical vectors, whose intersections will help realize non-conventional architectures that address these pressing challenges: data-centric architectures, novel architectures based on emerging technologies, and beyond homogenous parallelism.

13 What are the prospects for these devices? How can we compare them to each other and to CMOS? 13

14 NRI Device Performance Benchmarking Goals: Enable concise communication of research outcomes. Focus researcher s attention on key technical challenges. Spark invention. Practices and methodology developed across four NRI centers by university PIs led by K. Bernstein K. Bernstein et al., Proc. IEEE 98, 2169 (2010). Comprehensive assessments with uniform engineering assumptions applied to all devices, led by I. Young and D. Nikonov D.E. Nikonov and I.A. Young, IEEE IEDM, pp , Dec. 2012; Proc. IEEE, vol. 101, no. 12, pp , Dec. 2013; IEEE J. Exploratory Sold-State Computational Devices and Circuits, DOI /JXCDC , to be published. 14

15 Benchmarking Example: Energy vs. Delay for 32 Bit Adder Electronic GpnJ SpinFET CMOS HP HJTFET gnrtfet IIIvTFET Delay, ps Spin torque CMOS LP SWD ASLD NML Magnetoelectric STMG STTtriad CMOS ref Electronic Spintronic Ferroelectric Orbitronic Straintronic D. Nikonov and I. Young, IEEE D. Nikonov D. J. Nikonov Exploratory and I.Young, Solid- State IEEE and Computational J. Exp. I.Young, Solid-State Devices Computational Proc. and IEDM, Circuits, Devices DOI and Circuits, to be /JXCDC , published Dec to be published.

16 Benchmarking Example: Energy vs. Delay for 32 Bit Adder (2012 results) Electronic GpnJ SpinFET CMOS HP HJTFET gnrtfet IIIvTFET Delay, ps Spin torque CMOS LP SWD ASLD NML Magnetoelectric STMG STTtriad CMOS ref Electronic Spintronic Ferroelectric Orbitronic Straintronic D. Nikonov and I. Young, IEEE D. Nikonov D. J. Nikonov Exploratory and I.Young, Solid- State IEEE and Computational J. Exp. I.Young, Solid-State Devices Computational Proc. and IEDM, Circuits, Devices DOI and Circuits, to be /JXCDC , published Dec to be published.

17 Benchmarking Example: Energy vs. Delay for 32 Bit Adder (2014 results) CMOS ref Electronic Spintronic Ferroelectric Orbitronic Straintronic Delay, ps D. Nikonov and I. Young, IEEE J. Exploratory Solid- State Computational Devices and Circuits, DOI /JXCDC , to be published.

18 Takeaways from Comparison As device models improve, estimates of device attributes tend to become more conservative (and more accurate). While no clear winner has emerged, the number of device concepts benchmarked as competitive with CMOS has increased. New device concepts continue to emerge, suggesting that more (perhaps many more) are yet to be invented. 18

19 The Band-to-Band Tunnel-FET Operating principle of a tunnel field-effect transistor, after Appenzeller: Bands are crossed in the on state and uncrossed by the gate voltage in the off state. 19

20 TFET Performance Prediction (100x performance advantage at low voltage) I-V curves for nanowire resonant TFET, heterojunction TFET, and MOSFET; all at Lg = 9 nm, VDD = 0.27 V Heterojunction TFET Scaling and Resonant-TFET for Steep Subthreshold Slope at sub-9nm Gate-Length, IEDM 2013, U. Avci and I. Young (Intel Corp.) 20

21 The TFET concept is still rapidly evolving. 2D materials and device structures Schematic representation of various topologies of TFETs, from Debdeep Jena, Proceedings of the IEEE, Vol. 101, No. 7, p July

22 Can a low-voltage device be fast? 100x faster than CMOS at 0.27V is still slow! Newer low-voltage device concepts, now being explored, may enable faster devices, perhaps ultimately exceeding what is possible with the silicon FET. TFETS based on two-dimensional (2D) materials Graphene p-n Junction Device (NRI INDEX center) R. Sajjad and A. Ghosh, arxiv: (2013) Piezoelectronic Transistor (DARPA Mesodynamics) D.M. Newns, et al., J. Appl. Phys. 111, (2012) and more 22

23 Graphene p-n Junction (GPNJ) Device A new steep slope device Gate engineering to orthogonalize transmissions and turn OFF graphene 1. Mobility unaffected 2. High ON current 3. High ON-OFF ratio with steep change in current Redwan Sajjad and Avik Ghosh, ACS Nano, Vol. 7, No. 11, pp , 2013

24 Another Example: IBM s Piezotronic Transistor (PET) Mechanical Clamp (High-Yield- Strength Material) Operating Principle: A voltage, V g placed across a piezoelectric (PE) expands the film. In a mechanically clamped structure, the resulting pressure drives an insulator metal transition in a piezoresistive (PR) film, allowing a current to flow. The area ratio a PR /A PE << 1 steps up the pressure in the PR. D.M. Newns et al., J. Appl. Phys. 111, (2012) 24

25 How will 2D materials impact nanoelectronics? Ultra-thin channels for otherwise conventional FETs? Probably not for high performance devices. Computational modeling by various groups suggests at best a limited benefit. Minimum channel length will be limited more by insulator thickness than by channel thickness. Application in flexible electronics, sensors, etc. seems more likely. Enabling new device concepts? Perhaps. A steep slope device with FET-like drive current at ~0.1 V supply would be truly revolutionary! 25

26 Conclusion Please continue to explore the fundamental materials science, and the many new device structures and concepts made possible by 2D materials. But for real impact, we ll need scalable, self-limiting, and selective processes for growth of single crystals and aligned heterostructures. patterning processes for nm-scale lateral features vastly improved control of point defects and more 26

27 Thanks for your attention!