EC-GATE-2015 PAPER-01 General Aptitude Q. No. 1 5 Carry One Mark Each

Size: px
Start display at page:

Download "EC-GATE-2015 PAPER-01 General Aptitude Q. No. 1 5 Carry One Mark Each"

Transcription

1 EC-GATE-5 PAPE- General Aptitude Q. No. 5 Carry One Mark Each. Choose the word most similar in meaning to the given word: Educe (A) Exert (B) Educate (C) Extract (D) Extend (C). If log x (5/7) = -/, then the value of x is (A) 4/5 (B) 5/4 (C) -5/49 (D) -49/5 (A) x x x a b a b. Operators, and aredefined by : a b ;a b ;a b ab. a b a b Find the value (A) - (B) - (C) (D) (C) (666)(66 6) Choose the most appropriate word from the options given below to complete the following sentence. The principal presented the chief guest with a, as token of appreciation. (A) momento (B) memento (C) momentum (D) moment (B) 5. Choose the appropriate word/phrase, out of the four options given below, to complete the following sentence: Frogs. (A) Croak (B) oar (C) Hiss (D) Patter (A) Frogs make croak sound. written permission.

2 EC-GATE-5 PAPE- Q. No. 6 Carry Two Marks Each 6. A cube of side units is formed using a set of smaller cubes of side unit. Find the proportion of the number of faces of the smaller cubes visible to those which are NOT visible. (A) : 4 (B) : (C) : (D) : (C) Number of faces per cube = 6 Total number of cubes = 9 = 7 Total number of faces = 7 6 = 6 Total number of non visible faces = 6-54 = 8 Numberof visible faces 54 Numberof non visible faces 8 7. Fill in the missing value Middle number is the average of the numbers on both sides. Average of 6 and 4 is 5 Average of (7+4) and (+) is 7 written permission.

3 EC-GATE-5 PAPE- Average of (+9+) and (++) is 8 Average of (4+) and (+) is 5 Therefore, Average of () and () is 8. Humpty Dumpty sits on a wall every day while having lunch. The wall sometimes breaks. A person sitting on the wall falls if the wall breaks. Which one of the statements below is logically valid and can be inferred from the above sentences? (A) Humpty Dumpty always falls while having lunch (B) Humpty Dumpty does not fall sometimes while having lunch (C) Humpty Dumpty never falls during dinner (D) When Humpty Dumpty does not sit on the wall, the wall does not break (B) 9. The following question presents a sentence, part of which is underlined. Beneath the sentence you find four ways of phrasing the underline part. Following the requirements of the standard written English, select the answer that produces the most effective sentence. Tuberculosis, together with its effects, ranks one of the leading causes of death in India. (A) ranks as one of the leading causes of death (B) rank as one of the leading causes of death (C) has the rank of one of the leading causes of death (D) are one of the leading causes of death (A). ead the following paragraph and choose the correct statement. Climate change has reduced human security and threatened human well being. An ignored reality of human progress is that human security largely depends upon environmental security. But on the contrary, human progress seems contradictory to environmental security. To keep up both at the required level is a challenge to be addressed by one and all. One of the ways to curb the climate change may be suitable scientific innovations, while the other may be the Gandhian perspective on small scale progress with focus on sustainability. (A) Human progress and security are positively associated with environmental security. (B) Human progress is contradictory to environmental security. (C) Human security is contradictory to environmental security. (D) Human progress depends upon environmental security. (B) written permission.

4 EC-GATE-5 PAPE- Electronics and Communication Engineering Q. No. 5 Carry One Mark Each. A region of negative differential resistance is observed in the current voltage characteristics of a silicon PN junction if (A) Both the P-region and the N-region are heavily doped (B) The N-region is heavily doped compared to the P-region (C) The P-region is heavily doped compared to the N-region (D) An intrinsic silicon region is inserted between the P-region and the N-region (A). A silicon sample is uniformly doped with donor type impurities with a concentration of 6 / cm. The electron and hole mobilities in the sample are cm / V s and 4cm / V s The charge of an electron is..5 P N q N D n cm respectively. Assume complete ionization of impurities. The resistivity of the sample in cm 9.6 C.. A unity negative feedback system has the open-loop transfer function Gs K s s s The value of the gain K (>) at which the root locus crosses the imaginary axis is. k C.Eis s s s s 4s s k By using outh Table, s row should be zero. For poles to be on imaginary axis k ; k should be Suppose A and B are two independent events with probabilities P A and P B. Let A and B be their complements. Which one of the following statements is FALSE? (A) PA B PAPB (B) PA \ B PA (C) PA B PA PB (D) PA B PAPB (C) We know that A and B are independent then P(A B) = P(A) P(B) written permission. 4 is.

5 EC-GATE-5 PAPE- A and B are independent then P(A/B) = P(A) and P(B/A) = P(B) Also if A and B are independent then AandB are also independent i.e., PA B PAPB (A), (B), (D) are correct (C) is false Since P(A B) = P(A)+P(B)-P(A B) = P(A)+P(B)-P(A)P(B) 5. The waveform of a periodic signal x(t) is shown in the figure. xt 4 4 t A signal g(t) is defined by. g t t x. The average power of g(t) is x(t) lim t dt Power of T 9t 9. Watts 6. In the network shown in the figure, all resistors are identical with. The resistance ab in of the network is. a ab b written permission. 5

6 EC-GATE-5 PAPE- eq By bridge condition eq eq 7. Consider a system of linear equations: x y z x y 4z and x 4y 6z k. The value of k for which the system has infinitely many solutions is. x-y+z = - x-y+4z = -x+4y-6z = k Augmented matrix A B K, K The system will have infinitely many solutions if p(a/b) = p(a) = r < number of variables k- = k = written permission. 6

7 EC-GATE-5 PAPE The polar plot of the transfer function (A) first quadrant (C) third quadrant Gs (A) s s Put s j j G j j, M, M s G s for s (B) second quadrant (D) fourth quadrant will be in the j So, zero is nearer to imaginary axis. Hence plot will move clockwise direction. It is first quadrant. 9. Let z x iy be a complex variable. Consider that contour integration is performed along the unit circle in anticlockwise direction. Which one of the following statements is NOT TUE? z (A) The residue of at z is / z (B) (C) z dz C dz i C z (D) z (complex conjugate of z) is an analytical function f z (D) z x iy u x,v y u and v x x written permission. 7

8 EC-GATE-5 PAPE- u and v y x y y u v i.e., C equations not satisfied z is not analytic (A) z = is a simple pole z z z esidue at z is limz. lim z z z z z (B) Since z is analytic everywhere Using Cauchy s integral theorem, C z dz y. Consider the signal st mtcos f t mˆ t f t where mˆ t denotes the Hilbert c transform of m(t) and the bandwidth of m(t) is very small compared to f c. The signal s(t) is a (A) high-pass signal (B) low-pass signal (C) band-pass signal (D) double sideband suppressed carrier signal (C) Given s(t) is the equation for single side band modulation (lower side band). Thus it is a Band pass signal.. For the circuit with ideal diodes shown in the figure, the shape of the output v out for the in given sine wave input v will be c.5t T in out (A).5T T (B).5T T (C).5T T (D).5T T (C) written permission. 8

9 EC-GATE-5 PAPE- The circuit can be re drawn as a d D V o b D D c During positive pulse, both diodes are forward biased. So output pulse of +ve polarity is produced. As polarity at d and c is given opposite to input terminals, hence +ve pulse is inverted. During negative pulse, both diodes are reverse biased. So, V = V. The result of the convolution xtt t is (A) xt t (B) xt t (C) xt t (D) xt t (D) x( t)* t t x( t)* (t t ) x t t t x t t. The value of p such that the vector. is an eigenvector of the matrix 4 p 4 4 is 7 4 AX X P 4 4 P 7 6 P 7 and 6 i.e., Equation gives P 7 4 P 7 written permission. 9

10 EC-GATE-5 PAPE In the given circuit, the values of V and V respectively are 4 V I I 5A 4 4 V (A) 5V, 5V (B) V, V (C) 5V, 5V (D) V, V (A) By nodal analysis 5 I I I 4I 5 5 I A 4 V 4I 5volts V 4(5) V V 5 volts 5. In an 885 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively (A) B and F (B) A and F (C) H and F (D) A and C (B) In an 885 microprocessor, after performing the addition, result is stored in accumulator and if any carry (overflow bit) is generated it updates flags. 6. Negative feedback in a closed-loop control system DOES NOT (A) reduce the overall gain (B) reduce bandwidth (C) improve disturbance rejection (D) reduce sensitivity to parameter variation (B) Negative feedback in a closed loop (i) Increases bandwidth (ii) educes gain (iii) Improve distance rejection written permission.

11 EC-GATE-5 PAPE A 6 Kb (=6,84 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is. 7 Generally the structure of a memory chip = Number of ow Number of column = M N The number of address line required for row decoder is n where M = n or n = log M As per information given in question : M = N So M N = M M = M = 6k = 4 M = 4 M = 8 n = log 8 = 7 8. A function f (x) x x is defined in the closed interval [-, ]. The value of x, in the open interval (-, ) for which the mean value theorem is satisfied, is (A) -/ (B) -/ (C) / (D) / (B) By Lagrange s mean value theorem f f f ' x -x+x = x -x- = So x =, -/ x= -/ only lies in (-,) 9. The electric field component of a plane wave traveling in a lossless dielectric medium is 8 z given by Ez,t aˆ y cos t V/ m. The wavelength (in m) for the wave is z E z, t cos t a m y written permission.

12 EC-GATE-5 PAPE- In the circuit shown, the switch SW is thrown from position A to position B at time t =. The energy in J taken from the V source to charge the. F capacitor from V to V is V B SW A.F t (A). (B).45 (C).9 (D) (C) So the capacitor in initially uncharged i.e. V C () = The capacitor will be charged to supply voltage V when the switch is in position B for time. So we need to find capacitor voltage c Vc t Vc V c Vc e e t 6 C. sec i dvc C dt d. e dt.. e e 6 t t t t So instantaneous power of source = V(t)i(t)..9 P t.e e t t E Pd t.9 e t dt.9 t.9 e 6.9.9J written permission.

13 EC-GATE-5 PAPE- In the circuit shown below, the Zener diode is ideal and the Zener voltage is 6V. The output voltage V (in volts) is. k V k V 5 Zener is not Breakdown Hence Vo 5V. Consider a four bit D to A converter. The analog value corresponding to digital signals of values and are V and.65v respectively. The analog value (in Volts) corresponding to the digital signal is..975 Analog output = [esolution] [Decimal equivalent of Binary] Ana log output In the circuit shown, at resonance, the amplitude of the sinusoidal voltage (in Volts) across the capacitor is. 4.mH cost Volts F 5 VC QV 9 L L Q.5 C 4 V C = 5-9 V C = 5V written permission.

14 EC-GATE-5 PAPE- 4 A sinusoidal signal of khz frequency is applied to a delta modulator. The sampling rate and step-size of the delta modulator are, samples per second and.v, respectively. To prevent slope overload, the maximum amplitude of the sinusoidal signal (in Volts) is (A) (A) To avoid slope overload, d.t s x(t) dt m max x(t) E sin f t m (B) (C) (D) d x(t) dt max Em E. f., E.. m m m 5. Consider a straight, infinitely long, current carrying conductor lying on the z-axis. Which one of the following plots (in linear scale) qualitatively represents the dependence of H on r, where H is the magnitude of the azimuthal component of magnetic field outside the conductor and r is the radial distance from the conductor? A B H H r r C D H H r (C) H I r r is the distance from current element. H r r written permission. 4

15 EC-GATE-5 PAPE- Q. No carry Two Marks Each 6. The input X to the Binary Symmetric Channel (BSC) shown in the figure is with probability.8. The cross-over probability is /7. If the received bit Y =, the conditional probability that was transmitted is. P[X ]. X 67 Y 7 7 P[X ] X P x. / 7 67 Y P x.8 / 7 6 / 7 P y / x P x Px / y P{y } Py / x 7 P{x }.8 6 P{y } Px / y The transmitted signal in a GSM system is of khz bandwidth and 8 users share a common bandwidth using TDMA. If at a given time users are talking in a cell, the total bandwidth of the signal received by the base station of the cell will be at least (in khz). 4 written permission. 5

16 EC-GATE-5 PAPE- Since GSM requires KHz and only 8 users can use it using TDMA, 9 th user needs another KHz. 9 th, th, th, th user can use another KHz bandwidth on time share basis. Thus for user we need 4 KHz bandwidth. 8. For the discrete-time system shown in the figure, the poles of the system transfer function are located at Xn Yn Z Z (A), (B), (C) (C), (D), Y(z) z H(z) X(z) 5 z 5 z z z z z z So, poles are z, z. 9. The circuit shown in the figure has an ideal opamp. The oscillation frequency and the condition to sustain the oscillations, respectively, are out C C (A) and (B) and 4 C C (C) and (D) and 4 C C (D) written permission. 6

17 EC-GATE-5 PAPE- Frequency of Wein bridge oscillator is, but in the question time constant is C doubled so, frequency becomes half. C Z j jc Z j c j j j c Z Z Z A source emits bit with probability and bit with probability. The emitted bits are communicated to the receiver. The receiver decides for either or based on the received value. It is given that the conditional density functions of are as, x,, x 5, f (r) 4 and f (r) 6, otherwise,, otherwise. The minimum decision error probability is (A) (B) / (C) /9 (D) /6 (D). For a silicon diode with long P and N regions, the accepter and donor impurity concentrations 7 5 are cm and cm, respectively. The lifetimes of electrons in P region and holes in N region are both s. The electron and hole diffusion coefficients are 49cm / s and 6cm / s, respectively. Assume kt / q 6mV, the intrinsic carrier 9 concentration is cm and q.6 C. When a forward voltage of 8 mv is applied across the diode, the hole current density in na / cm injected from P region to N regions is written permission. 7

18 EC-GATE-5 PAPE- q.d p.p Hole current density L P n n N Given i d N p d cm n 5 sec p n qva kt e Va 8mV,D p 6, Dn 49 qn D i p qva Jp kt N e d p e na / cm. For the NMOSFET in the circuit shown, the threshold voltage is V th, where Vth. The source voltage V ss is varied from to V DD. Neglecting the channel length modulation, the drain current I D as a function V ss is represented by. V DD V SS A I D B I D V DD V th V SS V th V SS written permission. 8

19 EC-GATE-5 PAPE- C I D D I D V DD V th V SS V DD V th V SS (A) V GS = V DS Hence MOS Transistor is in saturation. In saturation, D GS r DD SS T I k V V k V V V As V I Not linearly because square factor SS D Hence option (A) correct. In the system shown in figure (a), m(t) is a low-pass signal with bandwidth W Hz. The frequency response of the band-pass filter H(f) is shown in figure (b). If it is desired that the output signal z(t) = x(t), the maximum value of W (in Hz) should be strictly less than. mtcos4t Hf yt x t x t zt x t Amplifier Hf a Band pass filter f Hz 5 x(t) m(t).cos 4 t Spectrum of x(t) written permission. 9

20 EC-GATE-5 PAPE- X(f ) w w w w f y(t) =x(t)+x (t) Let us draw the spectrum of positive frequencies of y(t). y(t) m(t)cos 4t m (t)cos (4t) cos 48t m(t)cos 4t m (t) m (t) m (t) y(t) m(t)cos 4t cos 48 t m (t) w w y(t) Y(f ) w w w w 4 w 4 w w 7 4 w 7 w 5 written permission.

21 EC-GATE-5 PAPE In the circuit shown, I 8mA and I 4mA. Transistors T and T are identical. Assume o o that the thermal voltage VT is 6mV at 7 C. At 5 C, the value of the voltage V V V (in mv) is. V s I V V V I T T 8.88 We know that I VBE VT Ise I VBE VT Ise I I e At 5 O C, V V VT V 8mV T V V ln 8mV V V 8.88 mv 5. The electric field intensity of a plane wave traveling in free space is give by the following expression E x,t a 4 cos t k x V / m y In this field, consider a square area cm x cm on a plane x + y =. The total timeaveraged power (in mw) passing through the square area is. 5. E(x,t) = 4π cos( t - k x)v/m written permission.

22 EC-GATE-5 PAPE- P avg x y E a x x s 4 a 7.5a Power P P.ds a x y a x avg unit vector normal to thesurface x P 7.5a x. dydz s a 7.5 P 5. W P 5.mW 6. The maximum area (in square units) of a rectangle whose vertices lie on the ellipse x 4y is. rectangle o ellipse Let x, y be the length, breadth respectively of the rectangle inscribed in the ellipse x 4y, then Area of the rectangle (x) (y) i.e., 4xy Consider, f Area 6x y x 4x x y 4 f ' x x x x y y 8 8 written permission.

23 EC-GATE-5 PAPE- f '' x 8 48x when x f is maximum at x = Area is maximum and the maximum area is 4 8 i.e., 7. In the given circuit, the maximum power (in Watts) that can be transferred to the load L is. 4 V rms j L.66 4 j V 45 ; V 4 j Th(rms) Th(mq) Z j j Th Z L th Maximum power transfer to L is 45 Pmax I L.66W j 8. A lead compensator network includes a parallel combination of and C in the feed-forward s path. If the transfer function of the compensator is Gc s, the value of C is s 4..5 s Given G(s) s 4 Zero = = C Pole = 4 = C So, C =.5 written permission.

24 EC-GATE-5 PAPE A MOSFET in saturation has a drain current of ma for VDS.5V. If the channel length modulation coefficient is.5 V, the output resistance in k of the MOSFET is. Under channel length modulation I I V D Dsat DS did I dv r r DS Dsat IDsat.5 k 4. The built-in potential of an abrupt p-n junction is.75v. If its junction capacitance C J at a reverse bias V of.5v is 5pF, the value of C in pf when V.5 C j 7.5V is. V bi V Cj Vbi V C V V j bi Cj C j Cj.5 pf 8 So, answer is.5 J 4. In the circuit shown, assume that the opamp is ideal. The bridge output voltage V (in mv) for.5 is. 5 V V written permission. 4

25 EC-GATE-5 PAPE- 5 I5 A I Vo V 5mV A V o A 4. The damping ratio of a series LC circuit can be expressed as (A) C L (C) L (B) C ' ' (In series LC circuit) Q C L L C (C) C L (D) L C 4. In the circuit shown, switch SW is closed at t =. Assuming zero initial conditions, the value of v t (in Volts) at t= sec is. c t V SW 5 F 6 vct.58 Vc 4V V C ( - ) = V At t =, C is open circuit V c ( ) = 4V written permission. 5

26 EC-GATE-5 PAPE thc sec V t V V V e t C C C C C 4 4e t V 4 4e.58V 44. Consider a uniform plane wave with amplitude E of V / m and.ghz frequency travelling in air, and incident normally on a dielectric medium with complex relative permittivity and permeability as shown in the figure. r r Air Dielectric r j j r cm E? E V/m Freq.GHz. The magnitude of the transmitted electric field component (in V/m) after it has travelled a distance of cm inside the dielectric region is. Dielectric air j j r E V m r = So, E = E = V/m E Electric field in the dielectric after travelling cm E z E e r j j j j j r r j j j j written permission. 6

27 EC-GATE-5 PAPE- z cm E e e. 45. A vector P is given by P x ya x y a x yza. Which one of the following statements x y z is TUE? (A) P is solenoidal, but not irrotational (B) P is irrotational, but not solenoidal, (C) P is neither solenoidal nor irrotational (D) P is both solenoidal and irrotational (A) P x ya x y a x yza x y z.p x y x y x y It is solenoidal. a a a x y z P x y z x y x y x yz a x x y a y xyz a z xy x So P is solenoidal but not irrotational. 46. All the logic gates shown in the figure have a propagation delay of ns. Let A=C= and B= until time t=. At t=, all the inputs flip (i.e., A = C = and B = ) and remain in that state. For t >, output Z = for a duration (in ns) of A B C Z 4 A B C X Y Z As per information given on question the waveforms of A, B, C are as follows written permission. 7

28 EC-GATE-5 PAPE- A B C t The logic to solve this question is first obtain X, Y waveform and using this obtain Z. To obtain X, initially assume delay of NOT gate is and draw its waveform and finally shift it by nsec to obtain actual X. Similar procedure to be followed for obtaining Y and Z i.e., first draw waveform with delay and at the end shift by the amount of delay given in question. X B with delay B t B t B with delay t nsec Y B.A A t B with delay t Y AB without delay z AB Y C AB with delay t nsec t 4nsec written permission. 8

29 EC-GATE-5 PAPE- AB t 4 C t t t 4 Z without delay t 4 Z with delay 4 6 Clearly we can say that output is high during nsec to 6 nsec i.e. a duration of 4 nsec KI 47. A plant transfer function is given as Gs Kp s. When the plant operates in a ss unity feedback configuration, the condition for the stability of the closed loop system is KI (A) Kp (B) KI Kp (C) KI Kp (D) KI Kp (A) Gs sk s p K s I C.E s s s K K H table s Kp s KI s K K s p K I I P For stable system st column elements must be positive K I KP K K I KP I I written permission. 9

30 EC-GATE-5 PAPE A -input majority gate is defined by the logic function Ma,b,c ab bc ca. Which one of the following gates is represented by the function M(M(a,b,c),M(a,b,c),c)? (A) -input NAND gate (C) -input NO gate (B) and (D) Ma,b,c ab bc ac m,5,6,7 M a,b,c m,,,4 X let say for simplicity M a,b,c ab bc ac m,4,6,7 Y let c m,,5,7 z let f M a,b,c,m a,b,c,c f x, y,z xy yz zx (B) -input XO gate (D) -input XNO gate m,,,4 m,4,6,7 m,4,6,7 m,,5,7 m,,5,7 m,,,4 m,4 m7 m AND operater is like intersection m,,4,7 O operator is like union A B C A B C standard result Both options D and B are correct 49. The longitudinal component of the magnetic field inside an air-filled rectangular waveguide made of a perfect electric conductor is given by the following expression 9 H x,y,z,t. cos 5x cos. y cos t z A / m z The cross-sectional dimensions of the waveguide are given as a =.8m and b=.m. The mode of propagation inside the waveguide is (A) TM (B) TM (C) TE (D) TE (C) mx 5 x m 5a a ny. y n.b b Given is H z means TE mode mode TE written permission.

31 EC-GATE-5 PAPE The open-loop transfer function of a plant in a unity feedback configuration is given as Ks 4 Gs. The value of the gain K(>) for which j lies on the root locus s 8 s 9 is. 5.5 By magnitude condition s j G s H s So, k j 7 j j 4 j 8 5 K 5.5 So K value is = Two sequences [a, b, c] and [A, B, C] are related as, A a j B W W b where W e. 4 C W c W If another squence p,q, r is derived as, p A / q W W W B /, 4 4 r W C / W W then the relationship between the sequences [p, q, r] and [a, b, c] is p,q,r b,a,c p,q,r b,c,a (A) (B) (C) p,q,r c,a,b (D) p,q,r c,b,a (C) Consider, written permission.

32 EC-GATE-5 PAPE- 4 w w 6 w w w w w w w w w w w w w ; w w w ; w w w w A w w a B w w b C w w w w w w c w w w w w w a w w w w b w c w w w w w j w e, w w w w w w p a c q b a r c b d y 5. The solution of the differential equation t (A) t e dt dy y with y() y' is dt t (B) te t (C) te (D) te t (B) Differential equation is (D +D+).y = D +D+ = (D+) = D = -,- t solution is y t c ct e C.F t t y' t c e c c t e y() = ; y(t) = (+t)e -t y' gives c = and c +c (-) = c = written permission.

33 EC-GATE-5 PAPE The pole-zero diagram of a causal and stable discrete-time system is shown in the figure. The zero at the origin has multiplicity 4. The impulse response of the system is h[n]. If h[] =, we can conclude Imz ez (A) h[n] is real for all n (B) h[n] is purely imaginary for all n (C) h[n] is real for only even n (D) h[n] is purely imaginary for only odd n (A) x 54. Which one of the following graphs describes the function f x e x x? A B f (x) f (x) x x C f (x) D f (x) x x (B) f() = e -x (x +x+) f() = f(.5) =.67 For positive values of x, function never goes negative. written permission.

34 EC-GATE-5 PAPE The Boolean expression FX,Y, Z XYZ XYZ XYZ XYZ converted into the canonical product of sum (POS) form is (A) X Y ZX Y ZX Y ZX Y Z (B) X Y ZX Y ZX Y ZX Y Z (C) X Y ZX Y ZX Y ZX Y Z (D) X Y ZX Y ZX Y ZX Y Z (A) Given minterms are: F X, Y, Z XYZ XYZ XYZ XYZ So,maxtermisF X,Y,Z m,,,5 POS X Y Z X Y Z X Y Z X Y Z written permission. 4

Q. 1 Q. 25 carry one mark each.

Q. 1 Q. 25 carry one mark each. Q. Q. 5 carry one mark each. Q. Consider a system of linear equations: x y 3z =, x 3y 4z =, and x 4y 6 z = k. The value of k for which the system has infinitely many solutions is. Q. A function 3 = is

More information

Answer Key. Electronics Engineering GATE Forenoon Session 31st Jan, Write us at Phone: ,

Answer Key. Electronics Engineering GATE Forenoon Session 31st Jan, Write us at Phone: , Answer Key of Electronics Engineering GATE-2015 Forenoon Session 31st Jan, 2015 Write us at info@madeeasy.in Phone: 011-45124612, 9958995830 www.madeeasy.in Page 1 Section - I (General Aptitude) Q.1 Choose

More information

Q. 1 Q. 25 carry one mark each.

Q. 1 Q. 25 carry one mark each. GATE 5 SET- ELECTRONICS AND COMMUNICATION ENGINEERING - EC Q. Q. 5 carry one mark each. Q. The bilateral Laplace transform of a function is if a t b f() t = otherwise (A) a b s (B) s e ( a b) s (C) e as

More information

Electronics and Communication Exercise 1

Electronics and Communication Exercise 1 Electronics and Communication Exercise 1 1. For matrices of same dimension M, N and scalar c, which one of these properties DOES NOT ALWAYS hold? (A) (M T ) T = M (C) (M + N) T = M T + N T (B) (cm)+ =

More information

ECE Branch GATE Paper The order of the differential equation + + = is (A) 1 (B) 2

ECE Branch GATE Paper The order of the differential equation + + = is (A) 1 (B) 2 Question 1 Question 20 carry one mark each. 1. The order of the differential equation + + = is (A) 1 (B) 2 (C) 3 (D) 4 2. The Fourier series of a real periodic function has only P. Cosine terms if it is

More information

Exercise The determinant of matrix A is 5 and the determinant of matrix B is 40. The determinant of matrix AB is.

Exercise The determinant of matrix A is 5 and the determinant of matrix B is 40. The determinant of matrix AB is. Exercise 1. The determinant of matrix A is 5 and the determinant of matrix B is 40. The determinant of matrix AB is.. Let X be a random variable which is uniformly chosen from the set of positive odd numbers

More information

ONE MARK QUESTIONS. 1. Consider the network graph shown in the figure. Which one of the following is NOT a tree of this graph?

ONE MARK QUESTIONS. 1. Consider the network graph shown in the figure. Which one of the following is NOT a tree of this graph? ELECTRONICS & COMMUNICATION ENGINEERING ONE MARK QUESTIONS 1. Consider the network graph shown in the figure. Which one of the following is NOT a tree of this graph? (a.) (b.) (c.) (d.). The equivalent

More information

GATE 2017 ECE Session 3 Answer Key

GATE 2017 ECE Session 3 Answer Key 1. Three pair cubical dice are thrown simultaneously. What is the probability that all three dice have same number is... Ans. ( 1 36 ). The one of the eigen value is real, rest are imaginary the real value

More information

1.1 An excitation is applied to a system at t = T and its response is zero for < t < T. Such a system is (a) non-causal system.

1.1 An excitation is applied to a system at t = T and its response is zero for < t < T. Such a system is (a) non-causal system. . An excitation is applied to a system at t = T and its response is zero for < t < T. Such a system is (a) non-causal system x(t) (b) stable system (c) causal system (d) unstable system t=t t. In a series

More information

B. Both A and R are correct but R is not correct explanation of A. C. A is true, R is false. D. A is false, R is true

B. Both A and R are correct but R is not correct explanation of A. C. A is true, R is false. D. A is false, R is true 1. Assertion (A): A demultiplexer can be used as a decode r. Reason (R): A demultiplexer can be built by using AND gates only. A. Both A and R are correct and R is correct explanation of A B. Both A and

More information

EC Objective Paper I (Set - D)

EC Objective Paper I (Set - D) EC-Objective Paper-I ESE-5 www.gateforum.com EC Objective Paper I (Set - D). If a system produces frequencies in the output are not present in the input, then the system cannot be Minimum phase system

More information

ONE MARK QUESTIONS. 1. The condition on R, L and C such that the step response y(t) in the figure has no oscillations, is

ONE MARK QUESTIONS. 1. The condition on R, L and C such that the step response y(t) in the figure has no oscillations, is ELECTRONICS & COMMUNICATION ENGINEERING ONE MARK QUESTIONS. The condition on R, L and C such that the step response y(t) in the figure has no oscillations, is (a.) R L C (b.) R L C (c.) R L C (d.) R LC

More information

Conventional Paper-I Part A. 1. (a) Define intrinsic wave impedance for a medium and derive the equation for intrinsic vy

Conventional Paper-I Part A. 1. (a) Define intrinsic wave impedance for a medium and derive the equation for intrinsic vy EE-Conventional Paper-I IES-01 www.gateforum.com Conventional Paper-I-01 Part A 1. (a) Define intrinsic wave impedance for a medium and derive the equation for intrinsic vy impedance for a lossy dielectric

More information

GATE 2009 Electronics and Communication Engineering

GATE 2009 Electronics and Communication Engineering GATE 2009 Electronics and Communication Engineering Question 1 Question 20 carry one mark each. 1. The order of the differential equation + + y =e (A) 1 (B) 2 (C) 3 (D) 4 is 2. The Fourier series of a

More information

1 P a g e.

1 P a g e. 1. Choose the most appropriate word from the options given below to complete the following sentence. Communication and interpersonal skills are important in their own ways. each B. both C. all either.

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

INDIAN SPACE RESEARCH ORGANISATION. Recruitment Entrance Test for Scientist/Engineer SC 2017

INDIAN SPACE RESEARCH ORGANISATION. Recruitment Entrance Test for Scientist/Engineer SC 2017 1. The signal m (t) as shown is applied both to a phase modulator (with kp as the phase constant) and a frequency modulator with ( kf as the frequency constant) having the same carrier frequency. The ratio

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

GATE 2007 Electronics and Communication Engineering

GATE 2007 Electronics and Communication Engineering GATE 2007 Electronics and Communication Engineering Q.1 to Q.20 carry one mark each 1. If E denotes expectation, the variance of a random variable X is given by (A) E[X ] E [X] (C) E[X ] (B) E[X ] E [X]

More information

Exercise: 4. 1 converges. 1. The series. (D) e. (A) 2 ln 2 (C) 2 (B) 2. equal to. 4. If. a and b equation. d x 2. (D) ae 2t. (A) ae t.

Exercise: 4. 1 converges. 1. The series. (D) e. (A) 2 ln 2 (C) 2 (B) 2. equal to. 4. If. a and b equation. d x 2. (D) ae 2t. (A) ae t. Exercise: 4 1. The series n 1 = 0 n! converges to (A) ln (B) (C) (D) e. The magnitude of the gradient for the function f(x, y, z) = x =3y +z 3 at the point (1, 1, 1) is. 3. Let X be a zero mean unit variance

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

Conventional Paper I (a) (i) What are ferroelectric materials? What advantages do they have over conventional dielectric materials?

Conventional Paper I (a) (i) What are ferroelectric materials? What advantages do they have over conventional dielectric materials? Conventional Paper I-03.(a) (i) What are ferroelectric materials? What advantages do they have over conventional dielectric materials? (ii) Give one example each of a dielectric and a ferroelectric material

More information

ECE PN Junctions and Diodes

ECE PN Junctions and Diodes ECE 342 2. PN Junctions and iodes Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 342 Jose Schutt Aine 1 B: material dependent parameter = 5.4 10

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The

More information

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed)

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed) ECE-342 Test 2 Solutions, Nov 4, 2008 6:00-8:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free

More information

EE Branch GATE Paper 2010

EE Branch GATE Paper 2010 Q.1 Q.25 carry one mark each 1. The value of the quantity P, where, is equal to 0 1 e 1/e 2. Divergence of the three-dimensional radial vector field is 3 1/r 3. The period of the signal x(t) = 8 is 0.4

More information

GATE 2016 General Aptitude - GA Set-3 Q. 1 Q. 5 carry one mark each. Q.1 Based on the given statements, select the appropriate option with respect to grammar and usage. Statements (i) The height of Mr.

More information

Homework Assignment 08

Homework Assignment 08 Homework Assignment 08 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. Give one phrase/sentence that describes the primary advantage of an active load. Answer: Large effective resistance

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

GATE EE Topic wise Questions SIGNALS & SYSTEMS

GATE EE Topic wise Questions SIGNALS & SYSTEMS www.gatehelp.com GATE EE Topic wise Questions YEAR 010 ONE MARK Question. 1 For the system /( s + 1), the approximate time taken for a step response to reach 98% of the final value is (A) 1 s (B) s (C)

More information

GATE 2010 Electrical Engineering

GATE 2010 Electrical Engineering GATE 2010 Electrical Engineering Q.1 Q.25 carry one mark each 1. The value of the quantity P, where P = xe dx, is equal to (A) 0 (B) 1 (C) e (D) 1/e 2. Divergence of the three-dimensional radial vector

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

2013 Question Booklet Code EC : ELECTRONICS AND COMMUNICATION ENGINEERING

2013 Question Booklet Code EC : ELECTRONICS AND COMMUNICATION ENGINEERING 013 Question Booklet Code EC : ELECTRONICS AND COMMUNICATION ENGINEERING A Duration: Three Hours Maximum Marks: 100 Read the following instructions carefully. 1. Do not open the seal of the Question Booklet

More information

SESSION - 1. Auhippo.com

SESSION - 1. Auhippo.com SESSION - 03 Question Booklet Code EC : ELECTRONICS AND COMMUNICATION ENGINEERING A Duration: Three Hours Maximum Marks: 00 Read the following instructions carefully.. Do not open the seal of the Question

More information

This is the 15th lecture of this course in which we begin a new topic, Excess Carriers. This topic will be covered in two lectures.

This is the 15th lecture of this course in which we begin a new topic, Excess Carriers. This topic will be covered in two lectures. Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 15 Excess Carriers This is the 15th lecture of this course

More information

Digital Electronics Part II Electronics, Devices and Circuits

Digital Electronics Part II Electronics, Devices and Circuits Digital Electronics Part Electronics, Devices and Circuits Dr.. J. Wassell ntroduction n the coming lectures we will consider how logic gates can be built using electronic circuits First, basic concepts

More information

Q. 1 Q. 5 carry one mark each.

Q. 1 Q. 5 carry one mark each. GATE 2019 General Aptitude (GA) Set-3 Q. 1 Q. 5 carry one mark each. Q.1 I am not sure if the bus that has been booked will be able to all the students. (A) sit (B) deteriorate (C) fill (D) accommodate

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it. Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The

More information

Microelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises

Microelectronic Circuit Design Fourth Edition - Part I Solutions to Exercises Page Microelectronic Circuit esign Fourth Edition - Part I Solutions to Exercises CHAPTER V LSB 5.V 0 bits 5.V 04bits 5.00 mv V 5.V MSB.560V 000000 9 + 8 + 4 + 0 785 0 V O 785 5.00mV or ) 5.V 3.95 V V

More information

3. (a) Figure 3(a) shows a Bridge T network used in control systems. The element values are clearly marked in the figure.

3. (a) Figure 3(a) shows a Bridge T network used in control systems. The element values are clearly marked in the figure. I.E.S.-(Conv.) 1987 ELECTRICAL ENGINEERING PAPER - I PART A 1. (a) Define precisely unit step and unit impulse functions. Sketch the following function from t = 0 to t = 10 units, indicating all salient

More information

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00 1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.

More information

SEM-2016(02)-I ELECTRICAL ENGINEERING. Paper -1. Please read the following instructions carefully before attempting questions.

SEM-2016(02)-I ELECTRICAL ENGINEERING. Paper -1. Please read the following instructions carefully before attempting questions. Roll No. Candidate should write his/her Roll No. here. Total No. of Questions : 7 No. of Printed Pages : 8 SEM-2016(02)-I ELECTRICAL ENGINEERING Paper -1 Time : 3 Hours ] [ Total Marks ; 300 Instructions

More information

`EC : ELECTRONICS AND COMMUNICATION ENGINEERING

`EC : ELECTRONICS AND COMMUNICATION ENGINEERING 03 Question Booklet Code B `EC : ELECTRONICS AND COMMUNICATION ENGINEERING Duration: Three Hours Maximum Marks: 00 Read the following instructions carefully.. Do not open the seal of the Question Booklet

More information

(Refer Slide Time: 03:41)

(Refer Slide Time: 03:41) Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 25 PN Junction (Contd ) This is the 25th lecture of this course

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

ECE2262 Electric Circuits. Chapter 6: Capacitance and Inductance

ECE2262 Electric Circuits. Chapter 6: Capacitance and Inductance ECE2262 Electric Circuits Chapter 6: Capacitance and Inductance Capacitors Inductors Capacitor and Inductor Combinations Op-Amp Integrator and Op-Amp Differentiator 1 CAPACITANCE AND INDUCTANCE Introduces

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

CBSE Physics Set I Outer Delhi Board 2012

CBSE Physics Set I Outer Delhi Board 2012 Q28. a) In Young s double slit experiment, derive the condition for (I) constructive interference and (II) destructive interference at a point on the screen. b) A beam of light consisting of two wavelengths,

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

Q. 1 Q. 5 carry one mark each.

Q. 1 Q. 5 carry one mark each. General Aptitude (GA) Set-5 Q. 1 Q. 5 carry one mark each. Q.1 By giving him the last of the cake, you will ensure lasting in our house today. The words that best fill the blanks in the above sentence

More information

Q1. A wave travelling along a string is described by

Q1. A wave travelling along a string is described by Coordinator: Saleem Rao Wednesday, May 24, 2017 Page: 1 Q1. A wave travelling along a string is described by y( x, t) = 0.00327 sin(72.1x 2.72t) In which all numerical constants are in SI units. Find the

More information

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto

Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually

More information

Examination paper for TFY4185 Measurement Technique/ Måleteknikk

Examination paper for TFY4185 Measurement Technique/ Måleteknikk Page 1 of 14 Department of Physics Examination paper for TFY4185 Measurement Technique/ Måleteknikk Academic contact during examination: Patrick Espy Phone: +47 41 38 65 78 Examination date: 15 August

More information

GATE : , Copyright reserved. Web:www.thegateacademy.com

GATE : , Copyright reserved. Web:www.thegateacademy.com GATE-2016 Index 1. Question Paper Analysis 2. Question Paper & Answer keys : 080-617 66 222, info@thegateacademy.com Copyright reserved. Web:www.thegateacademy.com ANALYSIS OF GATE 2016 Electrical Engineering

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

SE]y[-2017(02)-I ELECTRICAL ENGINEERING. Paper. Please read each of the following instructions carefully before attempting questions.

SE]y[-2017(02)-I ELECTRICAL ENGINEERING. Paper. Please read each of the following instructions carefully before attempting questions. RoU No. 300218 Candidate should write his/her Roll No. here. Total No. of Questions : 7 No. of Printed Pages : 7 SE]y[-2017(02)-I ELECTRICAL ENGINEERING Paper Time : 3 Hours ] [ Total Marks : 300 Instructions

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Sample Exam # 2 ECEN 3320 Fall 2013 Semiconductor Devices October 28, 2013 Due November 4, 2013

Sample Exam # 2 ECEN 3320 Fall 2013 Semiconductor Devices October 28, 2013 Due November 4, 2013 Sample Exam # 2 ECEN 3320 Fall 203 Semiconductor Devices October 28, 203 Due November 4, 203. Below is the capacitance-voltage curve measured from a Schottky contact made on GaAs at T 300 K. Figure : Capacitance

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture

More information

Electronics and Communication Engineering Q. No. 1 to 25 Carry One Mark Each. Z The Boolean expression F implemented by the circuit is (A) XYZ XY YZ

Electronics and Communication Engineering Q. No. 1 to 25 Carry One Mark Each. Z The Boolean expression F implemented by the circuit is (A) XYZ XY YZ EC GATE-7-PAPER-II www.gateforum.com Electronics and Communication Engineering Q. No. to 5 Carry One Mark Each. Consider the circuit shown in the figure. Y MUX Key X Z The Boolean expression F implemented

More information

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1

Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop

More information

GATE 2008 Electrical Engineering

GATE 2008 Electrical Engineering GATE 2008 Electrical Engineering Q.1 Q. 20 carry one mark each. 1. The number of chords in the graph of the given circuit will be + _ (A) 3 (B) 4 (C) 5 (D) 6 2. The Thevenin'a equivalent of a circuit operating

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

Chapter 7. The pn Junction

Chapter 7. The pn Junction Chapter 7 The pn Junction Chapter 7 PN Junction PN junction can be fabricated by implanting or diffusing donors into a P-type substrate such that a layer of semiconductor is converted into N type. Converting

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution

Vidyalankar S.E. Sem. III [EXTC] Analog Electronics - I Prelim Question Paper Solution . (a) S.E. Sem. [EXTC] Analog Electronics - Prelim Question Paper Solution Comparison between BJT and JFET BJT JFET ) BJT is a bipolar device, both majority JFET is an unipolar device, electron and minority

More information

Consider a uniformly doped PN junction, in which one region of the semiconductor is uniformly doped with acceptor atoms and the adjacent region is

Consider a uniformly doped PN junction, in which one region of the semiconductor is uniformly doped with acceptor atoms and the adjacent region is CHAPTER 7 The PN Junction Consider a uniformly doped PN junction, in which one region of the semiconductor is uniformly doped with acceptor atoms and the adjacent region is uniformly doped with donor atoms.

More information

ELECTRONICS IA 2017 SCHEME

ELECTRONICS IA 2017 SCHEME ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

GATE 2010 Electronics and Communication Engineering

GATE 2010 Electronics and Communication Engineering GATE 2010 Electronics and Communication Engineering Q.1 Q.25 carry one mark each. Q1. The eigen values of a skew-symmetric matrix are (A) Always zero (B) Always pure imaginary (C) Either zero or pure imaginary

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Power System Operations and Control Prof. S.N. Singh Department of Electrical Engineering Indian Institute of Technology, Kanpur. Module 3 Lecture 8

Power System Operations and Control Prof. S.N. Singh Department of Electrical Engineering Indian Institute of Technology, Kanpur. Module 3 Lecture 8 Power System Operations and Control Prof. S.N. Singh Department of Electrical Engineering Indian Institute of Technology, Kanpur Module 3 Lecture 8 Welcome to lecture number 8 of module 3. In the previous

More information

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power

Announcements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power - Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances

More information

ADIKAVI NANNAYA UNIVERSITY::RAJAMAHENDRAVARAM II BTech (EIE) I Semester BTEIE301 DIGITAL LOGIC DESIGN MODEL QUESTION PAPER Time:3 hrs. Max.

ADIKAVI NANNAYA UNIVERSITY::RAJAMAHENDRAVARAM II BTech (EIE) I Semester BTEIE301 DIGITAL LOGIC DESIGN MODEL QUESTION PAPER Time:3 hrs. Max. II BTech (EIE) I Semester BTEIE301 DIGITAL LOGIC DESIGN SECTION-A (4 X 15 = 60 M) 1. a) List out the Basic Theorems and Properties of Boolean Algebra. Justify with the Proof (15M) b) Explain how 1's complement

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS 1) Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction (a) X -Y and (b) Y - X using 2's complements. a) X = 1010100

More information

Conventional Paper I-2010

Conventional Paper I-2010 Conventional Paper I-010 1. (a) Sketch the covalent bonding of Si atoms in a intrinsic Si crystal Illustrate with sketches the formation of bonding in presence of donor and acceptor atoms. Sketch the energy

More information

Digital Electronics Electronics, Devices and Circuits

Digital Electronics Electronics, Devices and Circuits Digital Electronics Electronics, Devices and Circuits Dr. I. J. Wassell Introduction In the coming lectures we will consider how logic gates can be built using electronic circuits First, basic concepts

More information

Q. 1 Q. 5 carry one mark each.

Q. 1 Q. 5 carry one mark each. GATE 2016 General Aptitude - GA Set-6 Q. 1 Q. 5 carry one mark each. Q.1 The man who is now Municipal Commissioner worked as. (A) the security guard at a university (B) a security guard at the university

More information

STD : 12 TH GSEB PART A. 1. An electric dipole is placed in a uniform field. The resultant force acting on it...

STD : 12 TH GSEB PART A. 1. An electric dipole is placed in a uniform field. The resultant force acting on it... STD : 1 TH PHYSICS RJ VISION PVT. LTD. (MOST STABLE & INNOVATIVE INSTITUTE) GSEB COURSE NAME: 1 TH Total Marks : 100 Time : 3 hrs PART A Multiple Choice uestions : 1. An electric dipole is placed in a

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information