Efficient arithmetic Fourier transform implementation to detect potential electromigration failures in FPGAs

Transcription

1 The University of Toledo The University of Toledo Digital Repository Theses and Dissertations 2011 Efficient arithmetic Fourier transform implementation to detect potential electromigration failures in FPGAs Sai Deepa Rayaprolu The University of Toledo Follow this and additional works at: Recommended Citation Rayaprolu, Sai Deepa, "Efficient arithmetic Fourier transform implementation to detect potential electromigration failures in FPGAs" (2011). Theses and Dissertations This Thesis is brought to you for free and open access by The University of Toledo Digital Repository. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of The University of Toledo Digital Repository. For more information, please see the repository's About page.

2 A Thesis entitled Efficient Arithmetic Fourier Transform Implementation to Detect Potential Electromigration Failures in FPGAs by Sai Deepa Rayaprolu Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering Dr. Mohammed Niamat, Committee Chair Dr. Srinivasa Vemuru, Committee Co-Chair Dr. Junghwan Kim, Committee Member Dr. Patricia R. Komuniecki, Dean, College of Graduate Studies The University of Toledo December 2011

3 Copyright 2011, Sai Deepa Rayaprolu This document is copyrighted material. Under copyright law, no parts of this document may be reproduced without the expressed permission of the author.

4 An Abstract of Efficient Arithmetic Fourier Transform Implementation to Detect Potential Electromigration Failures in FPGAs by Sai Deepa Rayaprolu Submitted to the Graduate Faculty as a partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering The University of Toledo December 2011 With miniaturization of components in VLSI circuits there is a steady increase in power density and current density resulting in an increase in temperature. This results in degradation in performance of the circuitry over time due to a number of failure mechanisms such as electromigration. There is a critical need to identify these failures that exhibit a mixed-signal degradation that can be identified through the analysis of Fourier coefficients. Arithmetic Fourier Transform (AFT) is a computationally simple and faster frequency domain technique for computing the Fourier coefficients. In this thesis, an efficient and modular architecture is proposed for the implementation of AFT algorithm which is used as Built-in-Self Test structure to identify electromigration faults in the interconnects of FPGA. The proposed design is efficient in terms of area, time and power utilization factors when compared to the previous architectures. iii

5 A Xilinx Virtex 5 FPGA, implemented in 65 nm prefabrication process, is used to implement and simulate the electromigration failure mechanism. This failure is determined for different lengths of interconnects and for various input patterns. Fault signatures are developed for different interconnect resources on the FPGA and simulation results are presented. Cut-off values for the Fourier Coefficients are determined for all the cases and identification of presence of electromigration is done accordingly using the proposed Arithmetic Fourier Transform (AFT) design. The cut-off values of percentage deviations in selected coefficient for local, intermediate and global interconnect are found to be 60%, 50% and 33.3%, respectively. Any deviation in the coefficient crossing the estimated cut-off percentages with respect to the signatures developed leads to the occurrence of electromigration faults and failures in the circuit. iv

6 This thesis is dedicated to my parents, R.V.S.S. Prasad Rao and R.jyohi Prasad, and my sister, Sai Ramya Rayaprolu. v

7 Acknowledgements First, I would like to thank my advisor Dr.Niamat for providing me an opportunity to conduct my Master s research under him and his mentorship over the course of it. Next, I want to thank Dr.Vemuru, whose time, understanding and patience when providing clear and simple explanations allowed me to complete my thesis. My sincere thanks to Dr. Junghwan Kim for being a part of my thesis committee. I would also like to thank UT Electrical Engineering and Computer Sciences department, for partially funding my Master s degree. I would like to thank my parents, R.V.S.S. Prasad Rao and R. Jyothi Prasad for their constant love, support, understanding, encouragement, motivation, and their sacrifices and efforts that made this thesis possible. Thanks to my sister Sai Ramya Rayaprolu for sharing my happiness, cheering me up, and being my best friend always. I would like to acknowledge my friends at UT, especially my classmate James Valleroy, in helping me understand the basics of my work, and Vivek Palepu, for being my best companion throughout my Masters and Internship phases of my career. Additional thanks to Kartheek Battu, Avinash, Manoj, Srikanth, Jyothi, Sankeerth, Keerthi, Bhavya, Pavan, Prakash, Prasad Garu, Suresh Reddy and Chaitanya for making my stay at UT wonderful and memorable. Last but not the least, I would like to thank my roommates Bhuvana, Karpagam, Snigdha, and Punita for always being friendly and providing me with comfort while working on my thesis. vi

8 Table of Contents Abstract... iii Acknowledgements...vi Table of Contents... vii List of Tables... xii List of Figures... xiv 1 Introduction Introduction FPGA and BIST Architectures FPGA BIST Architectures Need for Frequency Domain Techniques Electromigration Fault Modeling and Fault Signatures Motivation Model Development Goals of the Research Thesis Organization vii

9 2 Arithmetic Fourier Transform Conventional Fourier Techniques for DSP The computation of DFT Fast Fourier Transform Arithmetic Fourier Transform Comparison of Different Fourier techniques for DSP Motivation to AFT Arithmetic Fourier Transform Fourier Analysis Bruns Arithmetic Fourier Transform Survey of AFT Architectures Systolic Arrays for the AFT Modular Linear Array Architecture Overview of VLSI Architectures for AFT Hardware Design for AFT Computation Arithmetic Fourier Transform Implementation Gate Level Description of the Algorithm Internal Operation of a BasicArch Block Scaling of Alternate Average Values Mobius Function for Determining Fourier Coefficients viii

10 3.2 Comparison of Proposed Method with Prasanna et al AFT Algorithm Implementations: Matlab and VHDL Different Methods Computed to Determine Fourier Coefficients Using Arithmetic Fourier Transform MatLab Implemented Coefficients from Direct Equations of AFT Outline Code and Explanation Xilinx ISE Tool Implemented Coefficients Using VHDL Outline Code and Explanation Matlab Implemented Coefficients in Hardware Outline Code and Explanation Extension of Design: 16 Fourier Coefficients Area, Time and Power Estimations of the Design Area Analysis Timing Analysis Power Analysis Identification of Electromigration Failures Electromigration (EM) Motivation Weak 0s and Weak 1s Fault Model Development ix

11 6.2.1 Estimation of Net Length, Resistance & Capacitance of Interconnects Details of Weak 0 and Weak 1 in the Test Circuit Identifying Presence of EM Consequences of EM Occurrence Contributions and Conclusions Contributions Future Work References A Analysis for 6L and 24L Interconnect Lengths A.1 6L Interconnects A.1.1 Weak A.1.2 Weak A.2 24L Interconnect A.2.1 Weak A.2.2 Weak B Break Models B.1 Break Models for Mbreakp and Mbreakn Transistors B.1.1 Mbreakp B.1.2 Mbreakn x

12 C Logic Descipion for Select File C.1 Logic Description C.2 Example for BasicArch xi

13 List of Tables 3.1 Bit Values in Select File for the BasicArch Blocks Tabular Column for Comparing Different Architectures Coefficients Obtained from Matlab Implementation Binary Representation of Coefficients Obtained from Matlab Implementation Binary representation of coefficients obtained from Xilinx VHDL implementation of AFT Binary Select File Binary Select File for a 16-Port AFT Architecture Slice Logic Distribution of BasicArch Block on Xilinx Virtex 5 FPGA Slice Logic Utilization of BasicArch Block on Xilinx Virtex 5 FPGA Slice Logic Distribution of Top Level Block on Xilinx Virtex 5 FPGA Slice Logic Utilization of Top Level Block on Xilinx Virtex 5 FPGA Timing Analysis of BasicArch Block on Xilinx Virtex 5 FPGA Timing Analysis of Top Level Block on Xilinx Virtex 5 FPGA Power Estimation of Top Level Block on Xilinx Virtex 5 FPGA Resistances and Capacitances of Different Lengths of Interconnects Fourier Coefficients of Fault Free Inverter Circuit Signature Values Fourier Coefficients of Weak 0 Inverter Circuit of 2L Interconnect Fourier coefficients of Weak 1 inverter circuit of 2L Interconnect xii

14 6.5 Comparisons and Deviations of Coefficients with Prominent Differences A.1 Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-off Values for Determining the EM Fault in Weak 0 Circuit with Interconnects of Length 6L A.2 Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-Off Values for Determining the EM Fault in Weak 1 Circuit with Interconnects of Length 6L A.3 Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-Off Values for Determining the EM Fault in Weak 0 Circuit with 24L Length of Interconnect A.4 Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-Off Values for Determining the EM Fault in Weak 1 Circuit with Interconnects of Length 24L C.1 Sequence of Steps to Obtain the a Coefficient Binary Bits for BasicArch 3 as an Example C.2 Sequence of Steps to Obtain the b Coefficient Binary Bits for BasicArch 3 as an Example xiii

15 List of Figures 1-1 Block Diagram of FPGA Arrangement of Slices within the CLB Circuit Diagram of SliceL [3] Stages of BIST Systolic Array for AFT Arrangement of Process Elements for the Computation of AFT [10] Arithmetic Fourier Transform Algorithm [10] Data Flow Graph of the AFT Algorithm Block Diagram of the Top Level Architecture Input End of the Design Implementation of AFT Internal Components and Connections in a BasicArch XOR-Circuitry for Alternate Add and Subtract Logic Flow Chart for the Division Operation State diagram for the sequential division operation The Top Level Architecture in Detail Overall Approach for Coefficients Comparison and Validation Input Data Used as an Example to Compute Fourier Coefficients Pseudo-Code for Direct AFT Implementation Using Equations xiv

16 4-4 Schematic Representation of VHDL Program for AFT Implementation Outline Code of AFT in VHDL Top Level Architecture Fourier Coefficients from AFT Implementation on Xilinx Using VHDL (a) Outline Code of AFT Implementation (b) Computed Fourier Coefficients Hardware Utilization for the 16 Port Input Design Logic Levels for CMOS Logic Family Ideal Inverter Circuit with the Corresponding Waveforms Inverter Circuit with the R and C of Interconnect Modeled Inverter Circuit with Weak 0 Fault Modeled in it Inverter Circuit with Weak 1 Fault Modeled in it Output Waveform for a Fault Free 2L Interconnect Inverter Circuit Fault Free Inverter Circuit for 2L Interconnect Output Waveform of Fault free Inverter Circuit of 2L Interconnect Inverter Circuit with 2L Interconnect Modeled with Weak 0 Fault Output Waveform of Inerter Circuit with 2L Interconnect Modeled for Weak Inverter Circuit with 2L Interconnect Modeled with Weak 1 Fault \6-12 Output Waveform of Inverter Circuit with 2L Interconnect Modeled for a Weak 1 Fault : VHDL Implementation for the Identification of EM A-1 Circuit Diagram for Weak 0 fault with 6L interconnect A-2 Waveform Obtained after Simulating Weak 0 Circuit A-3 Circuit Diagram for Weak 1 Fault with 6L Interconnect xv

17 A-4 Waveform Obtained from Simulation of Weak 1 Circuit A-5 Circuit Diagram for Weak 0 Fault with 24L Interconnect A-6 Waveform for Weak 0 Circuit after Simulation A-7 Circuit Diagram for Weak 1 Fault with 24L Interconnect A-8 Waveform for Weak 1 Circuit with 24L Interconnect after Simulation C-1 Variable Declarations for the Algorithm C-2 Brief Algorithm in Terms of Equation xvi

18 Chapter 1 Introduction and Research Overview This chapter is organized into five Sections. The first section gives an overview of work done in this thesis. The second Section introduces the Field Programmable Gate Array (FPGA) and built-in self-test (BIST) architectures along with the need for frequency domain techniques. Section 1.3 introduces the motivation behind work done and an application of Arithmetic Fourier Transform (AFT) algorithm in identifying the electromigration fault. The contributions of research are discussed in Section 1.4 and the last section details the organization of the thesis. 1.1 Introduction With the advances in semiconductor technology, the device dimensions are continuously being reduced and the current density in interconnects on a chip is consistently increasing [2]. The occurrence of electromigration fault is one of the challenges that arise in such situations and hence its detection becomes very important in long-term reliability of electronic designs. In this thesis, an efficient Arithmetic Fourier Transform (AFT) architecture is developed and implemented in Xilinx Virtex 5 FPGA. A methodology is developed to identify the electromigration fault using the AFT that can be used in early detection of potential electromigration failures. 1

19 1.2 FPGA and BIST Architectures FPGA Field Programmable Gate Array is a special type of logic chip which comprises of thousands of programmable logic blocks, interconnections and input/output (I/O) blocks. These are very popular for prototyping electronic system designs. After the design is verified in prototypes, sometimes the designs are migrated to custom integrated circuits. With the increase in capabilities and speed, FPGAs are being used in product designs for complex functions and increasingly used in SoC (System on Chip) circuit implementations. The basic architecture of Xilinx FPGAs consists of a two-dimensional array of Configurable Logic Blocks (CLBs) and Programmable I/O blocks, connected by a programmable interconnect network as shown in Figure 1-1. Interconnects comprise of segments of wire of varying length. Each of the segments terminates either at a programmable switch matrix or at a CLB. The signals in FPGAs are routed using the routing resources, which are located in horizontal and vertical routing channels between each switch matrix. CLBs are capable of implementing sequential and combinational logic designs. Implementation of logic circuits on FPGAs is done by partitioning the functionality into individual logic blocks and then providing the necessary interconnections between the logic blocks using the switches. FPGA bridges the gap between discrete logic and costly Application Specific Integrated Circuits (ASICs) on the higher end of complexity scale [1]. FPGAs provide the users with all features to implement complex designs. 2

20 Figure 1-1: Block Diagram of FPGA Configurable Logic Block (CLB) In Xilinx Virtex-5 FPGA family, a Configurable Logic Block contains two slices that do not have direct connection with each other. Each slice is organized as a column in the CLB as shown in the Figure 1-2. Each slice contains four logic function generators called Look-Up-Tables (LUTs), four storage elements, and wide function multiplexers, carry logic to provide logic, arithmetic and ROM functions as shown in Figure 1-3 [3]. Most of the CLB inputs and outputs are connected to a switch matrix to gain access to the general routing resources. Each slice in the column also has an independent carry chain. The slices that provide the logic only functionality are generally called as SLICEL. Some 3

21 other slices, called SLICEM, provide additional memory-based functionalities like storing and sorting the data using distributed RAM and shifting data with 32 bit registers. Each CLB can contain up to one SLICEM blocks. Figure 1-2: Arrangement of Slices within the CLB Look-Up Table (LUT): The function generator or LUT in Virtex-5 can implement one six-input function or two five-input independent functions. However, the five-input functions share the same set of inputs. Each LUT has two independent outputs called O 5 and O 6. When a 6-input function is implemented only the O 6 output is used. When two 5-input functions are implemented both the outputs are used. 4

22 Figure 1-3: Circuit Diagram of SliceL [3] The propagation delay through the LUT is same whether a 6-input function is implemented or two 5-input functions are implemented. Along with the LUTs, each slice contains three multiplexers. These multiplexers can be used to combine the LUTs to 5

23 generate the functions of up to 7 or 8 inputs. Figure 1.3 shows the detailed implementation of a CLB slice BIST Architectures Testing the circuitry for proper functionality is a critical need for electronic systems. The goal of testing is to exercise all portions of the circuit, checking to ensure that all logical functions and interconnections are operating properly. This process is further complicated by the limited input/output pin count relative to the complexity of modern electronic systems. This limits the ability to move test vectors into the circuitry and send back resulting responses of the system for analysis. Built-In Self Test (BIST) solves these issues by having the test pattern generators and the analyzers embedded inside the circuitry. However, this approach adds additional overhead. An additional advantage of BIST methodology is that the integrity of the circuitry can be maintained beyond manufacturing testing [4]. The BIST circuitry consists of three main blocks as shown in Figure 1-4: TPG (Test Pattern Generator), CUT (Circuit Under Test), and ORA (Output Response Analyzer). In order to test a circuit, inputs are given as test vectors or test patterns. The outputs from the CUT are given as input to the ORA. response By comparing the values at the output from CUT with the stored signature values of the test patterns, ORA will identify whether the circuit is faulty or not. 6

24 Figure 1-4: Stages of BIST Need for Frequency Domain Techniques: Electromigration failures can manifest as either reduced voltage levels or as increased signal transition times. These effects are analog in nature that can be easily detected using frequency domain techniques. DFT is widely used in the field of signal processing to analyze the frequency components contained in a sampled signal. But, due to high number of complex calculations and low speed of computation, Fast Fourier Transform (FFT) has become popular to compute the Fourier coefficients more efficiently. Since most of the FFT calculations are composed of complex numbers, the mathematical computations with complex numbers make it a difficult task. Hence, Arithmetic Fourier Transform (AFT), an even less complex approach to perform the DFT [8] with efficient area and time results is considered in this work. It involves less complex computations which include additions and one multiplication with real numbers. If there arises the need for computation of many DFTs in stipulated timeline, use of AFT method will make the task easier. A detailed discussion of the AFT is done in Chapter 2. In this work, AFT algorithm is used in BIST circuit and new hardware architecture is developed. An area efficient and modular design of AFT is then 7

25 implemented on Xilinx Virtex 5 FPGA using VHDL. The accuracy of the coefficients calculated while using Fourier transforms tend to increase with the increase in input signal bit width, i.e, the number of bits used to represent the value of the input signal. However it comes with additional hardware complexity. Hence, AFT implementations are developed with different input bit-widths ( 8-bits, 9-bits, 10-bits, 12-bits and 16-bits). Also, with increase in the bit length of architecture, variations in area, time and power parameters are also observed as discussed in Chapter Electromigration Fault Modeling and Fault Signatures Motivation The miniaturization of electronic circuitry has been the primary driving force in Very Large Scale Integrated (VLSI) circuits. FPGA vendors are one of the primary users of these cutting edge processes of the electronics industry resulting in high density complex circuits. This is leading to high density of interconnects within the FPGA that can potentially have or develop many faults and failures. The scaling down of the process features can lead to increase in circuit densities in interconnects. The increase in current density increases the temperature of interconnects which tend to melt with time, leaving them to break or cause shorts and become reason for the failure of an IC. This phenomenon is termed as Electromigration (EM). Hence, it becomes very important to test the FPGA interconnects for EM failures during their normal operation. 8

26 1.3.2 Model Development Identifying electromigration occurrence in interconnects of FPGA using AFT is the main focus of this thesis. A circuit model is developed to perform analysis in order to identify the early occurrence of EM faults, The transient analysis results of the circuit s output voltage signal provides the values that are given as inputs to AFT implementation. The output of the AFT implementation computes the corresponding Fourier coefficients. These Fourier coefficients obtained from the fault free circuit are used as signature values to compare with the values obtained from the electromigration fault introduced model. Earlier identification of the potential EM faults in FPGA interconnect can be used to extend the lifetime of FPGA by avoiding the failing interconnect and using alternative signal interconnect resources on the FPGA. The details of the entire procedure are explained in Chapter Goals of the Research The goals of this research work are as follows: To develop an efficient BIST circuitry for detecting potential electromigration failures in FPGAs based on frequency transform methods. To efficiently implement hardware designs of AFT using VHDL and MATLAB To determine the Area, Delay and Power analysis in FPGA implementations of AFT algorithms 9

27 To model a circuit of driver stage and interconnect in Virtex-5 FPGA based on 65 nm IC fabrication process To develop EM fault signatures for short, medium and long interconnects in FPGAs based on Arithmetic Fourier Transform coefficients. 1.5 Thesis Organization This thesis is organized as follows: The second chapter delineates the known efficient methods of implementing AFT algorithm in the literature. The third chapter presents the proposed method describing an efficient and modular architecture developed at gate level for the implementation of AFT. In chapter 4, different modes of result analyses (VHDL and Matlab) are discussed in detail with the validation of results obtained. The fifth chapter explains the Area, Time and Power (A-T-P) utilized by the developed gate level hardware for AFT implementation with different input bit-widths. The sixth chapter provides a detailed explanation of an AFT algorithm application in identifying the presence of Electromigration (EM) fault in a circuit. The conclusions and future work that can also be done with respect to the AFT algorithm in chapter 7. 10

28 Chapter 2 Arithmetic Fourier Transform This chapter is organized as three Sections. In the first Section, the Fourier transform methods are introduced. In the second Section, Arithmetic Fourier Transform, a computationally less intensive approach to obtain Fourier coefficients is discussed. VLSI architectures used in the implementation of AFT are introduced in the third section. 2.1 Conventional Fourier Techniques for DSP The computation of DFT Discrete Fourier Transform, DFT, is a function used to convert a time domain signal into its frequency domain representation. DFT is widely used to analyze the frequency components contained in a sampled signal. The one dimensional Fourier Transform of a complex function is defined as It is also possible to generalize the Fourier transform into discrete structures such as finite groups. A new transform that uses only a finite number of samples of the sequence a(n) and computes a finite number of frequencies is defined as the Discrete Fourier Transform. 11

29 Given a sequence of N values of signal and time period T, the Discrete Fourier Transform is defined as: where = =2π/ (NT) Where =, k=0,1,..,n-1, Fast Fourier Transform The Fast Fourier Transform (FFT) algorithm is a method to compute the DFT more efficiently with respect to the number of complex calculations and speed of computation. It employs the method of separating the sequence into two sequences of total length divided by 2, consisting of even and odd indexed samples as shown below: Where m is an integer with values m= 0 to (N/2-1) 12

30 An important aspect of FFT is that its computation needs the results from the previous stage output. Stage (x) needs the outputs from the previous stage (x-1) for its computation. Similarly the stage (x-1) needs the outputs from stage (x-2) for its computation. Its computation can be performed in place in memory. FFT is a very efficient and fast method with regards to total number of computations required [9]. When comparing the number of computations required in DFT and FFT, DFT needs multiplications while FFT needs only N/2 multiplications for each stage which still reduces when the value of N is power of 2 to. Even though several methods for computing the FFT have been proposed, computing the FFT is time-consuming since the number of needed complex multiplications is proportional to NlogN [10]. Some of the shortcomings of FFT are as follows: - Use of complex number sequences in FFT makes it difficult in computations. - Most of the multiplications involved in FFT calculations are not real numbers Arithmetic Fourier Transform Number Theoretic Transform (NTT) is an algorithm similar to DFT which works with the modular arithmetic on integers instead of complex numbers. This method does not give the detailed observations required in terms of the spectral density of the transformed signal. Hence the use of NTT is restricted and by itself cannot be put into correspondence with DFT. 13

31 The Number Theoretic Transforms includes an algorithm called as Mobius Inversion formula which computes the DFT involving an entirely novel technique [6]. H.Bruns established the definition and algorithm of Mobius Inversion formula and it was practically implemented by Wintner in 1945 [7]. Later, Tufts and Sadasiv rediscovered the Mobius Inversion formula and renamed it as Arithmetic Fourier Transform (AFT) [4]. This algorithm was proven to perform the DFT with efficient area and time results. It involved less complex computations and included only additions and one multiplication of real numbers. When compared to FFT, the computational complexity of execution definitely reduces but the accuracy of obtained Fourier coefficients also reduces. This is the main drawback of using AFT when compared to FFT. 2.2 Comparison of Different Fourier techniques for DSP Motivation to AFT Arithmetic Fourier Transform is an alternative approach to FFT for computing the Discrete Fourier Transform of a sequence of length N. In order to find 2N+1 Fourier coefficients, the architecture discussed in this thesis requires few adders and only one multiplier [10]. One of the major advantages of the AFT over using FFT is its possibility in having non-uniformity in data dependencies i.e. non uniformly sampled data cases can be given as inputs to the Mobius functions. AFT requires 3N real multiplications and 3N 2 /2 real additions for computing 2N+1 Fourier series coefficients of a function. The complex multiplications and additions required in AFT are O(N) and O(N 2 ), respectively. The number of complex 14

32 multiplications and complex additions required in an N point FFT are O(NlogN) and O(N 2 logn), respectively. AFT is O(logN) times faster than FFT and is computationally less complex than FFT [Bharat]. As a result, the hardware requirements also reduce. AFT, unlike FFT, does not require the sine and cosine coefficients and its accuracy is not affected by the coefficient and rounding errors. 2.3 Arithmetic Fourier Transform Fourier Analysis Let us consider an arbitrary, real valued function A(t) with period T, that is exactly represented by Fourier series ideally with an infinite number of terms. To simplify the notation and functionality of the Fourier series analysis, let us consider it over N samples of the function. The Fourier series approximation of the signal is given as: (2.4) where a 0 is the zero th harmonic defined by If we shift the signal A(t) by a factor of αt, the equation becomes 15

33 (2.6) The Mobius function µ(n) is defined as follows [8]: (2.9) The conditions that are considered for Mobius Inversion Formula are [10]: - N is a positive integer - f(n) is a non-vanishing function in the interval 1<=n<=N - f(n)=0 for n>n Let us consider a function g(n) such that where [x] denotes the integral part of a real number. 16

34 2.3.2 Bruns Arithmetic Fourier Transform The Fourier coefficients can be derived from the equation (2.7) Let A(t) from (2.4) and S (n, α) be the nth average such that for the n values ranging from (n = 1, 2, 3, 4) with the corresponding m values ranging from ( m= 0,1,2,.., n-1) of shifted by the amount Here, n represents the index of coefficient being determined. The a n and b n coefficients of the Fourier series A(t) are computed by ) (2.13) An explanation for algorithm to compute 1-D AFT is given in [14]. This method has different computational complexities for the calculations of a n and b n Fourier coefficients. However, using Bruns original form of the AFT makes it possible to compute the even and odd coefficients, a n and b n, with a single matrix of similar complexity. Prasanna et.al [10] showed that using Bruns original form, the even and odd Fourier coefficients can be computed by equations (2.16) and (2.17) shown below. 17

35 A new average, the 2n th Bruns alternating average for 2n values (m=0, 1, 2..., 2n-1 ) of shifted A(t) is defined by where -1 < α < 1. as follows The coefficients c n (α) are given by the Mobius Inversion formula for finite series where B(2n,α) is the 2n th Bruns alternating average [12]. The a n coefficient can be calculated by α =0 and b n coefficient can be calculated by α = (1/4n). Therefore, The harmonic is given by 18

36 The Bruns original AFT uses the weighted, signed, averages of discrete values of A(t) where the weights were alternatively given as ± 1. Using the above equations for a n and b n Fourier coefficients, it is possible to develop a new extended AFT algorithm (equivalent to Bruns original method) whose architecture is more suitable for VLSI implementation. 2.4 Survey of AFT Architectures Systolic Arrays for the AFT Figure 2-1 shows the front end computation of the systolic array type implementation of the AFT. All the inputs come in an array and each of them is sent into the architecture. Zero mean corrections of the input values is done after which the input is sent into the demultiplexer. It makes use of an additional arithmetic unit to compute the mean of inputs which can in turn be computed by adding all the inputs together and then right shifting the end result by one bit [14]. The computation of Fourier coefficients is not possible with only one input. It has to consider other inputs coming into the architecture for the final computations. Hence, all the Fourier coefficients cannot be obtained at the same time. The computational complexities of computing a and b coefficients are different making it a non-modular architecture. 19

37 Figure 2-1: Systolic Array for AFT Modular Linear Array Architecture This method proposed by [10] is modular and area efficient VLSI architecture for computing AFT coefficients. It makes use of the processing elements (PEs) and I/O sequencing with the uniform/non-uniform data dependencies in the AFT computation and assignment of Mobius function values as shown in Figure 2-2. In order to find 2N+1 Fourier coefficients, two sets of N PEs each and a multiplier is used for computations [10]. Each PE has adders and uses registers for storage of the intermediate values. The most important contribution of this design is that it achieves O (N) speed up [15][10]. The multiplier is used to scale the Bruns alternate averages that are computed by the first set of N PEs. The scaling factors are stored in the external memory; Ms. After scaling the 20

38 outputs are multiplied by the respective Mobius values, -1, 0 or 1. The values -1, 0 and 1 are stored in an external memory location Mm. These group of the process elements take the scaled Bruns averages and the Mobius coefficients to compute the Fourier coefficients a n and b n according to equations (2.16) and (2.17). Algorithm explaining the same in terms of equations is shown in Figure 2-3. Since the VLSI architecture here is modular and has fixed bandwidth, it leads to a compact hardware implementation [10]. Compared to the DFT architectures in the literature [15][16], this architecture has significantly less area. Figure 2-2: Arrangement of Process Elements for the Computation of AFT [10] 21

39 2.4.3 Overview of VLSI Architectures for AFT The modular and area efficient VLSI architecture developed in [10] uses the Bruns alternate average algorithm, i.e., it uses weighted, signed and averaged discrete values of A(t) where the weights are alternatively ±1. The coefficients and are directly computed from (α) of the fundamental theorem. The difference in the formulae for and is with respect to the value of α.to calculate, a shift of α is needed in the alternating average B(2n,α). The value of the shift is equal to (1/4n) for Hence the coefficient is given by B(2n,0) while the coefficient if given by B(2n,1/4n). The Bruns B(2n,α) differs from S(n,α) in that it uses only the even samples. Considering even samples overcome the requirements for using zero-mean functions [6] as in the case of procedure followed by [14]. By using this architecture, computing and requires only odd l values for the terms in B(2nl, α), i.e. half the terms of type S(n, α) even though the number of operations required to calculate B(2nl, α) is twice that of S(n, α). Hence, for both cases, the total number of additions remains the same [12]. The number utilized in Bruns technique uses less number of multiplications for scaling. Finally, a considerable advantage in the Bruns AFT is that the zero-mean function is not needed as it is a time consuming process [10]. A comparative error analysis also done with the method confirms that the total amount of noise level reduction is 1.25dB. [6]. A Gaussian periodic function with zero- 22

40 order interpolations calculated using a computer simulation only shows a.92 db signalto-noise ratio gain. This makes it possible to compute a n and b n Fourier coefficients with hardware of same complexities. This algorithm does not require the use of complex Phase 1:// Computing B(2n,α) using zero-order interpolation For n 1 to N For m = 0 to 2n 1 Begin A [ A [ For n End 1 to 2N Phase II : Scaling: \\ Multiplication of scaling factors For n 1 to N Begin B B ; B B End Phase III:// Computing the Fourier coefficients using the Mobius Inversion formula For i = 1 to n For l = 1 to [ Begin B ; B ; end Figure 2-3: Arithmetic Fourier Transform Algorithm [10] multiplications as is the case for FFT algorithm. 23

41 The method in [10] thus has a better throughput than the other methods with respect to the computational complexities in finding the Fourier coefficients. Although the approach used in [10] has a computationally simple method of finding Fourier coefficients, the hardware used for the inner logic within the processing elements remains complex. In this work, the hardware used in the processing elements is made more regular and simple. The input stage is simplified and performs computations with every new input sample as explained in next chapter. 24

42 Chapter 3 Hardware Design for AFT Computation In the previous chapters different VLSI architectures for AFT computations to find the Fourier coefficients were discussed. The implementation details of an improved and modified architecture are presented in this chapter. A gate level implementation of the AFT algorithm is proposed and synthesized for a target Xilinx Virtex5 FPGA. 3.1 Arithmetic Fourier Transform Implementation The computation of AFT algorithm comprises of three major blocks as shown in Figure 3-1: 1) Alternate averages 2) Scaling stage 3) Mobius Inversion (computation of the coefficients). The first stage of alternating average block has four groups that process their respective averages once every eight input samples. The DC component (or DC coefficient) for the input data is represented as a 0 (Mean) in Figure 3-1. The alternate average values obtained for these eight inputs are given as inputs to the Scaling stage. In the scaling stage, mean,,,,, 25

43 ,, and represent the inputs to scaling stage coming from the Alternate average. The output from this stage is looped back to the alternate average stage and also given as input to the 3 rd stage called Mobius function. The mean value is scaled down by 1/8 since there are eight coefficients in this design that are being computed. In the 3 rd stage, Mobius Inversion, the final coefficients are computed using the equations for and as mentioned in (2.16) and (2.17). Detailed description of implementation of each stage with the hardware involved in it is discussed in the next few Sections Gate Level Description of the Algorithm The top-level of the entire Arithmetic Fourier Transform block is shown in Figure 3-2. Clock, Div_clock with higher frequency and reset signals are used to synchronize and initiate computations of the entire block. In addition to these, sampled input signal data for which the Fourier coefficients have to be determined is also part of the set of incoming signals. The design consists of four functional blocks, BasicArch 1-4, as shown in Figure 3-2 that are similar to each other. Computations for Fourier coefficients and are started in the BasicArch 1. Similarly, computations for and coefficients, 26

44 Figure 3-1: Data Flow Graph of the AFT Algorithm 27

45 and coefficients, and and coefficients, start in BasicArch blocks 2, 3, and 4, respectively. A new input data sample is provided to the block at regular intervals when it is enabled. A signal is sampled to number of data points and is given as input to the architecture. This input is selectively operated in the BasicArch blocks using the information stored in the select file shown in Table 3.1. Here a binary bit 1 represents that the sample input data is used for computation in the particular BasicArch block while a 0 represents the corresponding input sample is not utilized in the BasicArch block. The select file is one of the inputs coming into the design and which sets the first component of alternate average block of the design, a multiplexer. A description of the logic behind the values stored in select file is mentioned in Appendix C. Alternate average is computed in four individual but similar blocks referred as BasicArch 1-4 shown in Figure 3-3. The corresponding select file is shown in Table 3.1. The scaling stage and Mobius function computation stage form the second and third levels that follow the alternate average stage in determining Fourier coefficients. Detailed description of hardware implementation of each of the three stages is discussed in this chapter. 28

46 Figure 3-2: Block Diagram of the Top Level Architecture Table 3.1: Bit Values in Select File for the BasicArch Blocks 29

47 An analog signal is sampled at regular intervals and the binary converted values of these samples are provided as input to the architecture. On every clock pulse, a new data sample is given as input to the design for processing and computation of AFT. All the incoming data samples have a corresponding binary bit value in the select file. These bits along with the data values are given to the BasicArch blocks which initiate the computations of AFT. Figure 3-3: Input End of the Design Implementation of AFT 30

48 The total number of inputs coming to the architecture is not restricted and hence can be a flow of continuously incoming data. The select file pattern repeats itself after every 2N (=8) patterns, where 2N corresponds to the number of Fourier coefficients determined by the architecture, eight in this case Internal Operation of a BasicArch Block The BasicArch blocks contain many interconnected digital components as shown in Figure 3-4. These structures contain two multiplexers, a NOT gate, an XOR gate, two full adders, four flip flops, one demultiplexer, 6 registers and one subtractor. The inputs to the first multiplexer are the input sample and a stored zero value. Based on the bit value for the input sample from the select file either the sampled input or the zero is forwarded for further computations. This signal is then forwarded to another two-input multiplexer, that selects either the input or its 2 s complement for the alternate average operation. The select line to the second multiplexer is connected to an XOR gate as shown in Figure 3-5. One of the inputs to the XOR gate is 1 and the other input is looped back to its output through a flip flop that is gate-clocked by the bit read from the select file. Thus the XOR gate alternately generates a 0 or 1 whenever the select file bit for the block is 1. This alternate 0 and 1 values obtained are given to the select line of the second multiplexer. With this select input, the second multiplexer output alternates between the selected input data or its complement. Hence, we provide the sequence of data needed for alternate averaging to the adder of the BasicArch block. 31

49 Figure 3-4: Internal Components and Connections in a BasicArch The output from this multiplexer is given to the demultiplexer that keeps track of the computations of a and b coefficients. When the clock is high, additions for computing a coefficients are processed and when clock is low, additions for computing b coefficients are activated. Whenever, the data is ready in adders, it is added to the previous output from the accumulator. Hence the result in the adders keeps updating with every new input coming to the design. 32

50 Figure 3-5: XOR-Circuitry for Alternate Add and Subtract Logic Scaling of Alternate Average Values The values from the accumulator are passed down to the next stage of scaling once every eight inputs coming into the architecture. Scaling stage consists of two different components: shift registers and divider. In the scaling stage, the values from accumulators are divided by 1/2, 1/4, 1/6 or 1/8 for BasicArch blocks 1, 2, 3, and 4, respectively. Division of 1/2, 1/4, and 1/8 is easily implemented by using a 1-bit, 2-bit and 3-bit shift registers, respectively. The scaling of 1/6 is accomplished by using a 1-bit shift register ( shifting the binary string to right by one bit, performing a division by 2) followed by a divider ( for dividing by 3). The operation of division by 3 is shown in the flow chart in Figure 3-6 and state diagram in Figure 3-7. Divider The sequential process of the division algorithm is indicated by the flow chart in Figure 3-6 [18]. The control block uses a finite state machine to provide: shift and 33

51 subtract control signals, DONE and OVERFLOW signals. The state machine controller is initialized and stays in state ST_WAITLOAD until LOAD becomes 1. The registers are initialized with the values described below prior to the division. RegA Upper bits of dividend is equal to number of divisor bits RegB Divisor ( 3, 011 ) RegQ- lower bits of the dividend equal to dividend bits minus divisor bits QuoRemSign Signed bit of dividend XOR ed with signed bit of divisor Sequence Counter VHDL: Twice the number of bits in the divisor including the signed bit. The sign of the quotient (QUOTIENT) and remainder (REMAINDER) are always the same, i.e., QuoRemSign and is set when data is loaded. Initially, a divide overflow condition is tested by subtracting the divisor in RegB from the upper n bits of the quotient in RegA, where n is the number of bits in the divisor. If RegA is greater than or equal to RegB, that is, A_GE_B is a logic 1, an OVERFLOW condition exists and the state machine traverses to state ST_OVERFLOW and OVERFLOW is set to logic 1. 34

52 Figure 3-6: Flow Chart for the Division Operation OVERFLOW remains set until either a reset or subsequent load occurs. An OVERFLOW means the division would result in a quotient that requires more bits than there are bits in RegQ to hold it. If RegA is less than RegB, that is, A_GE_B is a logic 0, there is no OVERFLOW, so the process continues by shifting left RegA and RegQ, ready for the next test. The most significant bit for RegQ is shifted into the least significant bit of RegA. The flowchart, Figure 3-6, shows a loop which shifts left and either transfers RegA RegB back to RegA if A_GE_B = 1, or leaves RegA unchanged if A_GE_B = 0. 35

53 Figure 3-7: State diagram for the sequential division operation If A_GE_B is at logic 1, the divisor will go into the bits of the quotient or partial remainder in RegA. The corresponding quotient bit is, therefore, at logic 1 and is inserted into final quotient. If A_GE_B is a logic 0, the bits of the quotient or partial remainder in RegA is less than the divisor. The corresponding Quotient bit is therefore at logic 0 and is inserted into final quotient. This looping process continues until the counter is zero, that is, there has been as many shifts as there are bits in the divisor. When the counter reaches zero, the magnitude bits of the quotient resides in RegQ and the magnitude bits of the remainder resides in RegA. An important point to be considered while implementing a divider as part of the entire architecture is synchronization. The division needs 12 clock cycles to perform each step 36

54 of process mentioned in the state diagram. Hence the frequency of the clock for divider should be as high as 12 times the frequency of main clock coming as input to the AFT design Mobius Function for Determining Fourier Coefficients The outputs from the second stage of scaling are given as inputs to the last stage that is Mobius function. Its evaluation operates on the outputs from all scaled BasicArch blocks. Its execution in hardware makes use of only an adder and subtractor in order to perform multiplications with -1, 0 and +1 to compute the final Fourier coefficient. Hence the entire top level representation from its front to back end gate level diagram is shown in Figure 3-8. The Fourier coefficients also keep updating once with every new set of eight input samples. 3.2 Comparison of Proposed Method with Prasanna et al. Reduced hardware requirement and simplicity in the process elements for computing the coefficients is a major advantage of the proposed gate level implementation as compared to [10]. This is achieved mainly because the number of inputs considered for the computation is only one at a time unlike method in [10] where eight samples are considered at a time. Comparison of the hardware utilization in terms of processors and control units in [10] and proposed gate leveled digital design implementation is shown in Table

55 Figure 3-8: The Top Level Architecture in Detail 38

56 Table 3.2: Tabular Column for Comparing Different Architectures Parameter Prasanna et al. Proposed Method Adders 8 4 Registers O(N) = O(4) < O(N) (less than O(4)) Multipliers 1 1 Control signals Many Very few Area Utilization More Comparatively Less Power Utilization More Comparatively Less Delay Less Comparatively More The architecture in [10] is not flexible and depends on the size of input array. If the number of inputs per cycle of update of Fourier coefficients is changed, the architecture has to be re-designed entirely with change in the control circuitry for each of the process elements. The proposed method has a flexible architecture uses only one input that comes at a time. With the addition of few control signals, BasicArch blocks, and change in sequence of select bits the entire architecture can be easily modified. The number of adders required in Prasanna et al. is more than the proposed method, since each architecture needs only one adder to perform the addition operations. Total number of registers used for keeping track of intermediate variables and results in [10] is greater than the number of registers required in the proposed method. This is mainly due to comparatively complex PE and hardware design of AFT algorithm in [10]. This also results in more control signals. In this work, AFT algorithm is interfaced as DFT block on an FPGA to detect electromigration failure. Hence, the primary concern for developing this design is always to have a modular and area efficient design. EM failure can occur in any hardware but 39

57 builds over a very long period of time. Although the delay in obtaining the Fourier coefficients using the proposed method is greater than the delay obtained in [10], the impact on the system performance is minimal. In the next chapter the simulations, implementation and interfacing of the entire AFT algorithm is discussed in Matlab and VHDL. 40

58 Chapter 4 AFT Algorithm Implementations: Matlab and VHDL AFT involves frequency domain transformation of signals. Therefore, consideration of sampling and representation of the input signal is very important. In this work, sampled values of voltage signals obtained from circuit simulations are used to mimic the signals within FPGA. These sampled analog values are then converted to binary digital values and provided as input to the architecture implemented in Matlab and VHDL to obtain the Fourier coefficients. In this chapter, the details of the Matlab and VHDL coding implementation are shown along with the comparison of the results. 4.1 Different Methods Computed to Determine Fourier Coefficients Using Arithmetic Fourier Transform Figure 4-1 shows the work done in computing the coefficients using different approaches in implementing and verifying functional correctness of the AFT algorithm. 41

59 This Figure is divided into three main parts. The left most part gives brief description of the AFT algorithm. Figure 4-1: Overall Approach for Coefficient Comparison and Validation 42

60 In the middle part, Matlab is used to implement the AFT algorithm by directly computing equations 2.16 and 2.17 in order to determine the Fourier coefficients [6, [10] and [14]. The inputs to the Matlab code are sampled analog voltage values of the signal for which these equations are computed directly from stage to stage. Hence the Fourier coefficients obtained here are analog in nature. In the third part, the results of Fourier coefficients from the hardware implementation of algorithm in VHDL as described in last chapter are obtained. The final coefficients thus obtained are binary in nature. In order to validate the results obtained from the proposed method of hardware design, binary values of the Fourier coefficients obtained in both the methods (Matlab and VHDL) are compared and validated. In this chapter, set of input values as shown in Figure 4-2 is taken as example for which the Fourier coefficients are determined Figure 4-2: Input Data Used as an Example to Compute Fourier Coefficients 43

61 4.2 MatLab Implemented Coefficients from Direct Equations of AFT Outline Code and Explanation: The pseudo code shown in Figure 4-3 is implemented in Matlab to calculate the Fourier coefficients directly from the equations. Fourier coefficients obtained for the set of input data in Figure 4-2 are given in Table 4.1. Table 4.2 gives the binary form of the obtained coefficients in Table 4.1. For n=1:4 For m=0:2n-1 Alt_avg(n) =... End alt_avg(n)=alt_avg(n)*1/2n; For l=1:2: (N/n) mob_fn(n)= end end Figure 4-3: Pseudo-Code for Direct AFT Implementation Using Equations Table 4.1: Coefficients Obtained from Matlab Implementation a Coefficients b Coefficients a 1 = = a 2 = = a 3 = = a 4 = =

62 Table 4.2: Binary Representation of Coefficients Obtained from Matlab Implementation a Coefficients b Coefficients Xilinx ISE Tool Implemented Coefficients Using VHDL: Figure 4-4: Schematic Representation of VHDL Program for AFT Implementation The FPGA implementation of AFT algorithm in VHDL is purely digital as explained in Chapter 3. To test and verify the functionality, the binary form of sampled input signals values are written into a text file. This stored value in the file is then read by the VHDL model as input. At regular intervals, a new value is read and fed into the design. 45

63 4.3.1 Outline Code and Explanation: A pseudo code for BasicArch computing the alternate average which includes different components is shown in the Figure 4-5 below. entity basicarch is generic( n:integer:=7); port ( input1, input0: in STD_LOGIC_VECTOR (n downto 0); Rambit: in STD_LOGIC; ); end basicarch; architecture Behavioral of basicarch is component badd generic( n:integer:=8); Port ( ); end component; component FF generic( n:integer:=8); Port (----); end component; component scal generic(n: integer:=8); Port(---); end component; component alter Port(-----); end component; signal s1, s2: std_logic_vector; signal s3: integer:=0; signal s4: integer:=0; Begin mux1: bmux generic map ( n=>7) port map (); not1: bnot generic map ( n=>7) port map (); mux2: bmux generic map ( n=>7) port map (); end Behavioral; Figure 4-5: Outline Code of AFT in VHDL In the pseudo-code of Figure 4-5, input1 and input0 represents the input signals and the variable rambit, binary bit, obtained from the select file. Badd is the adder 46

64 component, bmux is the multiplexer, scal is the multiplier, FF the flip-flop, alter the XOR gate and NOT gate etc. When implemented as hardware Figure 4-5 transforms to Figure 4-6. Figure 4-6: Top Level Architecture 47

65 The input signals coming to the top level of the architecture are binary data samples, select values from external file, clock and the reset signals. When this simulation is run for the given input samples, we obtain updated values of Fourier coefficients. The output signals coming out from the top level hold the final values of the Fourier coefficients. Figure 4-7 shows the timing diagram of Fourier coefficients obtained from implementation of AFT on Xilinx Virtex 5 FPGA using VHDL. Figure 4-7: Fourier Coefficients from AFT Implementation on Xilinx Using VHDL Table 4.3: Binary representation of coefficients obtained from Xilinx VHDL implementation of AFT a Coefficients b Coefficients Table 4.3 represents the binary form of the coefficients obtained from the VHDL implementation of AFT in Figure 4-6. The values in Table 4.2 and Table 4.3 on comparison with each other are found to be in agreement with each other. This validates the correctness of developed hardware architecture implementation of AFT. 48

66 4.4 Matlab Implemented Coefficients in Hardware Perspective The previous Sections have discussed about the implementation of Fourier coefficients both in Matlab and VHDL (hardware), but this Section discusses another approach in Matlab that executes the same algorithm of AFT, but from the hardware perspective. Syntactically, the equations for the computation of coefficients are presented in Matlab but the sequence of evaluation is similar to that executed in VHDL. The pseudo code for the same is shown in Figure 4-8(a). The inputs to this program are the integer form for the binaries that go as input to the hardware design of VHDL implementation. Hence, the results from this approach are the coefficients presented in the form of integers. The Matlab code of this implementation is given in Appendix. The coefficients thus obtained are directly comparable to the hardware VHDL implementation Outline Code and Explanation: For each new input sample read from the stored file the column col_in, the index of data, is incremented. The binary bits corresponding to the particular col_in from the select file, shown in Table 4.4, are used along with sampled input. 49

67 Table 4.4: Binary Select File The change in sign of the adder to perform alternate additions and subtractions in the computations of a and b coefficients are taken care by the variables fsgna and fsgnb. As mentioned in the select file diagram, the first two rows correspond to the computation of and Fourier coefficients, the 3 rd and 4 th row correspond to the computations of and coefficients, 5 th and 6 th rows for and computations and finally 7 th and 8 th rows for and computations. With each new data, a next column of select file is used. The select file can be treated as circular buffer of size 8.,,, and so on are the representations of single binary bits. Times is a variable which counts the number of cycles run in order to complete all the finite data coming in. and give the number of rows and columns of the select file. Figure 4-8(b) gives the 50

68 integer representation of binary Fourier coefficients computed in lines of hardware implementation in Matlab for a given set of data. Input=[a1 a2 a3 a4..]; Row=1:r1; Column=1:c1; Sel_val=[a11 a12 a13 a14 a15 a16 a17 a18 a21 a22 a23 a24. a31 a32 a33.. -]; While col_in <= no_inputs while col <= 8 row =1; if row == 1 if sel_val (row,col)== else end end if row == End If col > times=times+1; End (a) if times==cross_times col_in = cross_input_vals; end (a) (b) Figure 4-8: (a) Outline Code of AFT Implementation (b) Computed Fourier Coefficients 51

69 4.5 Extension of Design: 16 Fourier Coefficients In this thesis, the implementation of the 8 Fourier coefficient single port input design architecture is discussed, developed, simulated and synthesized. The linear scalability of the hardware is demonstrated for a 16 Fourier coefficients in Figure 4-9. The hardware yields eight a and eight b Fourier coefficients. The entire structure of hardware remains the same for 16 coefficient design. The main operation is based on the binary select file of size 16x16 as shown in Table 4.5. In this case, the patterns repeat after every 16 input samples and the Fourier coefficients are updated once every 16 input samples. Table 4.5: Binary Select File for a 16-Port AFT Architecture 52

70 The hardware implementation for obtaining 16 Fourier coefficients is shown in Figure 4-9. There is a proportional increase in the number of BasicArch blocks. An additional divide by 5 and divide by 7 blocks are required in scaling stage in addition to shift registers. Figure 4-9: Hardware Utilization for the 16 Port Input Design 53

71 Chapter 5 Area, Time and Power Estimations of the Design A detailed explanation of the digital implementation in hardware is discussed in previous chapters. Hardware implementations involve tradeoffs between different parameters. In this chapter, the efficiency of the hardware implementations is analyzed in terms of three parameters: Area, Time and Power (ATP). Area, Time and Power Estimations of the Design Mapped on FPGA An estimation of FPGA hardware utilization rate (Area A), time of execution (T), and power consumption (P), at synthesis level is necessary to allow an efficient exploration of a large design space and to select the best possible implementation solution (algorithm vs architecture). In addition to these parameters an estimation of the accuracy of the implementation must also be considered. The primary concern for accuracy of a design is to look into the number of bits necessary to represent the input samples applied to the AFT architecture and its impact on the results. Increasing the number of bits used in processing can improve the accuracy of the output but it comes with an increased expense in one or more of the performance criteria of the implementation. 54

72 Interfacing AFT algorithm on FPGA using VHDL coding has few steps to be executed. The code describing the hardware is first simulated for functional correctness. After simulation, the design is implemented on targeted FPGA that involves translation, mapping, placing and routing. A detailed description of the design analysis with internal files carried among different stages is detailed in [17]. This chapter is divided into three Sections: Area analysis of the design, timing analysis and Power analysis. 5.1 Area Analysis Area of design is the total FPGA hardware resources utilized in its implementation. These resources vary with parameters such as the bit-width of the data, memory storage, number of components, placement and routing between the components, etc. The effect of the following input data widths is studied on the architecture: 8-bit wide, 9-bit wide, 10-bit wide, 12-bit wide and 16-bit wide. Total number of hardware resources in the resulting architecture in each case is evaluated and the results are tabulated for comparison. Table 5.1 compares the hardware resource utilization for the BasicArch block for inputs of different input bit-widths. The second column gives the total LUT-FF pairs used in the implementation of the component. In some of these pairs either LUT or FFs are not used. The third column lists number of unused FFs and the fourth column lists unused LUTs. The total count of the CLBs and other devices, as mentioned above, does not give an accurate area estimation on FPGA. During synthesis, placement and routing, the 55

73 design is automatically optimized by the Xilinx synthesis software, and this optimization process is not transparent to the user. As the design gets larger, more LUTs and flip-flops in a slice get utilized [19]. The resource utilization in absolute numbers and as a percentage of overall FPGA resources are described in Table 5.2. The slice logic distribution and utilization for entire AFT implementation is given in Tables 5.3 and 5.4 respectively. As expected, from the Tables 5.1, 5.2, 5.3 and 5.4, it is clearly seen that as the bit-width of input data is increasing, the hardware required for BIST on FPGA also increases. The BIST structure implementing AFT algorithm must occupy as few FPGA resources as possible so that rest of the FPGA resources can be used for different purposes. Table 5.1: Slice Logic Distribution of BasicArch Block on Xilinx Virtex 5 FPGA Architecture Total number of LUT-FF pairs Used Unused FF Unused LUT Fully Used LUT-FF pairs 8-bit /793, 60% 57/793, 7% 259/793, 38% 9-bit /806, 58% 63/806, 7% 268/806, 39% 10-bit /880, 60% 68/880, 7% 278/880, 38% 12-bit /964, 60% 78/964, 8% 298/964, 38% 16-bit /1118, 60% 99/1118, 8% 339/1118, 38% Thus, 8-bit architecture that uses less than 2% of total FPGA resources is selected in the final implementation. 56

74 Table 5.2: Slice Logic Utilization of BasicArch Block on Xilinx Virtex 5 FPGA Architecture Slice Registers Slice LUTs Number Used as Logic Slices 8-bit 316, 1% 736, 2% 736, 2% 9-bit 331, 1% 743, 2% 743, 2% 10-bit 346, 1% 812, 2% 812, 2% 12-bit 438, 1% 1019, 3% 1019, 3% 16-bit 877, 2% 1788, 9% 1788, 9% Table 5.3: Slice Logic Distribution of Top Level Block on Xilinx Virtex 5 FPGA Architecture Total number of LUT-FF pairs Used Unused FF Unused LUT Fully Used LUT-FF pairs 8-bit , 79% 48, 3% 207, 7% 9-bit , 67% 144, 7% 358, 37% 10-bit , 66% 157, 8% 384, 38% 12-bit , 64% 184, 10% 435, 37% 16-bit , 67% 226, 11% 551, 37% Table 5.4: Slice Logic Utilization of Top Level Block on Xilinx Virtex 5 FPGA Architecture Slice Registers Slice LUTs Number Used as Logic Slices 8-bit 255, 1% 1167, 6% 1167, 6% 9-bit 502, 2% 1397, 7% 1397, 7% 10-bit 541, 2% 1457, 7% 1457, 7% 12-bit 619, 3% 1561, 8% 1561, 8% 16-bit 877, 4% 1788, 9% 1788, 9% 57

75 5.2 Timing Analysis The maximum delay between an input and output ports of a combinational circuit consisting of logic gates (or between FF stages of a sequential circuit) is used for the time estimation, T. CLB delays, and wire delays are used to calculate the delay in each path. The critical path is the path that yields longest input to output delays. Timing simulation verifies whether the design runs at a desired speed for the device under worst case conditions or not. Xilinx ISE timing analysis identifies the worst case path delay after design is mapped, placed and routed for FPGAs. The timing summary in terms of minimum input arrival time before clock, maximum output required time after clock, and maximum combinational path delay are computed. The critical path can be obtained with the combination path delay from static timing analysis from post-placement and routing implementation. The gate delays also contribute to the path delay in the circuit and hence minimum and maximum gate delays are also given in Table 5.5 and Table 5.6. The timing delays are obtained based on the nominal delays of the hardware and routing resources utilized by the design. Tables 5.5 and 5.6 summarize the results of the timing analysis of the design for different architectures with varying input bit-widths for the Basicarch block and for the overall design. From the results it can be observed that the clock period minimum input arrival time and the maximum gate delay increase with the increase in the input data bit-width. The other parameters more or less remain the same with the increase in the bit-width. 58

76 Minimum Input arrival time before clock represents the maximum path delay from all primary inputs to the sequential elements in the design. Similarly, the maximum output required time after clock represents the maximum path from the sequential elements to all the primary outputs. The maximum combinational path delay is the maximum path delay from register outputs to register inputs. If the value for maximum combinational path delay does not determine clock period then it is represented as No path. Generally, a value in this column represents the maximum delay for signal propagation in the design, which when exceeded will result in unexpected behavior. Component: BasicArch Table 5.5: Timing Analysis of BasicArch Block on Xilinx Virtex 5 FPGA Architecture Minimum Period (usecs) Min. input arrival time before clock Max output required time after clock Max. combinational path delay Minimum Gate Delay Maximum Gate Delay 8-bit No path bit bit No path bit No path bit No path The minimum and maximum gate delays also shown in the table contributes to the timing details of the design. 59

77 Component: Top-Level Table 5.6: Timing Analysis of Top Level Block on Xilinx Virtex 5 FPGA Architecture Minimum Period (usecs) Min. input arrival time before clock Max output required time after clock Max. combinational path delay Minimum Gate Delay Maximum Gate Delay 8-bit No path bit bit No path bit No path bit No path Power Analysis Power consumption, P, is another critical performance criteria. Total power consumption is based on a number of factors such as clock frequency, activity rates, design density (number of interconnects), logic block and interconnect structure, power supply voltage levels etc. In this work, the power estimation for a design is obtained from the XPOWER Estimator. The estimated power thus computed is the sum of static power (quiescent power) and dynamic power. Quiescent power is the power consumed in the absence of signal transitions and is depends on the FPGA family being used, Xilinx Virtex 5 FPGA in this case. The dynamic power on the other hand, is the sum of logic power, IO power, clock power and signal power and is based on the architecture used to implement the design [19]. The voltage source information inthe Table 5-7 displays the power (Vccint Power) drawn from each voltage supply along with dynamic current (Icc). The total 60

78 dynamic power is also shown in the last column. The power computation for design is tabulated for all architectures of 8-bits, 9-bits, 10-bits, 12-bits and 16-bits input lengths in Table 5-7. As the bit-width of input increases more dynamic current flows in the design which also increases the total dynamic power consumption of the architecture. The power estimation of a design is computed only after it is placed and routed on the FPGA. [20]. Table 5.7: Power Estimation of Top Level Block on Xilinx Virtex 5 FPGA Architecture Icc (A) Vccint Power (Watts) Total Quiescent Power (Watts) Total Dynamic Power (Watts) 8-bit bit bit bit bit In this chapter, an analysis on hardware utilization, timing analysis, and power consumption of the architecture is presented for different input bit-widths. An architecture that computes with larger bit widths usually results in more accurate computations. At the same time, an increase in input length also increases the hardware utilization and power consumption. Since electromigration is a fault that takes a long time to manifest, the focus of implementation is to detect EM faults with minimum hardware resources. Therefore AFT architecture using 8-bit inputs is used in the implementation. 61

79 In the next chapter, methods of identifying the EM fault using the 8-bit AFT hardware is presented. 62

80 Chapter 6 Identification of Electromigration Failures This chapter is divided into three major Sections. The first Section introduces the electromigration fault and the formation of Weak 0 and Weak 1 states. The second Section details the fault model used in this thesis in order to identify the potential electromigration fault. The use of AFT hardware in the identification of the possible electromigration failure in the circuit is explained in Section three. 6.1 Electromigration (EM) The phenomenon of electromigration is caused by the mass transport of metal atoms due to shift in momentum by electron currents especially under high current densities and high temperature. The first failure is the formation of vacancies leading to voids as a result of metal migration. The second failure is the formation of shorts between different layers in the integrated circuit due to the accumulation of migrating ions. The migrating ions exert pressure at a site and breaking the passivation layer between the metal layers [2]. 63

81 6.1.1 Motivation With the miniaturization of components in VLSI circuits, there is a steady increase in current density of interconnects [24]. In FPGAs, interconnects occupy up to 70%-80% of FPGA area [2]. For the given size of a chip, miniaturization reduces the device and interconnects size but also increase in number of components. The miniaturization also results in interconnect structures that are tall and thin resulting in increasing coupling capacitance between the interconnect wires. This results in increased current densities in the interconnect as compared to prior technology generations. With passage of time, the increased current densities in the metallic wires on the chip results in migration of metal atoms and the interconnect performance starts to deteriorate. This method of failure is termed as failure due to electromigration (EM). Even before occurrence of fault, the degradation of the wire due to electromigration ultimately leads to weak 0s and weak 1s [25]. The weak 0s and weak 1s can lead to faulty temporal behavior at the output end of the particular path Weak 0s and Weak 1s: In digital design, the logic circuits are designed to source and sink two types of signals called high (binary 1 ) and low (binary 0 ). Practical design considerations result in neither the high being at full voltage supply nor the logic low at zero voltage. Some possible sources for these variations include threshold variations, capacitive/inductive coupling in the circuits, switching noise, etc. For example, in CMOS logic gates operating with a 2V supply voltage, acceptable voltage levels range 64

82 from 0V to 0.49V for logic low and from 1.49V to 2V for logic high as shown in Figure 6-1. Due to electromigration and resulting local heating, the wire melts down resulting in weak 0s and weak 1s [22]. Weak 0s and Weak 1s are due to voltage and current drops in the circuitry. In this work, the Arithmetic Fourier Transform is used as the BIST circuit to identify the EM faults. The signature values of Fourier coefficients for a non-faulty circuit are stored in ORA. The input values are read from the fault-prone circuit location under test. The deviation of the resulting Fourier coefficients from AFT architecture from stored signature values is used in the identification of electromigration fault. V dd = 2V V ohmin = V High Weak logic levels V olmax = 0.494V Low 0.0V Figure 6-1: Logic Levels for CMOS Logic Family 65

83 The parameters shown in Figure 6-1 are defined as follows: V ohmin = Minimum output voltage in the High-state. V olmax = Maximum output voltage in the Low-state. As a part of work in this thesis, a model for the driver circuit in the interconnect of an FPGA is developed. It consists of an inverter representing the driving stage as shown in Figure 6-2. The entire circuit is modeled based on 90 nm process parameters, similar to the process used in the Xilinx Virtex 5 FPGA. Although the output voltages of the Virtex-5 FPGA can be either 3.3V or 5 V, the internal circuitry operate on a 2.7 V power supply. Mbreakp and Mbreakn are the two transistors modeled using BSIM4 MOSFET models. They use typical 65 nm technology parameters obtained from Predictive Technology Modeling resource [26]. The models for Mbreakn and Mbreakp used in the circuit are shown in Appendix B. In the interconnect wire, the formation of electromigration leads to change in the characteristics of the interconnect wire. This is depicted by a resistor mimicking the behavior of the EM formation. Depending on the type of potential electromigration fault, a short to the power/ground bus or an open in interconnect is controlled through the value of the modeled resistor. SPICE simulations are used to obtain the values of output voltages in the presence of the EM faults. Discrete sampled values of the voltage are then applied to the implemented AFT module to detect the electromigration fault. 66

84 2.7V Input 0V 2.7V Output Figure 6-2: Ideal Inverter Circuit with the Corresponding Waveforms 6.2 Fault Model Development: A resistor in introduced between the power supply and fault location of the circuit developed above. The included resistor(s) model the effects of EM short to the power supply. This short is present independent of the input signal to the driving inverter. When the input to the inverter is high 1, the NMOS transistor is ON and PMOS transistor is 67

85 OFF. In a fault free circuit the output voltage would be at logic high voltage value. In a faulty circuit the presence of the EM resistor provides a continuous current path from power supply to the ground via the NMOS transistor resulting in a degraded output voltage level. The transient and steady state values of the output voltage will depend on the EM resistance. When EM resistance is large, its effect on overall output response is minimal. As the interconnect degrades due to EM, its effects are modeled with reduced values of the short resistance. The steady state value of logic low voltage 0 starts to increase with decreasing value of modeled EM resistance resulting in Weak 0. Alternately, an EM short to ground can be represented by placing a resistor between fault location on interconnect and ground. As the resistance value goes down with increasing EM, the steady state and transient output voltage values gets affected in transitions towards logic high. This results in degradation of logic 1 value resulting in a Weak 1 circuit. The output responses obtained from circuit simulations are provided as input to the AFT circuit and compared with fault free signatures to identify the potential failure due to electromigration. EM failure not only makes the output voltage weak but also provides a path from power supply to ground resulting in significant power dissipation in the FPGA. These potential failure or performance degradation can be avoided by earlier detection of EM failure in interconnect. Alternate paths for routing can be used in this case using redundant FPGA resources extending the lifetime of the FPGA. In FPGA, the CLBs are interconnected with each other by wiring resources either directly or through the switch resources. The programmable switch matrices help in 68

86 directing routes to the signals carried by the wires (interconnects) between CLBs. Depending on the distances between source CLB and the destination CLB and also the type of signal carried, the length of interconnects vary. As interconnect is basically an electrical wire joining the two CLBs, it comprises of internal resistances and capacitances that depend on the length of interconnects. The interconnect parameters are also based on the short, medium and long interconnect models from [26] Estimation of Net Length, Resistance and Capacitance of Interconnects: In the case of Xilinx FPGAs devices, the wires are tagged as unidirectional. L represents the average length of a side of CLB and surrounding wiring space. In Virtex-5 FPGA, 22% have =2, 66% of the wires have =6, and 13% have =24 that will be referred as 2L, 6L, and 24L interconnects respectively. [5]. The interconnects of length 2L are assumed as short wires, 6L as medium wires, and 24L as the long wires. For different lengths, the values of the parameters like resistances and capacitances vary which are respectively used to develop different models. The identification of EM occurrence for different cases of 2L, 6L and 24L is individually detected for both Weak 1 and Weak 0 conditions [28]. Net-Length (L) From [26], an average area of CLB for Virtex 5 FPGA is taken to be 4209 μ. This implies that the net length is square root of Therefore, the net-length (L) is equal to μm. The values of 2L, 6L and 24L representing the local, intermediate and 69

87 global interconnects respectively, are computed to be approximately 130 μm, 389 μm and 1557 μm. The resistor and capacitor values of an interconnect depend on the length of the interconnect. Resistance and capacitance values are determined based on the 65 nm process interconnect information from [26]. The inverter circuit is modified to include interconnect load effects as shown in Figure 6-3. R1 and R2 form the distributed resistances of interconnects whereas C1, C2 and C3 represent the distributed interconnect capacitance. C4 is the load capacitance modeled as FO5 i.e., with a fan-out of 5 inverters. Figure 6-3: Inverter Circuit with the R and C of Interconnect Modeled Resistance (R): The electrical resistance of a wire is expected to be greater for a longer wire, less for a wire of larger cross Sectional area and is expected to depend on the material of which wire is made. The equation representing the same is given by 70

88 R= l/a where, l = the total length of the wire (2L, 6L or 24L in this work) A= cross Sectional area of the wire (width of the wire * thickness of the wire) = Resistivity of copper interconnect (=1.7x ) The values of width and thickness are determined from [26] for the respective technology used. Capacitance (C): Wire has capacitance per unit length to layers above and below it. Hence, it is similar to parallel plate capacitance which is given by the equation: C = εa/d where ε=k.ε0, k being the dielectric constant (value is taken from 65nm process of [26] ) ε0 is the permittivity in free space = 8.85 x F/m A= Area of the interconnect = L (net length) * thickness of interconnect d= Distance between two interconnects placed in parallel. For three values of net lengths, we have three different values for capacitances. 71

89 The respective sets of resistances and capacitances are put together to form the final circuitry. These circuits are simulated for implementing an application of AFT algorithm. All the three interconnect lengths with corresponding resistance and capacitance values are shown in Table 6.1. Table 6.1: Resistances and Capacitances of Different Lengths of Interconnects Length of the Interconnect Net- Length R1 (Ohm) R2 (Ohm) C1 (Farad) C2 (Farad) C3 (Farad) C4 (Farad) 2L μm L μm L μm Details of Weak 0 and Weak 1 in the Test Circuit: To study the effects of weak 0 operation, an additional resistor, RL, is introduced between the power supply and driver circuit as shown in Figure 6-4 to a normal fault free circuit. The resistor, RL, that models EM effects, resembles a fault free circuit when its value is infinity. As the value of RL decreases, the potential drop across RL affects the circuit to behave in an undesired manner. Similarly a resistance connected between the output and ground is used to model the effects of electromigration for Weak 1 case as shown in Figure 6-5. The value of the resistance, RL is varied in PSPICE simulations in Figures 6-4 and 6-5 to obtain the response of the circuit for different levels of electromigration effect. 72

90 Figure 6-4: Inverter Circuit with Weak 0 Fault Modeled in it Figure 6-5: Inverter Circuit with Weak 1 Fault Modeled in it 73

91 6.3 Identifying Presence of EM: In the fault free circuit, the response of inverter circuit is obtained as shown in Figure 6-6. For larger values of RL (in faulty circuits), there is no impact on the circuit behavior since there will be no current flowing through the high resistance path. When the RL value decreases, the current flow through RL, deviates the output voltage levels from a fault free circuit. Procedure for Identification For a fault free case, the output wave is as shown in the Figure 6-6. The sampled output voltage values obtained from the SPICE simulations are given as inputs to the AFT architecture which computes the Fourier coefficients. The set of Fourier coefficients,,,,, and obtained from the implemented AFT circuit for fault free circuit are set as the signature values that will be used as reference. The sampled analog signal cannot be directly given as inputs to AFT circuit. An analog to digital converter must be used between the captured analog data and the digital block of AFT. An in-built ADC in Xilinx FPGAs is not currently available. Inbuilt data conversion circuits are currently under development by FPGA manufacturers [30]. One such product having an integrated ADC on FPGA is SmartFusion that is it has a programmable analog interface in-built in the FPGA [34]. In a faulty circuit, Weak 0 or Weak 1, the value of the resistor i.e. represents the level of electromigration in the circuit. The value of is inversely proportional to the amount of electromigration affecting the circuit performance. For a given input to the circuit, the is varied from a 74

92 high to low resistance values resulting in different output responses. The Fourier coefficients for faulty circuits are tabulated. Figure 6-6: Output Waveform for a Fault Free 2L Interconnect Inverter Circuit The next step in the process for identification of EM is comparison with the signature (fault fee circuit) Fourier coefficients. Equation (6.1) shown below computes the percentage deviation of the faulty Fourier coefficients with respect to the fault free coefficients. The coefficients with larger percentage deviation are used as signatures to identify potential EM failures. (6.1) Consequences of EM Occurrence: In case of Weak 0 with decrease in the RL value the logic LOW level of output voltage raises above 0 V. If the resulting logic LOW voltage level exceeds the threshold 75

93 voltage, Vth, then the NMOS transistor of the buffer circuit connected at the end of interconnect will operate in an undesired manner resulting in circuit failure. In case of Weak 1, with decrease in the RL value the logic HIGH level of the output voltage decreases from V DD to a lower value. If the voltage level falls below (V DD -V thp ) the PMOS transistor of the buffer circuit at the end of interconnect turns ON resulting in circuit failure. Figures 6-7, Figure 6-8, and Table 6.2 show the circuit diagrams, corresponding output waveforms, and AFT coefficients for fault free circuit. The tabulated results are the signature Fourier coefficient values which are used for comparison with the Fourier coefficients obtained from the faulty circuits, Weak 0 and Weak Fault Free Figure 6-7: Fault Free Inverter Circuit for 2L Interconnect 76

94 Figure 6-8: Output Waveform of Fault free Inverter Circuit of 2L Interconnect Table 6.2: Fourier Coefficients of Fault Free Inverter Circuit Signature Values Input type Falling Input Rising Input From Figure 6-8, both low and high voltage levels are at 0V and 2.7V as provided to the inverter circuit. In Table 6.2, the Fourier coefficients for the falling and rising inputs are also mentioned. As stated previously, these coefficients are now considered as reference values and are used for comparison with coefficients from faulty cases Weak 0: In the Figure 6-9, the inverter circuit has an additional resistor RL across the PMOS mimicking the EM fault. 77

95 Figure 6-9: Inverter Circuit with 2L Interconnect Modeled with Weak 0 Fault The values of RL used in the circuit are represented with different colored waveforms in the output for each value of RL as shown in Figure The obtained Fourier coefficients from the simulation of above circuit are shown in Table 6.3. Figure 6-10: Output Waveform of Inerter Circuit with 2L Interconnect Modeled for Weak 0 78

96 Table 6.3: Fourier Coefficients of Weak 0 Inverter Circuit of 2L Interconnect Input type Falling Input Rising Input Weak 1: A resistor RL mimicking the EM fault is introduced in the circuit as shown in Figure The corresponding waveforms for the range of RL values is shown in the Figure 6-12 and corresponding Fourier coefficient values obtained are mentioned in Table 6.4. Figure 6-11: Inverter Circuit with 2L Interconnect Modeled with Weak 1 Fault 79

97 Figure 6-12: Output Waveform of Inverter Circuit with 2L Interconnect Modeled for a Weak 1 Fault Table 6.4: Fourier coefficients of Weak 1 inverter circuit of 2L Interconnect Input type Falling Input Rising Input After the Fourier coefficients for faulty cases are noted, these values are compared with the signature values of Fourier coefficients obtained from the simulation of faultfree circuit of an inverter. Table 6.5 summarizes all the coefficients for different cases presented. It also shows the percentage deviation of coefficient values from the signature coefficients for both Weak 0 and Weak 1 cases. The signature coefficients obtained for falling and rising inputs are compared with the coefficients obtained for respective inputs in Weak 0 and Weak 1 cases individually. 80

98 Table 6.5: Comparisons and Deviations of Coefficients with Prominent Differences Input type Signature Falling input Rising Input Weak 0 Falling input Rising Input Percentage Deviation Falling input 60% % Rising Input - 80% % 80% - Weak 1 Falling input Rising Input Percentage Deviation Falling input 60% Rising Input - 80% % 80% - - The coefficient values that have small percentage deviations are discarded but the ones with large deviations are considered for comparison with signature values. For example, if the deviation of coefficient for falling inputs is greater than 60% the signature value then there is a possible occurrence of EM failure. Similarly, for rising inputs if the deviations of, and coefficients is greater than 80%, 67% and 80% respectively then there is a likely EM failure.. The identification of the electromigration is hence made possible for the transient responses of an inverter circuit using Arithmetic Fourier Transform. Identification of EM occurrence is also simulated using VHDL in Xilinx Virtex 5 FPGA by having the signature values stored in the registers. Signals shown in Figure 6-13 represent the process of identification of EM fault. Signals a_signature and b_signature hold the signature values and the signals a_coefficients and b_coefficients hold the actual coefficients obtained for a faulty circuit. Signals em_iden_a and em_iden_b are single bit signals which go high when the percentage 81

99 deviation of the values of Fourier coefficients obtained for a faulty circuit equals or becomes more than the cut-off deviation with respect to the corresponding signature coefficients. Figure 6-13: VHDL Implementation for the Identification of EM Hence, a complete analysis of EM identification is done in detail as an application of Arithmetic Fourier transform for and interconnect of length 2L. Similar analysis is also done for 6L and 24L interconnects. These results for the same are presented in the Appendix A. 82

100 Chapter 7 Contributions and Conclusions This chapter summarizes the contributions and conclusions of the work done in this thesis. Some future research prospects are also provided. 7.1 Contributions In this research, the development of a frequency-domain implementation of the BIST structure for detecting electromigration failures in the interconnects of FPGAs is presented. The main contributions of this thesis are: Implementation of a gate level Arithmetic Fourier Transform architecture to compute the Fourier coefficients on a Xilinx Virtex 5 FPGA. Development of an area efficient and modular hardware design using Matlab and VHDL coding techniques. Analysis of area, time, and power for the proposed architecture with different lengths of input data. Implementation of the proposed design for identifying those interconnects which are prone to electromigration failures. 83

101 Development of EM fault signatures for short, medium, and long interconnects in FPGAs using sample input data obtained from OrCAD PSPICE simulations. Conclusions The goal of this research to develop a modular and efficient architecture for AFT has been achieved with its implementation in identifying the potential EM faults in Xilinx Virtex 5 FPGA interconnects. Area, delay and power estimations for the AFT architecture mapped on the FPGA were analyzed for different input bit-widths: 8-bits, 9- bits, 10-bits, 12-bits, and 16-bits. It was found that the architecture with 8-bit of input data length was sufficient to detect the potential failures due to electromigration. This finding led to a design with corresponding utilization of area, time and power being minimum. The cut-off values of percentage deviations obtained from this work can be considered as reference values for the determination of electromigration faults in FPGAs. 7.2 Future Work In this work, AFT technique has been used for identifying electromigration failures only. However, this technique can be extended to identify other types of faults that are time dependent and tend to occur as time progresses. Based upon the mapping and placement of different applications on FPGA, different portions of the FPGA exhibit varying switching currents and leakage currents. Consequently, different portions of the FPGA age differently when implementing the 84

102 same design for a long period of time. Accelerated aging phenomena is dependent on different factors such as supply voltage, temperature, switching activity, resulting current in the devices, the state of the gates, and leakage currents [36]. Some faults like Hot-Carrier Effect (HCE), Time-Dependent Dielectric Breakdown (TDDB), Thermal Cycling, Stress Migration, and Negative Bias Thermal Instability (NBTI) also aggravates with age of the components or the circuits. Using the AFT method of fault identifications, presence of some of these faults can also be detected on FPGAs by considering the samples of data and variations in the parameters like threshold voltage values. This would however require the generation and storage of appropriate signatures to detect these faults.. 85

103 References [1] David Malintak, Basics of FPGAs design, A supplement to Electronic Design Automation editor, December 4, [2] B. Vasudevan, M. Niamat, M. Alam, and S. Vemuru, Analysis and test of electromigration failures in FPGAs, Circuits and Systems (ISCAS), pp , Paris, May 30, [3] Virtex-5 FPGA Configurable Logic Block, User guide, UG190 (v5.3) May 17, [4] B.F. Dutton, and C.E. Stroud, Built-In Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs, Proc. IEEE Southeastern Symposium on System Theory, pp , May [5] P.B. Minev, and V.S. Kukenska, The Virtex-5 Routing and Logic Architecture, Annual Journal of Electronics - ET, pp , Sozopol, Bulgaria, 17 th Sept., [6] I.S.Reed, Donald W.Tufts, Xiaoli Yu, T.K.Truong, Ming-Tang Shih, and Xiaowei 86

104 Yin, Fourier Analysis and Signal processing by Use of the Mobius Inversion Formula, IEEE Transactions on Acoustics, Speech, and Signal Processing. Vol.38. No.3, pp , March [7] A. Wintner, An arithmetical Approach to Ordinary Fourier Series, privately published monograph, pp. 29, Baltimore, [8] D. W. Tufts, and G. Sadasiv, The Arithmetic Fourier transform, IEEE ASSP Magazine, pp , Jan [9] C. D. Thompson, Fourier transforms in VLSI, IEEE Transactions on Computers, vol. C-32 no. I I, pp , [10] H. Park, and V. K. Prasanna, Modular VLSI Architectures for Computing the Arithmetic Fourier Transform, IEEE Transactions on Signal Processing, Vol. 41, No. 6, pp June [11] N. Venkateswaran, and K. Bharath, "Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level, Proc. DELTA, pp.15, Second IEEE International Workshop on Electronic Design, Test and Applications, Washington, [12] I. S. Reed, M-Tang Shih, T. K. Truong, E. Hendon, and D. W. Tufts, A VLSI Architecture for Simplified Arithmetic Fourier Transform Algorithm, IEEE Transactions on Signal Processing, Vol. 40, No. 5, pp , May,

105 [13] D. W. Tufts, and G. Sadasiv, The Arithmetic Fourier transform, IEEE ASSP Magazine, pp , Jan [14] B. T. Kelly, and V. K. Madisetti, Efficient VLSI Architectures for the Arithmetic Fourier Transform (AFT), IEEE Transactions on Signal Processing, Vol. 41, No. 1, pp. 365, January [15] S.Y.Kung, VLSI Array Processors, Prentice-Hall, [16] N.Ling, and M.A.Bayoumi, Algorithms for high speed multidimensional arithmetic and DSP systolic arrays, in Proc. Int. Conf. Parallel Processing, pp , [17] Xilinx Virtex-5 FPGA Synthesis and Simulation design guide [18] Douglas J. Smith, HDL Chip Design, Doone Publications, [19] L. Deng, K. Sobti, Y. Zhang, and C. Chakrabarti, Accurate Area, Tme and Power models for FPGA-based Implementations, International Conference on Acoustics, Speech, and signal Processing (ICASSP), Las Vegas 2008, March [20] L. Deng,, K. Sobti, Y. Zhang, and C. Chakrabarti, Accurate Models for estimating area and power of FPGA implementations, Acoustics, Speech and Signal Processing, pp , March

106 [21] Understanding the Timing Analysis Analysis/basic-timing-explain/td-p/63549 [22] Understanding the Synthesis Report, [23] FPGA design Flow, [24] K. Banerjee, A. Mehrotra, A. S. Vincentelli, and C. Hu, On thermal effects in deep sub-micron VLSI interconnects, Proceedings of the Design Automation Conference (DAC), pp , New Orleans, Louisiana, [25] N. Venkateswaran, S. Balaji, and V. Sridhar, Fault Tolerant Bus Architecture for Deep submicron based Processors, ACM SIGARCH Computer Architecture News, Vol. 33, No. 1, pp , March, [26] Predictive Techology, ptm.asu.edu [27] V. Betz, and J. Rose, Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect, IEEE Custom Integrated Circuits Conference, pp , [28] V. Garg, V. Chandrasekhar, M Sashikanth, and V. Kamakoti, A novel CLB architecture and circuit packing algorithm for logic area reduction in SRAMbased FPGAs, Proceedings of the IEEE ASP-DAC Conference, pp , [29] Analog to Digital Converter in Xilinx FPGA 89

107 [30] Details of ADC in Xilinx platform Documentation _adc.pdf [31] J. P. Uyemura, Introduction to VLSI circuits and systems, John Wiley & Sons, Inc., [32] Xcell Journal, Xilinx, Inc., Issue 59, Fourth quarter, [33] Tips for converting level 49 HSPICE models to Level 7 PSPICE models, [34] Link to Smartfusion FPGA [35] R. W. Knepper, Circuit characterization and performance estimation, SC571, BU Publications, chapter 4, pp. 1-22, [36] S. Srinivasan, R. Krishnan, P. Mangalgiri, Y. Xie, V. Naraynan, M. J. Irwin, and K. Sarpatwari, Toward Increasing FPGA Lifetime, IEEE Transactions on Dependable and Secure Computing, Vol. 5, Issue 2, pp , April

108 Appendix A Analysis for 6L and 24L Interconnect Lengths Detailed explanation of EM analysis for circuits with interconnects length 2L is discussed in chapter 6. The other two cases of lengths 6L and 24L are discussed here. It is to be noted that in the tabular columns mentioned in Appendix A, purple color represents the coefficients used for the identification of potential EM occurrence. Brown color and green color values are mentioned for the coefficients that forewarn the EM occurrence and can also be used as the flags for its identification. A.1 6L Interconnects presented. Following the analysis of the two different faults Weak 0 and Weak 1 are A.1.1 Weak 0 The circuit diagram of the inverter circuit with EM fault introduced into it with a resistor mimicking it is shown in FigureA-1. This circuit is developed in the same manner as that of the circuit with 2L length interconnect as mentioned in Chapter 6. The output waveforms obtained for different values of are also shown in FigureA-2. 91

109 Sampled values of the output waveform are given as inputs to the AFT block and the final Fourier coefficients are determined and tabulated as shown in Table 1. Figure A-1: Circuit Diagram for Weak 0 fault with 6L interconnect Figure A-2: Waveform Obtained after Simulating Weak 0 Circuit 92

110 Table A.1: Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-off Values for Determining the EM Fault in Weak 0 Circuit with Interconnects of Length 6L Rising Input Falling Input Signature Values of Coefficients Obtained fourier Coefficients Absolute % Deviations Signature Values of Coefficients Obtained fourier Coefficients Absolute % Deviations Absolute percentage deviations for rising and falling input cases are computed and identification of EM fault is analyzed. In case of the rising input, all the coefficients with their deviations more than 50% with respect to the signature value are considered for identifying the potential EM occurrence. Similarly, for falling input, only coefficients and are used for the identification since they have deviations of more than 50% with respect to the signature coefficients. Hence any path detected to produce Fourier coefficients with more than 50% of deviations in and is potentially used to identify potential EM occurrence. A.1.2 Weak 1 In this case, the circuit simulated for determination of Fourier coefficients is shown in Figure A-3. The resulting output waveforms for different values of R L are given as Figure A- 4. All the computed Fourier coefficients are tabulated as shown in Table 2. 93

111 FigureA-3: Circuit Diagram for Weak 1 Fault with 6L Interconnect Figure A-4: Waveform Obtained from Simulation of Weak 1 Circuit 94

112 Table A.2: Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-Off Values for Determining the EM Fault in Weak 1 Circuit with Interconnects of Length 6L Rising Input Falling Input Signature Values of Coefficients Obtained fourier Coefficients Absolute % Deviations Signature Values of Coefficients Obtained fourier Coefficients Absolute % Deviations For rising input, if any one of the Fourier coefficient values a1, a3, a4, b1, b2 and b4 obtained are found to have deviations of more than 50%, then the presence of EM fault is identified. A deviation in the value of coefficient b3 of more than 33% can also be used for the identification. Similarly, identification of EM occurrence for a falling input can be determined by only a1 coefficient with its cut-off percentage deviation being 75%. A.2 24L Interconnect A.2.1 Weak 0 The circuit diagram of an inverter circuit with EM fault introduced into it with a resistor mimicking it is shown in Figure A-5. The circuit is developed with the length 24L having its resistor and capacitor values appropriately designed according to the 95

113 formulae mentioned in Chapter 6. The Fourier coefficients obtained from applying sampled output values are compared to the stored signature values. Percentage deviations for two cases, rising input and falling input are given in the Table 3. Figure A-5: Circuit Diagram for Weak 0 Fault with 24L Interconnect Figure A-6: Waveform for Weak 0 Circuit after Simulation 96

114 In case of the rising input, percentage deviations in the coefficients,, and are prominently used. Any of these Fourier coefficients having their values with more than 50% of deviations is good enough to identify the probably EM occurrence. Similarly, for falling input, the coefficient values of,, and can be used in the identification of the EM fault in the circuit. Table A.3: Comparison of Fourier Coefficients with the Signature Values and Determining the Cut-Off Values for Determining the EM Fault in Weak 0 Circuit with 24L Length of Interconnect Rising Input Falling Input Signature Values of Coefficients Obtained fourier Coefficients Absolute % Deviations Signature Values of Coefficients Obtained fourier Coefficients Absolute % Deviations A.2.2 Weak 1 The circuit diagram and corresponding output waveform for different values of EM effect is plotted in Figure A-7 and Figure A-8, respectively. The Fourier coefficients obtained from the circuit simulation is shown in Table 4. 97

115 Figure A-7: Circuit Diagram for Weak 1 Fault with 24L Interconnect Figure A-8: Waveform for Weak 1 Circuit with 24L Interconnect after Simulation 98