FPGA Resource Utilization Estimates for NI PXI-7854R. LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008

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1 FPGA Resource Utilization Estimates for NI PXI-7854R LabVIEW FPGA Version: 8.6 NI-RIO Version: 3.0 Date: 8/5/2008 Note: The numbers presented in this document are estimates. Actual resource usage for your designs may be different (smaller or greater) than the resource usage computed using the information contained in this document. 1. How to use the table An example Resource utilization tables for the functions on the FPGA palette Structures Array Cluster & Variant Numeric Boolean Comparison Timing Memory & FIFO Memory FIFO FIFO DMA host-to-target FIFO DMA target-to-host FPGA Math & Analysis Look-up Table 1D Butterworth filter Notch filter DC & RMS Measurements Fast Fourier Transform Rational Resampler Synchronization Advanced... 29

2 1. How to use the table The tables in this spreadsheet contain approximations of resource usage. To obtain an estimate for your design, add the corresponding numbers for each function/vi you use. Some of the functions on the LabVIEW FPGA palette consume no logic resources on the FPGA because they are purely wiring operations: For more FPGA-specific information about the objects on the palette see LabVIEW Help: VI and Function Reference > FPGA Module VIs and > FPGA VI and Function details. For information on the resources available for the PXI-7854R target, go to: Start menu > Programs > National Instruments > NI-RIO > R Series Intelligent DAQ Specifications Then, look under the heading Reconfigurable FPGA. To allow for target overhead, you should add the following base numbers to the sum of flip flops and the sum of LUTs: Flip LUTs Also add the corresponding numbers for the controls and indicators in your VI(s): Data type Resource usage Flip LUTs Numeric controls and indicators U U U U I I I I FXP<±,8,4> FXP<±,16,8> FXP<±,32,16> FXP<±,64,32>

3 Boolean controls and indicators Boolean 3 4 Data type Fixed array size Resource usage Flip LUTs Array controls and indicators U U U U I I I I FXP<±,8,4> FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Boolean

4 An example To illustrate the difference between actual resource usage and the estimate obtained using the spreadsheet, we use an example from the NI Example Finder, Counters R Series.lvproj

5

6 Actual resource usage: Slice Logic Utilization: Slice Registers: 1,053 out of 69,120 1% Number used as Flip : 1,053 Slice LUTs: 1,070 out of 69,120 1% Number used as logic: 1,061 out of 69,120 1% Number using O6 output only: 906 Number using O5 output only: 76 Number using O5 and O6: 79 Number used as Memory: 6 out of 17,920 1% Number used as Shift Register: 6 Number using O6 output only: 6 Number used as exclusive route-thru: 3 Estimated resource usage: Name of VI/Element Resource Usage Flip LUTs Select I32/U32 SCTL Select I32/U32 SCTL Select I32/U32 SCTL Greater? Boolean SCTL Greater? Boolean SCTL Not SCTL 0 1 Increment I32/U32 SCTL 0 32 Subtract I32/U32 SCTL 0 33 Tick count 32-bit SCTL Loop timer 32-bit Structures Timed Loop Timed Loop Case structure SCTL 0 0 Flat sequence SCTL 0 0 While loop, i terminal unwired Stacked sequence 0 0 Controls and indicators 7x Boolean x U Base Total

7 3. Resource utilization tables for the functions on the FPGA palette 3.1. Structures Name of VI/Element Data Outside SCTL Inside SCTL Type Flip LUTs Flip LUTs Structures For Loop, i terminal wired Not supported For Loop, i terminal unwired Not supported While Loop, i terminal wired 2 3 Not supported While Loop, i terminal unwired Not supported Timed Structures 0 0 Timed Loop Not supported FPGA Clk Const Case Structure Flat Sequence Structure 0 0 No sequencing effect Stacked Sequence Structure 0 0 No sequencing effect Diagram Disable Structure Conditional Disable Structure Local Variable Boolean I8/U I16/U I32/U I64/U Decorations Free Label Thin Line Thin Line with Arrow Flat Frame Thick Line Thick Line with Arrow Feedback Node Boolean I8/U I16/U I32/U I64/U

8 3.2. Array Name of VI/Element Data Array Outside SCTL Inside SCTL Type Size Flip LUTs Flip LUTs Array Array Size Index Array I32/U Replace Array Subset I32/U Insert Into Array Delete From Array Initialize Array Build Array Array Subset Rotate 1D Array I32/U Not supported Reverse 1D Array Split 1D Array Interleave 1D Arrays Decimate 1D Array Array Constant Array to Cluster Cluster to Array Reshape Array

9 3.3. Cluster & Variant Name of VI/Element Outside SCTL Inside SCTL Flip LUTs Flip LUTs Cluster & variant Unbundle Bundle Unbundle by Name Bundle by Name Cluster Constant Cluster to Array Array to Cluster Name of VI/Element 3.4. Numeric Input (s) Output Flip Outside SCTL LUTs DSP48 Es Flip Inside SCTL LUTs DSP48E s Numeric Add I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,16,8> FXP<±,32,16> FXP<±,32,16> FXP<±,64,32> FXP<±,64,32> Subtract I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,16,8> FXP<±,32,16> FXP<±,32,16> FXP<±,64,32> FXP<±,64,32> Multiply I8/U8 I16/U I16/U16 I32/U I32/U32 I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,32,16> FXP<±,64,32>

10 Quotient & Remainder I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U Not supported I64/U64 I64/U Conversion To Byte Integer To Word Integer To Long Integer To Quad Integer To Unsigned Byte Integer To Unsigned Word Integer To Unsigned Long Integer To Unsigned Quad Integer To Fixed Point I16 FXP<±,16,16> I32 FXP<±,32,32> I64 FXP<±,64,64> Number to Boolean Array Boolean Array to Number Boolean to (0,1) Increment I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,16,8> FXP<±,32,16> FXP<±,32,16> FXP<±,64,32> FXP<±,64,32> Decrement I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,16,8> FXP<±,32,16> FXP<±,32,16> FXP<±,64,32> FXP<±,64,32> Data Manipulation Rotate Left with Carry I8/U8 I8/U8 I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U Rotate Right with Carry I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U Logical Shift I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U

11 I64/U64 I64/U Rotate I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U Split Number Join Numbers Swap Bytes Swap Words Absolute Value I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,16,8> FXP<±,32,16> FXP<±,32,16> FXP<±,64,32> FXP<±,64,32> Round to Nearest I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,9,9> FXP<±,32,16> FXP<±,17,17> FXP<±,64,32> FXP<±,33,33> Round Toward -Infinity I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,8,8> FXP<±,32,16> FXP<±,16,16> FXP<±,64,32> FXP<±,32,32> Round Toward +Infinity I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,9,8> FXP<±,32,16> FXP<±,17,17> FXP<±,64,32> FXP<±,33,33> Scale by Power of 2 I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U Square I8/U8 I16/U I16/U16 I32/U I32/U32 I64/U FXP<±,16,8> FXP<±,32,16>

12 FXP<±,32,16> FXP<±,64,32> Negate I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,15,7> FXP<±,16,8> FXP<±,31,15> FXP<±,32,16> FXP<±,63,31> FXP<±,64,32> Reciprocal FXP<±,32,16> FXP<±,33,18> Not supported Sign I8/U8 I8/U I16/U16 I16/U I32/U32 I32/U I64/U64 I64/U FXP<±,16,8> FXP<±,2,2> FXP<±,32,16> FXP<±,2,2> FXP<±,64,32> FXP<±,2,2> Fixed-Point Clear Overflow Status FXP<±,32,16> FXP<±,32,16> Remove Overflow Status FXP<±,32,16> FXP<±,32,16> Include Overflow Status FXP<±,32,16> FXP<±,32,16> Numeric Constant Enum Constant Ring Constant Name of VI/Element Compound Arithmetic Mode Outside SCTL Inside SCTL Data inputs Flip LUTs DSP48Es Flip LUTs DSP48Es Type I32/U32 2 Add Add Add Multiply Multiply Multiply AND AND AND OR OR OR XOR XOR XOR

13 Boolean 2 AND AND AND OR OR OR XOR XOR XOR Boolean Name of Data Outside SCTL Inside SCTL VI/Element Type Flip LUTs Flip LUTs Boolean And Boolean I8/U I16/U I32/U I64/U Or Boolean I8/U I16/U I32/U I64/U Exclusive Or Boolean I8/U I16/U I32/U I64/U Not Boolean I8/U I16/U I32/U I64/U Compound Arithmetic see the second table in section 3.4. Numeric Not And Boolean I8/U I16/U I32/U I64/U

14 Not Or Boolean I8/U I16/U I32/U I64/U Not Exclusive Or Boolean I8/U I16/U I32/U I64/U Implies Boolean I8/U I16/U I32/U I64/U Number to Boolean Array I8/U I16/U I32/U I64/U Boolean Array to Number I8/U I16/U I32/U I64/U Boolean to (0,1) True Constant False Constant Name of Array Outside SCTL Inside SCTL VI/Element Size Flip LUTs Flip LUTs And Array Elements Or Array Elements

15 3.6. Comparison Name of Data Outside SCTL Inside SCTL VI/Element Type Flip LUTs Flip LUTs Comparison Equal? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Not Equal? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Greater? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Less? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Greater or Equal? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32>

16 Less or Equal? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Equal to 0? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Not Equal to 0? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Greater Than 0? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Less Than 0? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Greater or Equal to 0? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Less or Equal to 0? I8/U I16/U

17 I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Select? Boolean I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Max & Min? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> In Range and Coerce? I8/U I16/U I32/U I64/U FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Fixed-Point Overflow? FXP<±,16,8> FXP<±,32,16> FXP<±,64,32> Timing Name of Size of Internal Counter Outside SCTL Inside SCTL VI/Element (bits) Flip LUTs Flip LUTs Timing Loop Timer Wait Not supported Tick Count

18 3.8. Memory & FIFO Memory Boolean 1024 if multiple requestors only if multiple requestors only 1 1, s, 2 s I if multiple requestors only if multiple requestors only 1 1, s, 2 s I if multiple requestors only if multiple requestors only 1 1, s, 2 s I always always 1 1, s, 2 s

19 I never never 1 1, s, 2 s I if multiple requestors only if multiple requestors only 1 1, s, 2 s I always always 1 1, s, 2 s I never never 1 1, s, 2 s I if multiple requestors only if multiple requestors only 2 1, s, 2 s

20 I always always 2 1, s, 2 s I never never 2 1, s, 2 s I if multiple requestors only if multiple requestors only 8 1, s, 2 s I always always 8 1, s, 2 s I never never 8 1, s, 2 s

21 FIFO Number Data of Implementation Flip LUTs Type I Block memory if multiple requestors if multiple requestors only only 1, , 1, 1 Clear s, 2 s, 1 Clear Block 1 Number Data of Implementation Type I Block memory always always 1 1, , 1, 1 Clear s, 2 s, 1 Clear Number Data of Implementation Type I Block memory never never 1 1, , 1, 1 Clear s, 2 s, 1 Clear Number Data of Implementation Flip LUTs Type I Block memory if multiple requestors if multiple requestors only only 1, , 1, 1 Clear s, 2 s, 1 Clear Block 1

22 Number Data of Implementation Type I Block memory always always 1 1, , 1, 1 Clear s, 2 s, 1 Clear Number Data of Implementation Type I Block memory never never 1 1, , 1, 1 Clear s, 2 s, 1 Clear FIFO DMA host-to-target arbitration Flip LUTs Block I if multiple requestors only arbitration Flip LUTs Block I always arbitration Flip LUTs Block I never

23 arbitration Flip LUTs Block I if multiple requestors only arbitration Flip LUTs Block I always arbitration Flip LUTs Block I never FIFO DMA target-to-host arbitration Flip LUTs Block I if multiple requestors only arbitration Flip LUTs Block I always arbitration Flip LUTs Block I never

24 arbitration Flip LUTs Block I if multiple requestors only arbitration Flip LUTs Block I always arbitration Flip LUTs Block I never

25 3.9. FPGA Math & Analysis Name of VI/element FPGA Math & Analysis Control Discrete Nonlinear Systems Backlash Flip Outside SCTL LUTs Block DSP48E s Flip Inside SCTL LUTs Block DSP48 Es Friction Quantizer Dead Zone Rate Limiter Relay Saturate Switch Boolean Crossing Zero Crossing Memory Element Trigger Discrete Linear Systems Normalized Integrator Unit Delay Delay Not supported Zero-Order Hold Initial Condition Control Filter Utilities Linear Interpolation Saturate Zero Crossing Boolean Crossing Unit Delay Discrete Delay Not supported Generation Sine Wave Not supported Square Wave White Noise Scaled Window Analog Period Measurement Not supported

26 Look-up Table 1D Look-Up Table Specifications Data type Memory size Interpolate data Flip LUTs Block DSP48E s 1024 I16 2 KB yes U16 2 KB yes I8 1 KB yes I32 4 KB yes I16 4 KB yes I16 8 KB yes I8 2 KB yes I8 4 KB yes I32 8 KB yes I32 16 KB yes I32 64 KB yes Butterworth filter Butterworth filter configuration options Channels Input Output Type Order Cutoff frequency Sample rate Flip LUTs Block DSP48 Es 1 I16 I16 Lowpass 1 1kHz 50kS/s I16 I16 Lowpass 2 1kHz 50kS/s I16 I16 Lowpass 4 1kHz 50kS/s I32 I32 Lowpass 1 1kHz 50kS/s I32 I32 Lowpass 2 1kHz 50kS/s I32 I32 Lowpass 4 1kHz 50kS/s * I16 I16 Lowpass 2 1kHz 50kS/s * I16 I16 Lowpass 2 1kHz 50kS/s * I16 I16 Lowpass 2 1kHz 50kS/s * Multichannel support for the Butterworth filter is restricted to 16-bit resolution and 2nd order.

27 Notch filter Notch filter configuration options channels Input data type Expected sample rate (ks/s) Frequency (khz) Flip LUTs Block DSP48 Es 1 I I I I I I I I DC & RMS Measurements DC & RMS configuration options Function Input Hanning Expected Measurement DSP48Es data type window? sample rate time DC I16 no 50kS/s 20m DC I16 yes 50kS/s 20m DC I32 no 50kS/s 20m DC I32 yes 50kS/s 20m RMS I16 no 50kS/s 20m RMS I16 yes 50kS/s 20m RMS I32 no 50kS/s 20m RMS I32 yes 50kS/s 20m Sum I16 no 50kS/s 20m Sum I32 no 50kS/s 20m Mean I16 no 50kS/s 20m Square Mean I32 no 50kS/s 20m Square Square Sum I16 no 50kS/s 20m Square Sum I32 no 50kS/s 20m

28 Fast Fourier Transform The Fast Fourier Transform function is configurable for a range of input and output parameters. The resource usage table below is not exhaustive. Using the FFT VI inside of a SCTL enables an option to select the throughput. Throughput for all tests shown below is set not equal to one. Additionally, all tests (inside and outside SCTL) were performed using an output type of adapt to source. FFT configuration options Real data in data DSP48Es Length Direction Execution type FXP<±,16,8> 1024 Forward Inside SCTL FXP<±,16,8> 1024 Forward Outside SCTL FXP<±,16,8> 1024 Inverse Inside SCTL FXP<±,16,8> 1024 Inverse Outside SCTL FXP<±,16,8> 2048 Forward Inside SCTL FXP<±,16,8> 2048 Forward Outside SCTL FXP<±,16,8> 2048 Inverse Inside SCTL FXP<±,16,8> 2048 Inverse Outside SCTL FXP<±,32,16> 1024 Forward Inside SCTL FXP<±,32,16> 1024 Forward Outside SCTL FXP<±,32,16> 1024 Inverse Inside SCTL FXP<±,32,16> 1024 Inverse Outside SCTL FXP<±,32,16> 2048 Forward Inside SCTL FXP<±,32,16> 2048 Forward Outside SCTL FXP<±,32,16> 2048 Inverse Inside SCTL FXP<±,32,16> 2048 Inverse Outside SCTL Rational Resampler Rational resampler configuration options Number DSP48Es Input data type of channels Execution L M I32 1 Inside SCTL I32 1 Inside SCTL I32 1 Outside SCTL I32 4 Inside SCTL I32 4 Inside SCTL

29 I32 4 Outside SCTL I32 8 Inside SCTL I32 8 Inside SCTL I32 8 Outside SCTL FXP<±,32,16> 1 Inside SCTL FXP<±,32,16> 1 Outside SCTL FXP<±,32,16> 4 Inside SCTL FXP<±,32,16> 4 Outside SCTL FXP<±,32,16> 8 Inside SCTL FXP<±,32,16> 8 Outside SCTL Synchronization Name of Outside SCTL Inside SCTL VI/Element Flip LUTs Flip LUTs Synchronization FIFO see section 3.8 Memory & FIFO Occurrences Generate Occurrence Wait on Occurrence 1 2 Not supported Wait on Occurrence with Not supported Timeout in Ticks Set Occurrence 2 5 Not supported First Call? Interrupt 1 11 Not supported Advanced Advanced FPGA programming techniques could include either the HDL Interface Node or CLIP node. These methods also utilize FPGA resources on your target; however, the amount of resources will vary based on how the code is written.

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