ECE260B CSE241A Winter Statistical Timing Analysis and SPICE Simulation

Transcription

1 ECE260B CSE24A Winter 2005 Statistical Timing Analysis and SPICE Simulation Website: / courses/ ece260bw05 ECE 260B CSE 24A Statistical Timing Analysis & SPICE

2 Outline Static timing analysis Timing constraints Timing graph False path Variations Sources of variation and levels of analysis Monte Carlo SPICE simulation Statistical static timing analysis Pdf propagation Correlation (bounds, PCA, interval-valued) Gate and interconnect delay variation ECE 260B CSE 24A Statistical Timing Analysis & SPICE 2

3 Summary: Timing Constraints Synchronous design = combinational logic + sequential elements For each flip-flop: T max + T setup < T cycle - T skew CLK FF Q combinational logic D FF T min > T hold + T skew T max : longest data propagation path delay T min : shortest data propagation path delay CLK DATA T cycle T hold T setup ECE 260B CSE 24A Statistical Timing Analysis & SPICE 3

4 Timing Analysis Testing Simulation Device modeling (BSIM) Transistor-level time domain analysis (SPICE) Frequency domain interconnect analysis (AWE, PRIMA) Static timing analysis Transistor-level (PathMill) Gate-level (PrimeTime) ECE 260B CSE 24A Statistical Timing Analysis & SPICE 4

5 Data paths with timing constraints Starting from primary inputs/ff outputs Ending at primary outputs/ff inputs Represented by a labeled directed graph G = <V,E> 0 0 Timing Graph A C B Timing node V ~pin/primary input/output Timing edge E ~gate/wire delay (Timing arc ~gate delay) 2 U V.20 X Y.20 2 Z.5 F 0 0 A C B 2 2 U V X Y 2 2 Z.5 F Courtesy K. Keutzer et al. UCB ECE 260B CSE 24A Statistical Timing Analysis & SPICE 5

6 Characterization Static analysis = vector-less worst case analysis Graph based path propagation No logics Pre-characterized look-up tables for gate delays Min/max/rise/fall Characterized interconnect delays On-the-fly delay calculation SDF (standard delay format) annotation X Y 2 Z X 2 Z ECE 260B CSE 24A Statistical Timing Analysis & SPICE 6 Y 2

7 Compute Longest Path Origin 0 0 A U.20 X 2 C.5 2 V.20 Z B 2 2 Y (Kirkpatrick 966, IBM JRD) F Compute longest path in a DAG G = <V,E,delay,Origin> / / delay is set of labels, Origin is the super-source of the DAG Forward-prop(W){ for each vertex v in W for each edge <v,w> from v Final-delay(w) = max(final-delay(w), delay(v) + delay(w) + delay(<v,w>)) if all incoming edges of w have been traversed, add w to W } Longest path(g){ Forward_prop(Origin) } Courtesy K. Keutzer et al. UCB ECE 260B CSE 24A Statistical Timing Analysis & SPICE 7

8 Compute Longest Path Origin 0 0 A U.20 X 2 C.5 2 V.20 Z B 2 2 Y (Kirkpatrick 966, IBM JRD) F Compute longest path in a DAG G = <V,E,delay,Origin> / / delay is set of labels, Origin is the super-source of the DAG Forward-prop(W){ for each vertex v in W for each edge <v,w> from v Final-delay(w) = max(final-delay(w), delay(v) + delay(w) + delay(<v,w>)) if all incoming edges of w have been traversed, add w to W } Longest path(g){ Forward_prop(Origin) } Dynamic programming How to exclude a set of paths? Courtesy K. Keutzer et al. UCB ECE 260B CSE 24A Statistical Timing Analysis & SPICE 8

9 Timing Analysis Terminology Actual arrival time (AAT): forward propagation Required arrival time (RAT): backward propagation Slack = RAT - AAT A measure of how much timing margin exists at each node Slack < 0 timing violation Can optimize a particular branch Can trade slack for power, area, robustness Critical path clock ECE 260B CSE 24A Statistical Timing Analysis & SPICE 9

10 Timing Exceptions False paths: topologically connected but logically impossible to enable To enable a path Logically: non-controlling values (e.g., 0 for OR gates, for AND gates) at side inputs Temporally: earlier signal transitions at side inputs clock ECE 260B CSE 24A Statistical Timing Analysis & SPICE 0

11 False Path Representation Abstracted graph Set_false_path -from { } through { } -through { } to { } from through through to from through through to ECE 260B CSE 24A Statistical Timing Analysis & SPICE

12 False Path Identification Tagged timing analysis Arrival times with the same tag are compared to find worst case False path filtered b arr: tag: 0 arr: 2 tag: 2 d a clock c arr: 3 tag: 3 a from through through to d b tag: 2 c tag: 3 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 2

13 Handling Latch-Based Designs Latch: level enabling sequential element Transparent signal propagation Latch Time borrowing Path delay of previous stage T borrow combinational logic CLK D Q combinational logic Path delay of current stage + T borrow CLK DATA transparent T borrow ECE 260B CSE 24A Statistical Timing Analysis & SPICE 3

14 Outline Static timing analysis Timing constraints Timing graph False path Variations Sources of variation and levels of analysis Monte Carlo SPICE simulation Statistical static timing analysis Pdf propagation Correlation (bounds, PCA, interval-valued) Gate and interconnect delay variation ECE 260B CSE 24A Statistical Timing Analysis & SPICE 4

15 Variations Variability is proportionately increasing manufacturing - FEOL: critical dimensions are scaling faster than our control of them - BEOL: variability dramatically increases the number of independent and significant sources of variation environmental (Vdd, temperature) fatigue (hot electron effect) across-chip (OCV/ACLV, temperature, Vdd) circuit design (PLL jitter, coupling noise) model-to-hardware correlation ECE 260B CSE 24A Statistical Timing Analysis & SPICE 5

16 Delay impact of variations BEOL metal Parameter Delay Impact -0% +25% (Metal mistrack, thin/ thick wires) Environmental (Voltage islands, IR drop, temperature) Device fatigue (hot electron effects) V t and T ox device family tracking ±5 % ±0% ± 5% (Can have multiple V t and T ox device families) Model/ hardware uncertainty ± 5% (Per cell type) N/P mistrack ±0% (Fast rise/ slow fall, fast fall/ slow rise) PLL ±0% (Jitter, duty cycle, phase error) [Courtesy Kerim Kalafala] Requires 2 20 timing runs or [-65%,+80%] guard band! ECE 260B CSE 24A Statistical Timing Analysis & SPICE 6

17 Process Variations Sources of Variations:. Environmental factors 2. Physical factors Figure: Device and interconnect variation trends for different technology generations.the percentage of the total variation accounted for by within-die variation for selected parameters. Source: Models of process variations in device and interconnect by Duane Boning, MIT & Sani Nassif, IBM ARL. ECE 260B CSE 24A Statistical Timing Analysis & SPICE 7

18 Process Variations (..contd) Figure: Statistical distribution of 6-bit adder Critical Path delay 0.8µm technology. 3σ -worst case of monte-carlo simulation CWC: classical worst case model Process Parameters: Oxide thickness, Length, Width, Threshold voltage Impact of Unrealistic Worst Case Modeling on the Performance of VLSI circuits in Deep Submicron Region CMOS Technologies - A.Nardi, A.Neviani, E.Zanoni,M.Quarantelli, IEEE 99 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 8

19 Process Variation Classification systematic - CMP and OPC related random - fluctuations in doping concentration, lens aberration - modeling limitations inter-chip - from die to die / wafer to wafer / lot to lot intra-chip - within a single die - spatially correlated ECE 260B CSE 24A Statistical Timing Analysis & SPICE 9

20 Counting Process Variation Off-chip variation: two paths on a chip cannot use two different operating conditions (i.e., corners) at the same time for setup or hold analysis Launchclock_latepath (max) + data_latepath (max) < captureclock_earlypath (max) + clock_period setup Launchclock_earlypath (min) + data_earlypath (min) > captureclock_latepath (min) + hold On-chip variation: the software calculates the delay for one path based on maximum operating condition while calculating the delay for another path based on minimum operating condition for setup or hold checks Statistical static timing analysis (SSTA) Based on discrete corners pdf Continuous pdf (probability distribution functions) ECE 260B CSE 24A Statistical Timing Analysis & SPICE 20

21 Clock Re-convergence Pessimism Removal Common part of two clock propagation paths cannot have two different path delays at the same time Need to compute clock propagation delay from the branch point FF Q max combinational logic D FF min CLK max Common part ECE 260B CSE 24A Statistical Timing Analysis & SPICE 2

22 Outline Static timing analysis Variations Monte Carlo SPICE simulation Statistical static timing analysis ECE 260B CSE 24A Statistical Timing Analysis & SPICE 22

23 Circuit Simulation Kirchhoff s Voltage Law (KVL): the algrbraic sum of the voltage drops along any loop in a circuit equals zero Kirchhoff s Current Law (KCL): the algebraic sum of all the currents flowing out of (or into) any node in a circuit is zero ECE 260B CSE 24A Statistical Timing Analysis & SPICE 23

24 Modified Nodal Analysis c v i 3 o u t = 0 0 v g g 0 v 0 0 v 2 g g + g 2 g 2 0 v = c 2 0 v 3 0 g 2 g 2 0 v 0 0 i o u t i v or v T v 3 i N = L x n i o u t 2 3 o u t u 0 C x = G x + B u n n N N u N I out g v v g 2 2 v 3 c c 2 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 24

25 SPICE Input.include 30nm_model R node node2 20 C node 0.2f C2 node2 0.5f X innode node vddnode 0 inv Vsp vddnode 0.0 Vi innode 0 pwl( p 0 20n 0).op.tr p 25000p.plot v(innode) v(node2) i(c).end ECE 260B CSE 24A Statistical Timing Analysis & SPICE 25

26 SPICE Input * This is the 30nm_model file.temp 25.param size= 0.3u.subckt inv in out vdd vgnd m out in vdd vdd pmos w= 2*size l=0.3u m2 out in vgnd vgnd nmos w=size l=0.3u.ends inv.model pmos pmos +Level = 49 +Lint = 3.25e 08 Tox =.6e 09 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 26

27 Monte Carlo Analysis in HSPICE To set up a Monte Carlo Analysis, use the following HSPICE statements:.param sets a model or element parameter to a Gaussian, Uniform, or Limit function distribution.dc,.ac, or.tran analysis enables Monte Carlo.measure calculates the output mean, variance, sigma, and standard deviation.model sets model parameters to a Gaussian, Uniform, or Limit function distribution ECE 260B CSE 24A Statistical Timing Analysis & SPICE 27

28 Monte Carlo Analysis in SPICE Simulation * This enables Monte Carlo analysis.param xx=gauss(nominal, rel_variation, sigma<,multiplier>).tr n 0n sweep monte=list(0 20:30 40) ECE 260B CSE 24A Statistical Timing Analysis & SPICE 28

29 Outline Static timing analysis Timing constraints Timing graph False path Variations Monte Carlo SPICE simulation Statistical static timing analysis Pdf propagation Correlation (bounds, PCA, interval-valued) Gate and interconnect delay variation ECE 260B CSE 24A Statistical Timing Analysis & SPICE 29

30 Probabilistic Timing: Formulation Given: A probabilistic timing graph a graph with random node delays. Joint pdf of node delays, d( N ) Find: P (max D( G ) t ) P G = ( N, E), P C A W B X Y Z f Deterministic STA requires two algebraic operations Summation of delay Taking maximum D ( Z ) = max{ D ( X ) + d, D ( Y ) + d } X Z Y Z Probabilistic max is difficult Identity of longest path is random Exact evaluation for arbitrary pdfs is computationally prohibitive ECE 260B CSE 24A Statistical Timing Analysis & SPICE 30

31 Objective of Statistical Timing Analysis & Yield Prediction Find probability distribution of circuit delay PDF / CDF can be represented by continuous or discrete functions P P t t t Probability density function (pdf) Cumulative distribution function (cdf)

32 Strategy : Bounding the p.d.f Assumptions: A delay pdf is non-zero only on a finite interval A delay pdf equals 0 for all delay values < d min and for all values > d max Approximate continuous pdf and PDF with discrete functions Arrival Time PDF of n, An(t) = Probability( G D in the sample space has an arrival time) t a n t Graph delay computed by propagating arrival times from source node to sink node.. ECE 260B CSE 24A Statistical Timing Analysis & SPICE 32

33 Strategy : Bounding the p.d.f Graph transforms: Series Reduction n p n2 q n3 (t) (t) Convolution: Pr {D G P t}= p G t P = 0 t t t p t q t 2 dt dt 2 p t q d Parallel Reduction p(t) n n2 Pr {D G P t}= max t,t t p t q t 2 dt dt 2 q(t) P G P t =P t.q t ECE 260B CSE 24A Statistical Timing Analysis & SPICE 33

34 Strategy : Bounding the p.d.f Arrival Time Propagation: Independent Arrival Time propagation n 2 (A 2 ) n S n(a) n (A ) n S E n 3 n 2 (A 2 ) n(a) E 2 n (A ) ECE 260B CSE 24A Statistical Timing Analysis & SPICE 34

35 Strategy 2: Gaussian Processes Problem formulation: Assuming gate delays to be correlated Normal Random variable, compute the Mean and Variance of critical path delay MAX(D) Basic Idea: Transforming series-edges, n n2 n3 n n3 x x 2 t=x x 2 Exp [ t ]= 2 Var [ t ]=Var [ x ] Var [ x 2 ] 2.Cov [ x, x 2 ] Cov [ x x 2, x 3 ]=Cov [ x, x 3 ] Cov [ x 2, x 3 ] ECE 260B CSE 24A Statistical Timing Analysis & SPICE 35

36 Strategy 2: Gaussian Processes Transforming parallel-edges, N = MAX(N,N 2 ) need not be normal!! n N ~, 2 n2 N 2 ~ 2, 2 2 C. Clark, The greatest of a finite set of random variables. Operations Research, 96 For two stochastic variables X ~, 2 and Y ~ 2, 2 2 with correlation coefficient R[ x, y ]=, the mean Exp [ t ] and variance Var [ t ] of t=max [ x, y ] are obtained by the following equations, unless 2 = =0 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 36

37 Strategy 2: Gaussian Processes Exp [ t ]=. 2.. Var [ t ]= where, = x = 2 x = 2 = 2 exp [ x 2 2 ] x exp [ y2 2 ]dy Exp [ t ] 2 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 37

38 Strategy 2: Gaussian Processes Algorithm: Starts at source node, propagates the mean, variance and covariance structure of the graph until the sink is reached At sink node, we have the Mean and Variance of the critical path delay Results: ECE 260B CSE 24A Statistical Timing Analysis & SPICE 38

39 Strategy 3: Convex Majorization Probabilistic PERT, A. Nadas, IBM R & D Journal, 979 Problem Formulation: Identify a random variable M*, s.t. M* is convexly larger than the random variable M = MAX (D) For any two random variables X and Y X C X Y iff, t Pr X u. du t Pr Y u. du, t Equivalent to comparing residual expectation **E X t = t Pr X u. du ** =max,0 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 39

40 Strategy 3: Convex Majorization Theorem: Assume all edge delays X i have E(X i ) finite. Then. There exists a r.v. M* s.t. max j Pj n x i t i = E M* t =min {x i } E X i x i 2. M, the critical path length is convexly no larger than M* 3. The solution can be recast as the following constrained minimization problem: E M* t =min x i n i= E X i x i Subject to x i t j P j ECE 260B CSE 24A Statistical Timing Analysis & SPICE 40

41 Strategy 3: Convex Majorization 4. Let λ j be the Lagrange Multiplier associated with the j-th path constraint in the minimization problem. Then, for M, the critical path delay, j =Pr M = P j X i t j=,2,...,n is the probability that the j th path is critical, i.e., the j th bottleneck probability Computes a tight upper bound on the critical path delay, M, and also identifies the bottleneck probabilities of each path as a side-product. Computational complexity is very high!!! ECE 260B CSE 24A Statistical Timing Analysis & SPICE 4

42 Statistical timing tools Path-based conduct a nominal timing analysis list a representative set of critical paths (question: how may paths? question: which paths?) model the delay/slack of each path as a function of random variables (the underlying sources of variation) predict the parametric yield curve (statistical MIN of all path slacks), as well as generate diagnostics Block-based propagate arrival times and required arrival times in the form of probability distributions linear time approximate, quick-and-dirty ECE 260B CSE 24A Statistical Timing Analysis & SPICE 42

43 Statistical timing tools Path-based Slow and accurate Non-incremental; for sign-off Parameter-space methods More general (usually Monte-Carlo-based) Fabrication-parameter diagnostics Block-based Quick and dirty Incremental; for (robust) optimization Performance-space methods Assumes symmetry and linearity Criticality probabilities useful to circuit designer ECE 260B CSE 24A Statistical Timing Analysis & SPICE 43

44 Approaches to Statistical Timing Block - based approaches Approximations of distribution of max [Berkelaar, 98] Recent extension to handling spatial correlation [Chen, 03] Parameter - space integration methods Accurate, small number of sources of variation [Visweswariah, 03] Monte - Carlo simulation Can be sped up to be competitive [Scheffer, 04] Bounds - based methods Convex majorization [Nadas, 79] Stochastic majorization [Orshansky, 02; this work] ECE 260B CSE 24A Statistical Timing Analysis & SPICE 44

45 Outline Static timing analysis Timing constraints Timing graph False path Variations Monte Carlo SPICE simulation Statistical static timing analysis Pdf propagation Correlation due to fanout reconvergence Correlation among variations ECE 260B CSE 24A Statistical Timing Analysis & SPICE 45

46 Problem of Correlations Two types of correlation reconvergence spatial correlation gate delay pdfs Arrival time pdf Arrival time pdf B D I A C ECE 260B CSE 24A Statistical Timing Analysis & SPICE 46

47 PDF Propagation with Re-convergence Fanouts Recursive enumeration of re-converging nodes Grows exponentially with number of re-converging nodes in the graph Useful only for small timing graphs or for mostly treelike structures e D k P X =x = i =0 X P X =x D=d. P D=d ECE 260B CSE 24A Statistical Timing Analysis & SPICE 47

48 Dependent Arrival Time Propagation Intersection graph Dependence nodes Global set of dependence nodes Discrete PDF in delay-probability pairs (di, pi) Enumerate AAT PDF propagation of dependence nodes a b c g e d f h n s ECE 260B CSE 24A Statistical Timing Analysis & SPICE 48

49 Dependent Arrival Time Propagation. Identify dependence nodes 2. Propagate AAT PDF until the first dependence node nd 3. For each pair (ti, pi) at the dependence node 4. Propagate ti with cond. prob. pi 5. For each dependence node encountered, repeat 3 6. Collect AAT PDF with cond. prob. at each node e a b c g e d f h n s ECE 260B CSE 24A Statistical Timing Analysis & SPICE 49

50 Bounding the p.d.f Statistical bounds: what is the purpose?? PDF P(t) is an upper bound on arrival time PDF A n (t) iff P t A n t t Pr p t T clk Pr A n t T clk P t A n t if P T clk = Pr A n t T clk Probability that the actual arrival time exceeds T clk is bounded by α PDF A n t P t ECE 260B CSE 24A Statistical Timing Analysis & SPICE 50

51 Bounding the p.d.f Theorem: Let x, y, z be r.v. Let x, x 2 be i.i.d with x. Then PDF of r.v. max (x + y, x 2 + z) is an upper bound on PDF of r.v. max(x+y,x+z) upper bound on arrival time by node splitting! n 2 n s a n n s a n s a 2 n n 3 n 2 n s n 2 n 3 ECE 260B CSE 24A Statistical Timing Analysis & SPICE 5

52 Bounding the p.d.f Lower bound: x, y are lower bounds on max(x,y) Tightest lower bound, if fanin edge with maximum expected value is preserved!!! Results: Compares upper and lower bounds of ISCAS `85 circuits with Monte-carlo simulations Error within 2-3% ECE 260B CSE 24A Statistical Timing Analysis & SPICE 52

53 Outline Static timing analysis Timing constraints Timing graph False path Variations Monte Carlo SPICE simulation Statistical static timing analysis Pdf propagation Correlation due to fanout reconvergence Correlation among variations ECE 260B CSE 24A Statistical Timing Analysis & SPICE 53

54 Statistical Timing Analysis Basic approach: Estimate the distribution of every path delay Compute yield from the joint distribution of all path delays Fundamental statistical issues: Do you consider within-die variations, or only die-to-die? If yes, then are within-die path delay variations independent? If not independent, then how do you capture their correlation? Scale of difficulty: d i e - t o - d i e o n l y d i e - t o - d i e + w i t h i n - d i e w i t h i n d e p e n d e n c e d i e - t o - d i e + w i t h i n - d i e w i t h c o r r e l a t i o n H a r d H a r d e r M u c h H a r d e r ECE 260B CSE 24A Statistical Timing Analysis & SPICE 54

55 Statistical Timing Analysis Recent approaches: Propagate distributions to compute a path delay distribution - Efficient techniques for going through a node in the timing graph Handle within-die correlation using either of: - Quad-tree partitioning [Agarwal, Blaauw, & Zolotov: ICCAD-03] - PCA-based decomposition [Chang & Sapatnekar: ICCAD-03] Apart from integration difficulties, have key problems: Require change of methodology (statistical cell delay models) Require layout information, hence post-placement sign-off - not applicable in circuit design phase, pre-placement Get the correlation information from process ECE 260B CSE 24A Statistical Timing Analysis & SPICE 55

56 Characterization Methodology: Gate Delay Distribution Process Parameter Distributions p 2 Sensitivity Analysis (SPICE) Cell library p Parametrical Gate Delay Model n om dg n om dg = d g + ( pi - p i ) pi Mean gate delays d 2 Gate delay variance, d 2 d Gate Delay Distribution Gate delay covariance cov{ dg ( i ), dg ( j )}

57 Computing Path Delay Distribution Use deterministic STA with nominal delay values to generate a set of near-critical paths nom i max i i G P Π = { D D ( ) }, where is a path through D = { D ( ) Π} is a random vector of path delays i i Direct (computationally expensive) characterization of cov {D} Gate Delay Distribution A X Path Delay Distribution d 2 d C W B Y Z f D 2 D m i m j i j g i g j k = k = cov{ D, D } = cov{ d ( i, k ), d ( j, k )} ECE 260B CSE 24A Statistical Timing Analysis & SPICE 57 i j

58 Sensitivity Based Analysis Variations in geometric dimensions changes in electrical parameters R = R nom + a W+a 2 T C = C nom + b W+b 2 T+b 3 H Electrical parameters moments Moments delays Variations need to be small so that first order approximation is reasonably accurate ECE 260B CSE 24A Statistical Timing Analysis & SPICE 58

59 Interval Analysis Simple interval arithmetic X = [ x.lo, x.hi] Z = x + y = [ x.lo+y.lo, x.hi+y.hi] Affine interval arithmetic preserves correlations among variables, in a form analogous to a first-order Taylor series X = x 0 +x ε +x 2 ε 2 + +x n ε n Z = x + y = (x 0 + y 0 )+(x + y )ε +(x 2 + y 2 )ε 2 + +(x n + y n )ε n Each uncertainty symbol ε i stands for an independent component Approximate quadratic uncertainty terms by a new uncertainty symbol Push interval values through model reduction and delay calculation algorithms ECE 260B CSE 24A Statistical Timing Analysis & SPICE 59

60 Variational Analysis Matrix perturbation theory Let A be a symmetric matrix with eigenvalues λ >λ 2 > λ n and A =A+E denote a symmetric perturbation of A with eigenvalues λ >λ 2 > λ n Let the eigenvalues of E be ε >ε 2 > ε n Then, for I =,, n, λ i [ λ i +ε n, λ i +ε ] A = G - C which eigenvalues give poles ECE 260B CSE 24A Statistical Timing Analysis & SPICE 60

61 The Link to Process Quad-tree partitioning requires knowledge of the autocorrelation function: At what distances (on the die) does correlation become weak? PCA (principal components analysis) transform a set of correlated parameters into an uncorrelated set X a a a 2 p Z X a 2 2 a22 a2p = p X n an an 2 a np The X i are correlated, the Z i are independent, n > p typically Reduce number of random variables How are the PCA coefficients to be obtained? Z ECE 260B CSE 24A Statistical Timing Analysis & SPICE 6

62 Proposed Solution # Focus not on the particular design, but on design type: What is a typical transistor in this technology? What is a typical gate in this circuit design style? What is a typical path length in this class of design? Assume the circuit consists of a large number of such generic paths, spread across the die Compute yield from the aggregate statistical properties of such a large ensemble (population) of paths This eliminates the dependence on layout information for a particular design, allowing pre-placement analysis ECE 260B CSE 24A Statistical Timing Analysis & SPICE 62

63 Proposed Solution #2 Handle correlation using PCA but do not require the individual PCA coefficient values: Starting with the PCA fact: Use the Cauchy inequality: p p 2 2 i = ij j σ X = i ij j= j= X a Z a Leading to: p p p p 2 2 aij z j aijz j aij z j j= j= j= j= p p 2 aij z j σ X i z j j= j= Get a yield upper bound that requires only σ X, not a ij, but need to know p, the order of the PCA ECE 260B CSE 24A Statistical Timing Analysis & SPICE 63

64 Thanks A. Agarwal, D. Blaauw, U. of Michigan M. Orshansky, A. Bandyopadhyay, U. of Texas, Austin N. Menezes, Intel Inc. F. N. Najm, U. of Toronto S. Raj, S. Vrudhura, U. of Arizona V. Zolotov, Motorola Inc. ECE 260B CSE 24A Statistical Timing Analysis & SPICE 64