Dept. Information Systems Engineering, Osaka Univ., Japan
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1 Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise Takashi Enami Shinyu Ninomiya Masanori Hashimoto Dept. Information Systems Engineering, Osaka Univ., Japan {enami.takashi, ninomiya.shinyu, i hasimoto}@ist.osaka-u.ac.jp t
2 Agenda Background and objective Statistical modeling of power supply noise SSTA with statistical model of power supply noise Experimental results Conclusion 2008/04/16 ISPD
3 Background Voltage drop at power wire. Power supply noise is becoming more influential on timing due to increasing current consumption, decreasing power supply voltage. Demand for timing analysis considering power supply noise. 2008/04/16 ISPD
4 Objective Conventional analysis method Dynamic analysis Analysis with test patterns. => Combination space of test patterns is tremendous. Static analysis Analysis with constant voltage drop. => Irrelevant voltage drop leads to optimistic or excessively pessimistic estimation. Exact worst-case delay cannot be obtained practically. Propose a statistical timing analysis method that gives reasonable worst-case timing. 2008/04/16 ISPD
5 Difficulties of noise aware timing analysis Cell position (spatial) Switching timing (temporal) affect gate delay. B A Voltage A temporal spatial difference A: t 1 : delay(t delay(a) 1 ) > delay(t 2 ) B: delay(b) t 2 : delay(t delay(a) 1 ) < delay(t 2 ) B delay(b) t 1 t 2 Time Position of critical paths and spatial and temporal variation must be considered simultaneously. 2008/04/16 ISPD
6 Proposed approach (Overview) Voltage Time Power supply noise including spatial and temporal variation of power supply noise Statistical model Circuit structure SSTA Probab bility Estimate the worst-case delay. Delay Delay distribution 2008/04/16 ISPD
7 Agenda Background and objective Statistical modeling of power supply noise SSTA with statistical model of power supply noise Experimental results Conclusion 2008/04/16 ISPD
8 Modeling flow Power supply noise Spatial and temporal division. Power variables 1. Gaussianization: if necessary improve Gaussianity of the variables. Statistical model 2. Orthogonalization: transform the correlated variables into the uncorrelated variables. 2008/04/16 ISPD
9 Spatial and temporal division remove spatial and temporal continuity for variable assignment 1 Cycle oltage Vo V x,y,3 V x,y,1 V x,y,2 V x,y,3 V x,y,1 Time ex) divide a clock cycle into 3 time spans. spatial division temporal division choose a representative value use average voltage in each span. for each partition. 2008/04/16 ISPD
10 Assigning variables and obtaining distribution 1 Cycle V x,y,1 ty Voltage different clock cycle => different sample Probabilit Voltage V xy3 x,y,3 V xy1 x,y,1 V xy2 x,y,2 V xy3 x,y,3 V xy1 x,y,1 Time Data set of power variables calculate average, standard deviation and correlation coefficient can model spatial and temporal variation. Probability Probability V x,y,2 Voltage y Vx,y,3 Voltage 2008/04/16 ISPD
11 Correlation of power variables ltage Vo oltage Vo Time Time spatial correlation Volt tage 1 cycle Time temporal correlation Voltage drop tends to be similar. Voltage drop lasts awhile. spatial correlation temporal correlation Correlation of power variables is strong. 2008/04/16 ISPD
12 Correlation s effect on delay Correlation between variables affects delay distribution. ex) SUM operation V 1 V 2 Pro obability V 1,V 2 : no correlation V 1,V 2 : positive correlation Delay Delay calculation considering correlation is inevitable. i Computationally expensive. 2008/04/16 ISPD
13 Orthogonalization Orthogonalization by principal component analysis (PCA) Delay calculation considering correlation is facilitated [1]. Compact statistical model is derived when strong correlation exists. Compatibility with SSTA developed for manufacturing variability [1]. z i : original variable compac t μ i σ i λ j e ij pc j : average of z i : standard deviation of z i : jth largest eigenvalue : jth eigenvector corresponding to z i : jth principal cpa component (PC) [1] H. Chang, et. al., Statistical Timing Analysis Under Spatial Correlations, IEEE TCAD, Vol. 24, No. 9, Sep k, k : number of PCs 2008/04/16 ISPD
14 Gaussianization PCA assumes Gaussian distribution. Some variables might be different from Gaussian. improve Gaussianity of the variables before PCA. Box-Cox transformation Λ: Every variable has the optimum value individually. id original distribution transformed distribution Box-Cox transformation 2008/04/16 ISPD
15 Agenda Background and objective Statistical modeling of power supply noise SSTA with statistical model of power supply noise Experimental results Conclusion 2008/04/16 ISPD
16 Gate delay calculation canonical gate delay model considering i power supply noise. receiver side driver side σ V** : standard deviation of V** : sensitivity of V** to d* e (V**),j : jth eigenvector corresponding to V** How are these parameters(μ r, A r,j ) decided? 2008/04/16 ISPD
17 Parameter calculation Parameters of canonical delay model must consider not only cell position but also switching timing, Parameters are set based on arrival time. If switching timing crosses over the boundary of two time spans. => calculate weighted-average g of two spans. μ r,a r,j arrival time 1 cycle Time 2008/04/16 ISPD
18 Agenda Background and objective Statistical modeling of power supply noise SSTA with statistical model of power supply noise Experimental results Accuracy of proposed SSTA SSTA with reduced model SSTA considering i power supply noise and manufacturing variability Conclusion 2008/04/16 ISPD
![Experimental conditions noise generators, two circuits, FPU[2]](/docs-images/82/86227459/images/19-0.jpg "(90nm process, 39k gates), tiny64 processor[2] (90nm process,")
19 Experimental conditions noise generators, two circuits, FPU[2] (90nm process, 39k gates), tiny64 processor[2] (90nm process, 20k gates), size: 1mm x 1mm, input vector: random, 2000 clock cycles, circuits for timing analysis, ISCAS85 (5 circuits), 64-bit multiplier, ALU, H-tree (evaluation of clock jitter), FPU の電源網 [2] OPENCORES.ORG, /04/16 ISPD
20 Procedure of accuracy evaluation compare proposed SSTA and Monte Carlo STA (MC) using the same noise information given to PCA. power supply noise modeling MC delay distribution (MC) comparison statistical model proposed SSTA SSTA includes errors that originate from discretization, PCA for incomplete Gaussian distribution, SSTA operation. delay distribution (proposed p SSTA) 2008/04/16 ISPD
21 Accuracy of proposed SSTA SSTA MC circuit # cells MC avg (%) sd (%) c c c c c multiplier ALU H-tree average Proposed SSTA estimates the delay accurately. Estimation errors without Box-Cox transformation (avg: 0.465%, sd: 14.4%), 4%) => non-gaussianity was not significant but Box-Cox transformation improved results slightly. noise generator: FPU spatial division number: 10x10 temporal division number: /04/16 ISPD
22 Evaluation of variable reduction Evaluate accuracy and CPU time with the reduced d number of principal i components (PCs). noise generator: tiny64 circuit: multiplier spatial division number: 10x10 temporal division number: 10 => total 2000 variables (power + Opteron 2.4GHz #PCs reduction # PCs avg g(p (ps) sd (ps) CPU time reduction rate (ms) of CPU time (%) reduce CPU time largely with little loss of accuracy. 2008/04/16 ISPD
23 SSTA result both for power supply noise and manufacturing variability Proposed SSTA has a compatibility with SSTA developed for manufacturing variability. => can perform SSTA considering manufacturing and supply voltage fluctuation simultaneously. noise generator: FPU circuit: multiplier spatial division number: 10x10 temporal division number: 10 Vth variation: σ = 25mv SSTA considering both variabilities has a possibility to reduce timing margin. 2008/04/16 ISPD
24 Conclusion Proposed SSTA can consider dynamic power supply noise with PCA. Errors of proposed SSTA average: 0.456%, standard deviation: 12.7%. SSTA with the partial model reduced d CPU time more than 98% almost without loss of accuracy. Proposed SSTA can be performed considering manufacturing and supply voltage fluctuation simultaneously. 2008/04/16 ISPD
25 2008/04/16 ISPD
26 Calculation with switching transition calculate weighted-average of the parameters corresponding to input and output t transition timing. i 1. estimate t O with the use of μ r m. μ r,a r,j Span #(m) Span #(m+1) 2. calculate weighted-average based on Δt I and Δt O. average coefficient Δt I Δt O Time t I t O switching term (μ r m ) Circuit delay is calculated according to conventional SSTA. 2008/04/16 ISPD
27 Clock Skew Analysis Easily perform by application of clock jitter analysis. k ' + jitter = μ a 1 1 j=1 1, j pc j jitter 2 = μ 2 + k ' j= 1 a pc 2, j j skew 1,2 ( k ' μ μ ) + ( a a ) pc = 1 2 j=1 2008/04/16 ISPD , j 2, j j
28 Adaptive spatial discretization Power supply noise has heavily fluctuating area. => fine division calm area. => coarse division Spatial distribution of Adaptive discretization of FPU noise (average). FPU noise. 2008/04/16 ISPD
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