A Framework for Layout-Level Logic Restructuring. Hosung Leo Kim John Lillis

Transcription

1 A Framework for Layout-Level Logic Restructuring Hosung Leo Kim John Lillis

2 Motivation: Logical-to-Physical Disconnect Logic-level Optimization disconnect Physical-level Optimization fixed netlist Limited by the structure obtained from the logic-level Performance is determined largely by physicallevel Interconnect delay. Problem: timing optimization at logic-level actual performance.

3 Past Layout-Driven Restructuring Work: Replication Based Basic Operations: Gate Splitting Fanout Partitioning; Enables Path Straightening [Schabas, Brown. ISFPGA03] [Beraudo, Lillis. DAC03] [Hrkic, Lillis, Beraudo. TCAD06] [Chen, Cong. ISFPGA05]

4 Limitation of Logic Replication While interconnect delay can be significantly reduced, the LUT-depth of a path remains unchanged. The LUT-depth is typically determined by a technology mapper which does not have an accurate view of critical paths. Candidate: Remapping

5 Other Work Redundant Wires (e.g., [Chang, Cheng, Suaris, Marek- Sadowska. DAC00]) rewire connections while keeping logical equivalence. Predictable, but optimization scope limited [Lin, Jagannathan, and Cong. ISFPGA03] Remap based on placement-level timing analysis Significant restructuring, but placement of remapped cells determined by initial placement (not simultaneous). [Singh and Brown. Integration07] Shannon s expansion / precomputation Allows late signals to skip logic levels, but relatively local in nature

6 Objectives Overcome limitations of basic replication (e.g., fixed LUT-depth) Large and flexible remapping space Explicitly account for placement freedom of remapped LUTs Tight coupling with placement

7 Components of Approach (FPGA Domain) Placement-Level Static Timing Analysis Timing-Critical Fan-in Cone Extraction Induce Replication Tree [Hrkic,TCAD06]

8 Components of Approach (cont d) Replication tree Recursive, Exhaustive Ashenhurst LUT Decomposition Subject Graph (Choice Tree) Mapper and Embedder (Dynamic Programming) Legalizer A A choice node i j k l a B C a b c d e f g h (a) Given LUT-tree k j i l i j k l i k j l b R d i j k l B choice node C choice node e c R g 1 g 4 g 6 g 7 g 2 c d g 3 g 5 d c c d g 8 cd a b e h h e e g f h f a b f g a b c d e f g h (b) Choice tree

9 Remapping Example A B A B d E a b c C D e f g h i j k l (a) Given LUT-tree m E d e m C D a b c h f g i j k l (b) Mini-LUT tree after LUT-decompositions A B A E a b d e m C D c h f g i j k l (c) Alternative mapping de E B a b c C D f g h i j k l (d) Corresponding LUT-tree m

10 Functional Decomposition Simple Disjoint Functional Decomposition Test for decomposability Ashenhurst s theorem xy wz g 1 f 1 bit (Simple) x y Recursively decompose w x y z g 2 disjoint w z

11 All Recursive Decompositions f a b c d f a b c d g 3 a b g 3 g 2 c g 6 c d g 1 d g 3 a b g 8 g 5 d g 7 a b g 4 c g 1 g 2 d g 2 g 3 c g 3 a b g 4 g 5 c g 5 g 3 d g 6 g 3 c d g 7 a b g 8 g 8 c d ab cd

12 Choice Tree [Lehman,TCAD97] A i j k l A choice node B C l k l j l a b c d e f g h (a) Given LUT-tree k j i i j i k i j k l B choice node C choice node g 1 g 4 g 6 g 7 g 2 d g 5 c c d g 8 a b h e f h c g 3 d cd e h e g a b f g a b c d (b) Choice tree e f g h

13 Algorithm Mini-LUT Tree Mapping Fan-in Tree Embedding [Hrkic,TCAD06] Simultaneous Remapping and Embedding

14 Logic Remapping Formulation Formulation Given a mini-lut tree and arrival time at the leaves, map the tree to K-input LUTs minimizing cost subject to an arrival time constraint at the root. a b c d e f g h i j k l m

15 Solution Signature (c,a) for a sub-tree rooted u, a solution is characterized by two parameters: cost of the embedding (and remapping) of a sub-tree. arrival time at u. Dominance Relation (c,a) is not dominated by (c,a ) when c is better than c or a is better than a. arrival time cost

16 Solution Sets J S i [u] = {(c,a)} u: signal produced by root LUT i: # inputs of root LUT c: # LUTs in subtrees a: the latest among the fan-ins. S i [u] finalized solution from S i [u]. c: # LUTs in subtrees + 1 a: the root LUT included. S[u] non-dominated_sol(s 2 [b],, S K [b]) J u h i (0,6)(0,2) J S 2 [u]={(0,6)} u h i (0,6)(0,2) S 2 [u]={(1,7)}

17 J S i [u] Example For simplicity: one LUT = one unit cost one LUT = one unit delay

18 S i [u] and S[u] Example S i [b] S[b] = non-dominated_sol(s 2 [b],, S K [b]) = {(1,7)}

19 Computation of S i [u] J L R i = 1, no collapsing of u and L i = K-1, no collapsing of u and R Otherwise, collapsing of u, L, and R. i (a) K - i u u i = 1 a b i = 2 a b i = 3 (=K 1) c d c d K = 4 (b) (c) (d) J J J J J S 4 [u] = join(s[a],s 3 [b]) join(s 2 [a], S 2 [b]) join(s 3 [a],s[b])

20 Remapping Algorithm Example b a c arrival time d e f g (0,4) h i j k l m (0,6)(0,2)(0,3)(0,2)(0,1)(0,4) (a) Subject Tree

21 Algorithms Mini-LUT Tree Mapping Fan-in Tree Embedding [Hrkic,TCAD06] Simultaneous Remapping and Embedding

22 Tree Embedding [Hrkic,TCAD06] topology arrival time pin locations c R a b R d (0,4) e a c R b R d e (0,3) f (0,2) target layout graph cost metrics a Embedding Algorithm arrival time a f d b R d e e c R f f

23 Algorithms Mini-LUT Tree Mapping Fan-in Tree Embedding [Hrkic,TCAD06] Simultaneous Remapping and Embedding

24 Simultaneous Remapping and Formulation Embedding Given a mini-lut tree with fixed leaves and root, and arrival time at the leaves, a target layout graph Simultaneously map the tree to K-input LUTs and embed.

25 Solution Set S i [u][v] J The remapped root produces signal u and is placed at v in the target layout graph.

26 Solution Set S i [u][v] J Solutions S i [u][w] are finalized and drives vertex v in the target layout graph. Computed by shortest weight-constrained path algorithm. u S i [u][v] v w h i j k

27 Solution Set S[u][v] S[u][v] non-dominated-sol(s 2 [u][v],,s K [u][v]) The best remapping regardless of the number of inputs at v in the target layout graph.

28 Simultaneous Remapping and Embedding Example a v 23 b c h g d e f g i m h i j k l m (c) S 4 [a][v 23 ]={(22,10)} j k l arrival time (19,13) (20,11) (22,10) cost (c) S[a][v 23 ]={(19,13),(20,11),(22,10)}

29 Benchmarks Experiment 20 MCNC benchmark circuits At least 20% white space Comparisions Timing-driven VPR placer Replication Tree embedder Arbor embedder [Kim,GLSVLSI06] Remapping embedder Criteria of Interest LUT depth Clock period of circuits Different logic-level mappers and Stability effect of new algorithm

30 Optimization Flow Initial Netlist & Placement Static Timing Analysis & Replication Tree Construction Modified Netlist Tree Embedding Post-Processing & Legalization Repl Tree embedder Remapping embedder Modified Netlist & Placement

31 LUT Depth Changes Crit. Path Crit. Path ckt ckt s apex2 9 8 seq 8 8 dsip diffeq 9 9 alu4 9 9 misex3 9 8 apex tseng 9 9 ex5p New ckt Init. ckt Crit. Path Crit. Path ckt ckt clma s s pdc ex elliptic spla frisc 5 5 bigkey 8 8 des New ckt Init. ckt

32 Routed Clock Period ex5p tseng apex4 misex3 alu4 diffeq dsip seq apex2 s298 des bigkey frisc spla elliptic ex1010 pdc s38417 s clma Average Normalized Clock Period Avg Delay T-VPR 1 Repl Arbor Remap Max reduction of REMAP vs Arbor 11.7% VPR Repl Arbor Remap

33 Different Logic-level Mappers and Stability Effect of Remap FlowMap: optimal depth. FlowMap-r: relaxed depth. ZMap: optimal depth with simultaneous area minimization. Praetor: minimized area. Daomap 90 Span: 12% FlowMap FlowMap-r ZMap Praetor Daomap Span: 4% 0 VPR Repl Remap seq

34 Summary Study of layout-level restructuring for interconnect optimization. Functional Decomposition Choice Tree Remapping Algorithm Simultaneous remapping and embedding Experimental Result Average 17% reduction on clock period compared with T-VPR.

35 Thank You!