STATISTICAL TIMING ANALYSIS FOR DIGITAL CIRCUIT DESIGN. Lizheng Zhang

Transcription

1 STATISTICAL TIMING ANALYSIS FOR DIGITAL CIRCUIT DESIGN by Lizheng Zhang A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) at the UNIVERSITY OF WISCONSIN MADISON December 2005

2 c Copyright by Lizheng Zhang December 2005 All Rights Reserved

3 To my wife, Chang Dong for her consistent support to make my concentrated research possible i

4 ii ACKNOWLEDGMENTS This work is done under the decent advice of professor Charlie Chungping Chen and Yuhen Hu. Professor John A. Gubner and Barry D. Van Veen give great suggestions in non-gaussian statistical timing analysis. Professor Jun Shao helps a lot in the quadratic variation modeling and parameter estimation. Professor Kewal K. Saluja helps me in the delay testing part. Also I would like to thank my officemates Weijen Chen and Jengliang Tsai. Weijen Chen helps me in most of the statistical timing research. Jengliang Tsai gives help in the latch timing analysis. This thesis work is partially funded by TSMC, UMC, Faraday, SpringSoft, National Science Foundation under grants CCR & CCR and National Science Council of Taiwan, R.O.C. under grant NSC E Thank you!

5 iii TABLE OF CONTENTS Page LIST OF TABLES LIST OF FIGURES vi vii ABSTRACT x 1 Circuit Parameter Variations and Correlations Circuit Timer in Circuit Design Parameter Variations Traditional Corner-based Timing Method Review of Existing SSTA Algorithms Timing Variable Propagation Linear Approximation of MAX Operator Canonical Timing Model Problems in the Existing SSTA Algorithms Path Reconvergence Spatial Correlation Non-linearity of MAX/MIN Operators Delay Testing and Statistical Timing Non-Gaussian Gate/Wire Delay Non-Gaussian Parameter Variation Modeling Latch with Feedback Loops Gaussian Delay: First-Order Statistical Timing Analysis Extended Pseudo-Canonical Timing Model Tuple-based MAX Operation Non-Linearity of MAX Operator Non-Linear Condition Circuit Timing with Max Tuples Statistical Timing Algorithm Sparsity of Local Variation Vector Sensitivity Drop-and-Lump Fanout-based Sensitivity Pruning

6 iv Page 2.5 Analytical Spatial Correlation Model Exponential Spatial Correlation Spatial Correlation Resolution Simulations and Discussions Accuracy Improvement with Max Tuple Accuracy Improvement by Including Path Correlation Linear Complexity Delay Testing and Statistical Timing Linear Prediction with Least Square Error Prediction Error Minimization Heuristic Path Selection Algorithm Non-Gaussian Timing: Quadratic Form of Gaussian Variables Quadratic Gate Delay Model Quadratic Wire Delay Model Correlations and Distributions for Quadratic Timing Model Correlations between Quadratic Timing Variables Distributions of Quadratic Timing Variables SSTA with Quadratic Timing Model Extra Computation Complexity Application in Path Based Timing Analysis Simulations and Discussions Quadratic Modeling for Non-Gaussian Parameters Parameter Variation and Measurement Quadratic Parameter Fitting Confidence Interval Analysis Experiment and Discussions Level-Sensitive Latches with Feedback Loops Latch Timing Preliminary Circuit Convergence Reduced Timing Graph Iterative Timing Theory Graphical Imitation of Iterative Timing Convergence of the Iteration Mean Circuit Yield Prediction Computing Critical Cycle Mean Simulations and Discussions

7 v Appendix Page Accuracy of StatITA Performance of StatITA Timing and Design on Interconnect Pipelining DFF-Pipelined Wire Timing Latch-Pipelined Wire Timing Experiments and Results Full-custom Design of Wave-pipelined Interconnect Timing Constraints in Wave Pipelining Wave Pipelined Interconnect On-Chip CDR Phase Resolution Phase Lock Loop Noise Immunity of Receiver Testing Circuit Design LIST OF REFERENCES

8 vi LIST OF TABLES Table Page 1.1 CMOS technology roadmap Gap between statistical timing analysis and circuit delay testing Error comparison between drop-and-lumping and simple dropping Distribution error with respecting to Monte Carlo simulations: (1)WiscStat: SSTA method with EPCT model;(2)nopath: SSTA with existing canonical timing model where no path correlation is considered;(3)nocorr: SSTA with neither global correlation nor path correlation Circuit size N, average size of local variation vector(γ), mean (µ) and standard deviation(σ) of the output arrival time with/without fanout-based sensitivity pruning(fbsp). Sensitivity drop-and-lump is always applied Distribution Parameters for ISCAS Circuits with three Approaches: (1)Monte Carlo(M.C.); (2)Canonical Model(CanoStat); (3)Quadratic Model(QuadStat). Errors in parenthesis for CanoStat and QuadStat are computed using M.C. as standard Sink node s max tuple size, average tuple size and CPU time of CanoStat and QuadStat % yield clock cycle(t 97 ) and CPU time comparison between StatITA and MontITA Distribution Parameters for Delay Elements

9 vii LIST OF FIGURES Figure Page 1.1 Circuit timer identifies good designs(gray dots) out from bad designs(black dots) Correlation in timing parameter variations Corner-based timing analysis: 2 n corners for n parameters Complexity problem in path-based approach Path Correlation: both X and Y depend on local variation of P Quad-tree model underestimates the spatial correlation between wire segments 4 and Linear approximation underestimates MAX result at high probability level Non-Gaussian wire delay when wire width and thickness are Gaussian A simple latch circuit with a feedback loop and the possible divergence of the standard deviation of the departure time distribution Skewness of Z = max(x, Y ) given X and Y are Gaussian v.s. Non-Linearity of MAX Operator Determined by Monte Carlo simulation Skewness of max(x, Y ) when Y N(0, 1) Block-Based SSTA Algorithm Circuit with linear structure has timing complexity O[N 2 ] Fanout-based sensitivity pruning for arrival times A,B,C and D in an example circuit Spatial correlation matrix with correlation distance r c = 100µm Circuit whose timing variables are NOT Gaussian

10 viii Figure Page 2.8 Comparison of c.d.f. for Non-Linear Circuit between (1)existing linear approximation (2)conditional linear approximation with skewness threshold 0.5 and final tuple size of p.d.f. and c.d.f. comparison for c6288 from three methods Linear complexity of WiscStat with respecting to the circuit size N and global parameter number M Statistical circuit delay Y and statistical path delays P 1,P 2,,P k for designed circuit(left); deterministic circuit delay y and deterministic path delays p 1,p 2,,p k (right) Linear prediction One iteration from Y 0 to Y 1 in the path selection where path P 3 is selected Linear prediction error as a function of number of selected paths and number of global variation sources affecting circuit delay. The total number of path candidates is Distributions of Inverter Delay with parameter variations σ/µ = 30% Distributed Wire Delay Model Wire Delay Distribution Comparison from Three Approaches p.d.f. comparison between Monte Carlo and our linear approximation for D Z = max(x + kx 2,Y + ky 2 ) at different quadratic coefficients k where X and Y are independent standard Gaussian random variables Example Circuit for Path-Based timing analysis Distribution Comparison of Path Based Timing Analysis: (1)Monte Carlo; (2)Canonical Model Based; (3)Quadratic Model Based Distribution Comparison of ISCAS c3540 from Three Approaches: (1)Monte Carlo; (2)Canonical Model; (3)Quadratic Model Variation Sources p.d.f.s of quadratic form fitting based on N = 1000 measurement data for Gaussian and non-gaussian parameter. κ/σ is the skewness coefficient of the parameter

11 ix Appendix Figure Page 3.10 Estimation error ɛ for Gaussian distribution at different measurement data size N Estimation error ɛ for non-gaussian distribution at different measurement data size N Estimation error ɛ for Gaussian and non-gaussian distribution at different measurement data size N Notation used in this chapter Latch Timing Diagram The reduced timing graph of an example circuit The iteration mean of three nodes in the example circuit of figure 4.3 and their convergence trend Loop c and a node j Critical cycle mean G c for circuit s526 computed from StatITA and MontITA at clock cycle of 400ps Run time of StatITA v.s. circuit size DFF Pipelined Interconnect Stage Latch Pipelined Interconnect Stage Latch Timing BER and Throughput v.s. Mean Clock Frequency Timing Constraints of Wave Pipelined Computation Wave pipelined Interconnection Receiver of Wave Pipelined Interconnect PLL Timing GHz Testing Circuit Diagram

12 STATISTICAL TIMING ANALYSIS FOR DIGITAL CIRCUIT DESIGN Lizheng Zhang Under the supervision of Assistant Professor Charlie Chungping Chen At the University of Wisconsin-Madison When the device size in digital circuits scales down to nanometer region, the parameter variation will significantly affect the circuit performance and the traditional corner-based timing analysis methods are often too pessimistic to accommodate increasingly aggressive design goals. Statistical timing analysis, which models the parameter variation statistically, becomes a promising variationaware solution for the digital circuit design at the nanometer era. The first difficulty of statistical timing comes from the numerous types of timing variable correlations caused by inter-parameter dependency, parameter s spatial dependency, circuit s path reconvergence and the coexistence of transparent latches and feedback loops etc. We construct a comprehensive statistical timing framework to include all of these correlations to improve the timing accuracy. The second difficulty of statistical timing comes from the non-linearity of the timing analysis and the non-gaussianity of the timing variables. We also propose algorithms to deal with these non-idealities inside our statistical timing framework. Eventually, statistical timing analysis will take inputs from the manufacturing parameter measurements and generate outputs of timing predictions to the post-silicon delay testing. To complete such a timing flow, we firstly propose a quadratic fitting method to generate the input parameter models from measurement data. We also propose a linear prediction model which combines the statistical timing and delay testing results to provide circuit performance estimation while reducing the testing cost. Charlie Chungping Chen

13 x ABSTRACT When the device size in digital circuits scales down to nanometer region, the parameter variation will significantly affect the circuit performance and the traditional corner-based timing analysis methods are often too pessimistic to accommodate increasingly aggressive design goals. Statistical timing analysis, which models the parameter variation statistically, becomes a promising variationaware solution for the digital circuit design at the nanometer era. The first difficulty of statistical timing comes from the numerous types of timing variable correlations caused by inter-parameter dependency, parameter s spatial dependency, circuit s path reconvergence and the coexistence of transparent latches and feedback loops etc. We construct a comprehensive statistical timing framework to include all of these correlations to improve the timing accuracy. The second difficulty of statistical timing comes from the non-linearity of the timing analysis and the non-gaussianity of the timing variables. We also propose algorithms to deal with these non-idealities inside our statistical timing framework. Eventually, statistical timing analysis will take inputs from the manufacturing parameter measurements and generate outputs of timing predictions to the post-silicon delay testing. To complete such a timing flow, we firstly propose a quadratic fitting method to generate the input parameter models from measurement data. We also propose a linear prediction model which combines the statistical timing and delay testing results to provide circuit performance estimation while reducing the testing cost.

14 1 Chapter 1 Circuit Parameter Variations and Correlations 1.1 Circuit Timer in Circuit Design Modern CMOS circuits will usually include millions of transistors. It is impossible to manually verify such a huge circuit design satisfies the performance goal, instead, a program called circuit timer will be used. A golden timer can identify all good designs while no bad deigns are considered as good designs by mistake. As shown in figure 1.1, a golden circuit timer shouldn t be optimistic with which many bad designs are identified as good although no good design is excluded as bad. Such a timer will then sign off a lot of bad designs and so that significantly degrade the circuit time yield. A golden circuit timer should neither be pessimistic with which many good designs are wrongly identified as bad although no bad design is considered as good. Pessimism is not beneficial since it will waste a lot of design effort which is also very expensive for large circuits. Optimistic Golden Pessimistic Figure 1.1: Circuit timer identifies good designs(gray dots) out from bad designs(black dots)

15 2 A golden circuit timer is also demanded when a circuit is optimized for performance. Since it is not possible to manually optimize a million-gate circuit, a program called circuit optimizer will be used. The optimizer will twist the circuit design and ask the timer to see if the modification enhances the circuit performance. If the answer is yes, then the optimizer will continue to make the modification in the same direction. Otherwise, optimizer will try modification in other directions. So the circuit timer will perform as a judge during circuit performance optimization. Error in the timing will possibly mis-guide the optimizer and degrade the circuit performance eventually. 1.2 Parameter Variations When technology scales down to nanometer, uncontrollable parameter variations will significantly affect the circuit timing performance. As shown in table 1.1, the magnitude of parameter variations cannot scale down as fast as the nominal values, so parameter variation, as a percentage of the nominal value, becomes larger and larger. Parameters Nominal Values 3σ Values Years L eff [nm] T ox [nm] V dd[v ] V th [mv ] W [µm] H[µm] ρ[ mω ] Table 1.1: CMOS technology roadmap Circuit timing parameters are not independent to each other. They are, instead, correlated with each other as shown in figure 1.2(a). For example, variations in gate capacitance are not

16 3 independent to the variations in gate length. Variations in threshold voltage is not independent to that in the gate length either. Moreover, there are two types of orthogonal timing parameter variations: inter-die variations and intra-die variations. Inter-die variations, also called global or systematic variations, represent the parameter variations from chip to chip for the same circuit. The intra-die variations represent the parameter variations within the same die but different locations. Due to the way circuits are manufactured, these intra-die variations in different chip locations are also dependent to each other. Such intra-die location-related correlations are then called spatial correlations as shown in figure 1.2(b). Parameter Correlations (a) Inter-parameter correlations Spatial Correlations (b) Spatial correlations in intra-die variations Figure 1.2: Correlation in timing parameter variations 1.3 Traditional Corner-based Timing Method Circuit timing parameter variations and their correlations have been recognized for a long time. Traditionally, to ensure the requested timing yield in the existence of parameter variations and correlations, corner-based deterministic static timing analysis is proposed as shown in figure 1.3. Two corners, called worst case and best case, as shown in figure 1.3(a), will be individually timed for the single parameter variation. But when two parameter variations are significant, there will be four corners to be timed individually as shown in figure 1.3(b). So when number of parameter variations are large, there will be exponential number of corners needed to be timed individually. This

17 4 fact makes the classical corner-based timing analysis cumbersome and not efficient. Furthermore, the pessimism token in the corner-based approach will be amplified if more and more parameter variations are considered. For example, if there are 20 parameter variations and each parameter is considered at its 99% corner, then the corner-based approach will have to individually cover 2 20 =1M corners and the resulted timing yield is which is much more pessimistic than the requested value of 1%. Best Corner Worst Corner (a) Two corners for single parameter (b) Four corners for two parameters Figure 1.3: Corner-based timing analysis: 2 n corners for n parameters 1.4 Review of Existing SSTA Algorithms Due to the parameter variations and their correlations, classical corner-based timing analysis produces timing predictions that are often too cumbersome and pessimistic. To overcome such problem, statistical static timing analysis (SSTA) has been proposed which characterizes timing delays as statistical random variables and offers fast and accurate timing predictions. Existing SSTA methods can be categorized into two distinct approaches: path-based SSTA [1 4] and block-based SSTA [5 10]. The path based SSTA seeks to estimate the circuit performance based on selected critical paths. However, the task of selecting a subset of paths which are statistically critical has a worst-case computation complexity that grows exponentially with respect to the circuit size. Hence the path based SSTA is not easily scalable to handle realistic circuits.

18 Number of paths are exponential to the gate number in the circuit in the worst case Path-based operations: 92 ADD, 21 MAX Block-based operations: 10 ADD, 12 MAX Assume 1 MAX = 5 ADD: Speedup = 2.8 x Figure 1.4: Complexity problem in path-based approach The block based SSTA, on the other hand, champions the notion of progressive computation. Specifically, by treating every gate/wire as a timing block, the SSTA is performed block by block in the forward direction in the circuit without looking back. Signals propagating through timing blocks will add gate/wire delays into the arrival time. Delays and arrival times are both called timing variables of the circuit. As such, the computation complexity of the block based SSTA would grow linearly with respect to the circuit size. The complexity comparison between these two approach for a simple circuit is shown in figure 1.4 where the block-based approach shows 2.8 speedup even in such a simple case Timing Variable Propagation In block-based SSTA, a timing variable is modeled as a random variable that is characterized by its distribution of probability density function(p.d.f.) or equivalently, cumulative distribution function(c.d.f.). The goal of statistical timing analysis is to estimate the distribution of arrival times

19 6 in the circuits given the distributions of each block delay in the circuit. To accrue the overall timing variable distribution, the random timing variables will be joined through two basic operators [5]: ADD: When an input arrival time X propagates through a block with delay Y, the output arrival time will be Z = X + Y MAX: When two input arrival times X and Y merge in a block, a new arrival time Z = max(x, Y ) will be formulated. In the ADD operation, if both X and Y are Gaussian random variables, then Z = X + Y will also be a Gaussian random variable whose mean and variance can be found as: µ Z = µ X + µ Y (1.1) σz 2 = σ2 X + σ2 Y +2σ XY (1.2) where σ XY = cov(x, Y )=E{(X µ X )(Y µ Y )} is the covariance between X and Y. Since MAX is generally a nonlinear operator, Z = max(x, Y ) will not have Gaussian distribution even if both X and Y are Gaussian. However, in this situation, the mean, variance and skewness of the distribution of Z have been already derived analytically by Clark [11] in 1961 as follows: µ Z = µ X Q + µ Y (1 Q)+θP (1.3) σz 2 = (µ 2 X + σx)q 2 +(µ 2 Y + σy 2 )(1 Q)+ (µ X + µ Y )θp µ 2 Z (1.4) κ 3 Z = (µ3 X +3µ XσX 2 )Q +(µ3 Y +3µ Y σy 2 )(1 Q) µ Z(3σZ 2 + µ2 Z ) (1.5) + P θ {(µ2 X + µ X µ Y + µ 2 Y )θ 2 +2σX 4 + σxσ 2 Y 2 +2σY 4 2σ XY (σx 2 + σy 2 ) σxy 2 } where θ = σ (X Y ) and the skewness of random varaible Z is defined as: κ Z = 3 E{(Z µ Z ) 3 } (1.6) P and Q are the p.d.f. and c.d.f. of a standard normal distribution evaluated at λ = µ (X Y ) /σ (X Y ) : P (λ) = 1 exp( λ2 ) and Q(λ) = 2π 2 λ P (x)dx (1.7)

20 Linear Approximation of MAX Operator Although Z = max(x, Y ) is not a Gaussian random variable even both inputs X and Y are Gaussian, in the interest of simplicity, it is still desirable to find a Gaussian random variable Ẑ that approximates Z ( [6, 10]): Z = MAX(X, Y ) QX +(1 Q)Y + Pθ = Ẑ (1.8) where θ = σ (X Y ) and P, Q are defined in Equation (1.7). In [11], it has also been shown that if W is a Gaussian random variable, then the covariance between W and Z = MAX(X, Y ) can be found analytically as: cov(w, Z) = Q cov(w, X)+(1 Q)cov(W, Y ) (1.9) Substituting equation (1.8), it is easy to verify that cov(w, Ẑ) =Q cov(w, X)+(1 Q)cov(W, Y )=cov(w, Z) Hence, a nice property of the approximator Ẑ shown in equation (1.8) is that the cross-covariance between Z and other timing variable W is preserved when Z is replaced by Ẑ. We hereby prove that such a MAX approximation will minimize the error function as: + [max(x, y) ψ(x, y)] 2 f XY (x, y)dxdy = E{Z 2 } + E{Ẑ2 } 2E{ZẐ} (1.10) where f XY (x, y) is the joint distribution of X and Y and Ẑ = ψ(x, Y ) is an approximation of Z = max(x, Y ). So if function Ẑ = ψ(x, Y ) includes parameters of λ 1,λ 2,..., to minimize such an error function, the optimum values of λ i will be determined by the following optimal condition: E{Ẑ Ẑ } = E{Z Ẑ } (i =1, 2,...) (1.11) λ i λ i Such an optimal condition, if applied to the case of linear approximation Ẑ = ax + by + c, the optimal values of a, b and c will be the solution of equations: E{Z} = aµ X + bµ Y + c cov(z, X) = a σx 2 + b cov(x, Y ) cov(z, Y ) = a cov(x, Y )+b σy 2 (1.12)

21 8 Using equations (1.3) and (1.4), a, b and c can be solved as: a = Q; b =1 Q; c = Pθ (1.13) which match the approximation equation (1.8) Canonical Timing Model Previously, a canonical timing model [6, 7, 10] has been proposed to address the delay correlations through shared parameter variations. In this model, the i th block s delay in the circuit is represented as: n i = µ i + α i R i + β i,j G j (1.14) j=1 where µ i is the expected value of n i ; R i, called local variation, represents the parameter variation which only affects the considered timing block; G j, called global variation, represents the parameter variation which will affect more than one timing blocks; R i,g 1,G 2,... are all assumed to be mutually independent standard Gaussian random variables; the weight parameter α i (named local sensitivity) and β i,j (named global sensitivities) are deterministic constants which explicitly express the sensitivities of n i on each of the corresponding parameter variation sources. With such canonical representation, the variance of a block delay n i and its covariance with another block delay n k can be evaluated as: σ 2 n i = E{(n i µ i ) 2 } = α 2 i + j β 2 i,j cov(n i,n k ) = E{(n i µ i )(n k µ k )} = j β i,j β k,j 1.5 Problems in the Existing SSTA Algorithms Although the existing SSTA methods with canonical timing model and linear MAX approximation is efficient, it is still in the very beginning state of developing and there are many problems needed to be solved in order to improve it.

22 Path Reconvergence The importance of the path correlation comes from the fact that each gate/wire block in the circuit will have some local variations which are independent to the rest of the circuit. These local variations will propagate towards the circuit output and cause additional correlations due to the phenomenon of path reconvergence. Such path correlations, caused by sharing local variations along the path history, cannot be correctly captured if the arrival time is expressed as the canonical form of (1.14) since the only one term of local variation in the timing model is assumed to be purely random and independent and no path history information is maintained. P X Y Figure 1.5: Path Correlation: both X and Y depend on local variation of P For example, for the partial circuit showing in figure 1.5, both arrival times X and Y will be dependent on gate P s local variation R P. But at the time when X and Y are merged together, their local variation terms R X and R Y will not remember their common dependence on R P so the corresponding path correlation will be incorrectly ignored Spatial Correlation Another significant disadvantage of the canonical form of (1.14) is that it requires the independency between the global variations G i in the canonical timing model (1.14), as stated in [10]. Such independency will be satisfied by Principle Component Analysis(PCA) prior to the timing analysis if the original global variations are statistically correlated. But the complexity of the PCA grows as quickly as O[M 3 ] where M is the total number of global variations considered. Due to the important spatial correlation, the number of global parameters considered in the PCA will easily go up to thousands and so that PCA itself will be a very timing consuming step.

23 10 For example, to model the spatial correlation, the chip is usually covered by grids and each grid cell will be associated with a global parameter. So the total number of global variations will be equal to the number of grid cells. Assume that we have 10mm 10mm chip and the effective spatial correlation distance is about 100µm. Then the grid with cells is still rather coarse to model the spatial correlation. However, even such a coarse grid requires eigenvalue decomposition (EVD) or singular value decomposition (SVD) of a covariance matrix with the PCA-based approach. This is rather expensive computationally even if the covariance matrix is sparse. Moreover, in this example, global variations apart by 200µm are practically independent. So the rank of the covariance matrix in this case will be at least = Therefore, we cannot reduce the number of independent variables by PCA further than 2500 in order to correctly model those spatially correlated global parameter variations. So in the PCA-based approach, we need to compute 2500 eigenvalues and 2500 eigenvectors for a covariance matrix. So far there is no efficient computational method to achieve this. To avoid the expensive PCA computation, so-called quad-tree model has been proposed in [7]. A quad-tree is built to connect the grids cells together and the correlations between the global variations in the grid cells are represented by number of parent tree nodes they shared. However, this model might cause significant error since there are always nodes which are spatially very close to each other but belong to different subtrees in the quad-tree. So the correlation between these nodes might be significantly underestimated by this model Figure 1.6: Quad-tree model underestimates the spatial correlation between wire segments 4 and 5 For example, if the quad-tree is used to model the spatial correlation in an eight-segment straight wire, as illustrated in figure 1.6, the quad-tree will becomes a binary tree if the quadpartition is along the wire. It is obvious that the correlation between wire segments 2 and 3, 4 and 5 will be similar to that between wire segments 1 and 2 since they are similarly spatially separated.

24 11 But according to the quad-tree model, the spatial correlation between 1 and 2 will be the largest, that between 3 and 4 will be second and that between 4 and 5 will be the smallest. So the quad-tree model fails to give similar spatial correlation when distance is similar Non-linearity of MAX/MIN Operators While the linear approximation of MAX operation shown in equation (1.8) is simple, it doesn t work safely when the non-linearity of the MAX operation is significant. A simple counter example is illustrated in figure 1.7 where the left panel shows the two independent Gaussian random variables that are MAXed together, and the right panel shows the c.d.f.s ofmax(x, Y ) from Monte Carlo simulation and linear approximation. It can be seen from figure 1.7(b) that the existing linear approximation will underestimate the distribution at the high probability level. This behavior is risky since decisions made upon the estimated delay may result in excessive design failure. 4 p.d.f. of X and Y 1 c.d.f. of max(x,y) Monte Carlo Linear Approx (a) p.d.f. of Independent X and Y (b) c.d.f. of max(x, Y ) Figure 1.7: Linear approximation underestimates MAX result at high probability level Delay Testing and Statistical Timing During post-silicon delay testing, we can only measure the delays of those sensitizable paths in the circuit which means the delay testing is fundamentally a path-based approach. Moreover every single path delay measurement result is always deterministic although a set of such measurements

25 12 may allow us draw the underneath statistical distribution properties. Because of the testing cost limitation, it is not feasible to test all possible sensitizable paths. So overall, the delay testing is always deterministic and path-based and with limited path coverage. Statistically timing analysis will only give timing report as statistical distributions instead of deterministic values. Moreover, if the analysis is a block-based approach, the timing result will then have complete path coverage. So as summarized in table 1.2, we see a big gap between the delay testing and the statistical timing: path-based, deterministic delay testing and path or block based, statistical circuit timing. The significance to bridge over such gap is that we can predict the overall circuit delay as a deterministic value by testing delays of a finite set of paths which are even not necessary to be critical. Timing Analysis Delay Testing Report Statistical distributions Deterministic values Approach Block based Path based Path Coverage Complete Limited Table 1.2: Gap between statistical timing analysis and circuit delay testing Non-Gaussian Gate/Wire Delay If global parameter variations are assumed to follow Gaussian distributions [12, 13], the delay computed from the canonical form will always be Gaussian since it is a linear combination of Gaussian random variables. This may be acceptable for cases when the magnitude of variation is small and the nonlinear relationship between the gate/wire delay and the global variation sources is not significant. However, when variation becomes larger as technology scales down to nano-meter, the magnitude of the global variations becomes larger and the non-linearity of the gate/wire delay as a function of the global variations will be more significant and can not be accurately approximated

26 13 by the current linear canonical timing model. So even the global variations are modeled as Gaussian random variables, the gate/wire delays, in general, will not be Gaussian random variables. This yields unsatisfactory results where more accurate SSTA is demanded. T L W 0.8 W Wire delay distribution T Figure 1.8: Non-Gaussian wire delay when wire width and thickness are Gaussian For example, as shown in figure 1.8, the wire delay will be significantly non-gaussian even when wire width and thickness are both Gaussian random variables since the wire delay is a nonlinear function in width and thickness: D(W, T )=ρl 2 ( C s W + C f T ) Non-Gaussian Parameter Variation Modeling Most of the existing SSTA algorithms assume that the statistical characteristics of parameter variations have been calibrated perfectly at the foundry side (almost as a black box). SSTA algorithms then assume Gaussianity and zero errors on these parameters and perform SSTA confidently. In reality, such Gaussianity and zero-error assumptions are actually questionable and require more careful revisions. Due to the limited budget and human resources, there could often be only a few test chips or circuits to be manufactured and measured to estimate the parameter distribution. Therefore, estimation error is finite and has to be carefully analyzed to properly reflect the fidelity of the data

27 14 sources. Using only finite measurement data samples, it is mandatory to consider the confidence interval to make any formal statistical prediction. This effect has been most likely ignored in literatures. Moreover, due to the nature of semiconductor process, even the fundamental process parameter variations such as gate length or interconnect width/thickness may not follow Gaussian distributions. Therefore forcing the parameter distribution to be a Gaussian can potentially introduce large errors. So far, we still lack of efficient and solid statistical model to represent those non-gaussian parameter variations Latch with Feedback Loops With the presence of feedback loop, the timing-wise transparent level-sensitive latches may cause timing random variables to be self-dependent. In other words, a timing random variable will be dependent on a time variable with the same name, but instantiated in the previous clock cycle. Such a self-dependence presents itself as a new type of correlation that is caused by the coexistence of transparent latches and feedback loops. An example of self-dependence is illustrated in figure 1.9. Combinational Logic Distribution of D Iterations k=1 k=2 A C Latch D k=3 k=4 Figure 1.9: A simple latch circuit with a feedback loop and the possible divergence of the standard deviation of the departure time distribution Previously, a SSTA method for latch-based pipeline design have been proposed [14]. However, the issue of self-dependence is not addressed. In [15], a structural method is proposed to deal with the feedback loops by applying graph sorting algorithms. However, as pointed out by authors, the computation complexity of these algorithms may grow exponentially [15].

28 15 In classical deterministic timing analysis, an iterative latch timing algorithm, i.e. the famous SMO algorithm, has been proposed [16 18] to deal with the self dependence. In order to generalize the SMO algorithm to handle random time variables, one faces a convergence problem that can be briefly explained as follows: In deterministic timing analysis, each time variable assumes a deterministic value. Convergence will be guaranteed if each time variable is bounded within a predefined, finite range. However, with SSTA, each time variable is modeled with a mean value and a standard deviation. Even the mean value can be bounded, the corresponding variance may still diverge. This is illustrated in the figure 1.9 too. So we have yet to find an effective SSTA method for sequential circuits consisting of level sensitive latches and feed-back loops.

29 16 Chapter 2 Gaussian Delay: First-Order Statistical Timing Analysis 2.1 Extended Pseudo-Canonical Timing Model The canonical timing model [6, 7, 10] is a powerful tool to represent the numerous timing variables for a given circuit. However, in its original format, it will have problem if the path correlation and/or the spatial correlation are important. In this work, we propose an extended pseudocanonical timing model(epct) that is capable of efficiently capture all the correlation, including inter-parameter correlations, spatial correlations and correlations caused by path reconvergence between any pair of timing variables in the circuit be it a node delay or an arrival time. In the EPCT model, gate/wire delays are expressed as the linear combination of the timing parameters as following: D i = µ i + α i R i + β i,j G j (2.1) j which, compared with the canonical timing model in equation (1.14), relaxes the requirement of the independence of the global variations and so that the global variations G j may be CORRELATED. With such modification, the canonical form will then be suitable to treat the spatial correlation and we will show that it will not have the complexity problem as the original canonical form. The correlation between two gate/wire delays expressed with EPCT model can be evaluated as: cov(d 1,D 2 )= β 1,i β 2,j cov(g i,g j ) (2.2) i j Assume that there are N gate/wire blocks and M global parameter variations in the circuit, if every block delay is modeled by the EPCT format, then every timing variable, including all the

30 17 block delays and arrival times can be expressed as: X = µ X + N M α X,i R i + β X,j G j (2.3) i=1 j=1 where R i s are independent random variables and are also independent to G j s although there will possibly be correlations between G j s. With this equation, path correlations can be handled elegantly since the dependence on path history will be represented by non-zero sensitivity terms α X,k. Equation (2.3) can be rewritten in a compacted vector format as X L(µ X, α X, β X )=µ X + α Xr + β Xg (2.4) where * means transpose and r [R 1,,R N ] N(0, I) and g [G 1,,G M ] N(0, Σ g ) (2.5) are local variation vector and global variation vector respectively. r is independent to g. 0 is a zero vector and Σ g = E{gg } is the covariance matrix of global variations and generally not diagonal due to the potential correlations. α X =[α X,1,α X,2,..., α X,N ] and β X =[β X,1,β X,2,..., β X,M ] are X s deterministic variation vectors. Authors in [10] proves the correlation evaluation formula between timing variables represented by the canonical timing model of equation (1.14). We here prove a similar formula for correlation evaluation between time variables expressed with the EPCT model as equation (2.3) or (2.4). Theorem 2.1: Given timing variables X L(µ X, α X, β X ) and Y L(µ Y, α Y, β Y ), the correlation between them can be evaluated as: cov(x, Y )=α Xα Y + β XΣ g β Y (2.6) Proof: By definition: cov(x, Y )=E{(X µ X )(Y µ Y )} = cov(α X r, α Y r)+cov(α X r, β Y g)+cov(α Y r, β X g)+cov(β X g, β Y g) = E{α X rr α X } + E{β X gg β X } = α X α Y + β X Σ gβ Y where the independence between r and g is applied.

31 18 For the variance of a time variable, it is easy to get: Corollary 2.2: Given timing variable X L(µ X, α X, β X ), its variance is: σx 2 = α Xα X + β XΣ g β X (2.7) This corollary is actually the special case when X = Y of theorem Tuple-based MAX Operation If the MAX operator is significantly non-linear, significant error will occur if a linear operator is forced to approximate the MAX operator. However, for the purpose of timing analysis, it is not always necessary to explicitly compute the MAX output at every propagation step. Instead, we can defer the MAX evaluation until a linear approximation is appropriate. The key to realize such accuracy improvement is then to develop a criteria to decide the case where linear approximation will not have big error Non-Linearity of MAX Operator For Gaussian inputs, the linearity of the MAX operator will be equivalent to the Gaussianity of the output since linear combination of Gaussian random variables is a Gaussian random variable. Using Monte Carlo simulation, the Gaussianity of the output can be evaluated with a method called QQ-Plot [19] Specifically, if the output is Gaussian, then the simulated Monte Carlo output of the MAX operator will show a straight line in its QQ-Plot against a standard Gaussian distribution. And if the MAX output is non-gaussian, such QQ-Plot will deviated from linear. The more the non-gaussianity of the MAX output, the worse the linearity of such QQ-Plot. Since the linearity of the QQ-Plot can be quantitatively represented by the linear correlation coefficient of the QQ-Plot, the Gaussianity of the output of the MAX operator can be statistically and quatitatively measured. However, it will be very expensive if we run extensive Monte Carlo simulation during every step of MAX operation in timing analysis. It is desirable to establish a more convenient criteria to determine the linearity of the MAX operator.

32 Skewness of the MAX Output Non-Linearity of the MAX Operator Figure 2.1: Skewness of Z = max(x, Y ) given X and Y are Gaussian v.s. Non-Linearity of MAX Operator Determined by Monte Carlo simulation It is well known that skewness is not a Gaussianity index for a general random variable since there are distributions which are symmetric but non-gaussian. However, to measure the linearity of the MAX operator with Gaussian inputs, skewness of the MAX output will be a good choice. Figure 2.1 shows the relationship between the non-linearity of the MAX operator and the skewness of Z = max(x, Y ) for Gaussian inputs X and Y. The scattering points in the figure represent 1000 random samples of the relative mean, relative variance and the correlation of Gaussian random variables X and Y. The non-linearity of the MAX operator for each set of randomly sampled mean, variance and correlation is determined by QQ-Plot method with 10,000 Monte Carlo simulations. It is very clear in the figure that the skewness of the MAX output has significant positive dependency on the non-linearity of the MAX operator. Since skewness of the MAX output given Gaussian inputs can be analytically computed by equations developed by Clark [11], it is suitable to use skewness as an accurate and efficient measurement for the non-linearity of the MAX operator.

33 Non-Linear Condition It is clear that the linearity of the MAX operator is heavily dependent on its input parameters. Since we have a good measure of the linearity of the MAX operator, it is ready to study how the linearity changes when inputs vary. Skewness of max(x,y) 1 Skewness of max(x,y) Skewness Std of X [ σ ] Std of X [ σ ] 0 10 Mean of X [ µ ] Mean of X [ µ ] (a) 3D plot at ρ =0 (b) Contour plot at ρ =0 1 Skewness of max(x,y) 1 Skewness of max(x,y) Std of X [ σ ] Std of X [ σ ] Mean of X [ µ ] Mean of X [ µ ] (c) Contour plot at ρ = 0.5 (d) Contour plot at ρ =0.5 Figure 2.2: Skewness of max(x, Y ) when Y N(0, 1) Assuming the standard deviations σ Y σ X in max(x, Y ), then no generality will be lost if the two variances are assumed to be: σ X = σ [0, 1] and σ Y =1. This simplification is valid because of the scaling property of the MAX operator: max(cx, cy ) =c max(x, Y ) for any positive constant c. Aware the invariance of the MAX operator in the constant shifting as max(x, Y )+c = max(x + c, Y + c), both random variables of X and Y are shifted by the mean

34 21 of Y and so that the mean parameters will satisfy the range of µ X = µ and µ Y =0. The last parameter that needed to specify the two input random variables involved in a MAX operation is their correlation coefficient ρ which must be in the range of 1 ρ 1. With such parameter settings, the two Gaussian random variables X and Y are fully determined. And the skewness of Z = max(x, Y ) are computed using equations developed by Clark [11] and are shown in Figures 2.2. From figures 2.2, it is clear that in most of the cases, the skewness is zero which means Z = max(x, Y ) is normally distributed and MAX operator is linear. As a thumb rule, the non-linearity of MAX operator is significant when the following Non-Linear Condition satisfies: Given X and Y are Gaussian, max(x,y) will be significantly non-gaussian if X and Y have very similar mean but very different variance or if X and Y have similar mean and variance but very negative correlation Circuit Timing with Max Tuples If during a timing propagation step of MAX, max(x, Y ), the output arrival time is not Gaussian, no actual computation will be done and the MAX output will be simply recorded as a data structure called max tuple: Mt{X, Y }. With such max tuples, the arrival time propagation will have the following computations: ADD: a gate/wire delay, D, is added into a max tuple Mt{X, Y } as: Mt{X, Y } + D = Mt{X + D, Y + D} amax: an arrival time, A, is MAXed with a max tuple Mt{X, Y } as: max(a, Mt{X, Y }) =Mt{A, X, Y } tmax: two max tuples are MAXed together: max(mt{x, Y },Mt{U, V }) =Mt{X, Y, U, V }

35 22 To practically implement such tuple-based MAX evaluation, the number of arrival times in the max tuple, i.e. the tuple size, has to be maintained as small as possible. This is realized by the obvious associative rule of max tuple as: Mt{A, X, Y } = Mt{max(A, X),Y} = Mt{A, max(x, Y )} = Mt{X, max(a, Y )} so if any two Gaussian random variables in the max tuple doesn t satisfy the non-linear condition, then they can be replaced by a new Gaussian random variable by approximating the MAX with a linear operator and so that the size of the max tuple is reduced. This reduction process will be done iteratively to minimize the tuple size. Such kind of tuple size reduction method is realized by associating each max tuple with a skewness matrix which stores the output skewness if pairs of random variables in the max tuple are actually MAXed out. And also a threshold of skewness κ th is set before-hand to decide if the MAX result is Gaussian or non-gaussian. Also, to prevent the explosion of the tuple size, a safe-guard maximum allowed size for max tuple is also set and if any of the tuple size exceeds the maximum size, the skewness threshold will be increased to tolerate more tuple size reduction. Finally, in the primary output of the circuit, if the circuit delay is reported as max tuple, the output distribution can be easily evaluated by Monte Carlo simulation. For limited size of max tuple, such evaluation is efficient and accurate. 2.3 Statistical Timing Algorithm Before timing analysis, the delay sensitivities of each individual gate/wire are extracted from its Spice model and a gate/wire delay library is then formed. This library, together with the circuit being analyzed, serves as the input of the SSTA algorithm. A SSTA algorithm will then calculate the distributions for all arrival times in the entire circuit by carrying out ADD and MAX operation at each gate/wire block. The overall data flow of the algorithm is summarized in figure 2.3 where the timing graph in the SSTA is represented by a file with standard delay variance correlation format(sdvcf) where both gate/wire delay sensitivities and connections among gate/wires are specified.